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| Monday July 3rd |
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8:30-8:45 |
Welcome |
8:45- 9:30 |
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Keynote
Towards a front-end flow and design methodology for dynamically reconfigurable systems
J. Manuel Moreno Arostegui
Technical university of Catalunya, Spain |
9:30-10:10 |
Session 1: Reconfigurable Architectures
Session Chair: Peter Zipf |
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9:30-9:50 |
A Coarse-Grain Reconfigurable Machine With Floating-Point Arithmetic Capabilities
Claudio Brunelli, Fabio Garzia, Jari Nurmi
Tampere University of Technology, Finland |
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9:50-10:10 |
Data Transfer Protocols for a Two Slot Based Reconfigurable Platform
Alexander Warkentin, Florian Dittmann
Universität Paderborn, Germany |
10:10-10:50 |
Coffee Break & Poster Session |
10:50-11:50 |
Session 2: Applications of Reconfigurable Communication-centric SoCs
Session Chair: Eduardo de la Torre |
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10:50-11:10 |
A Reconfigurable Multi-Processor Platform for Convolutional and Turbo Decoding
Timo Vogt, Christian Neeb, Norbert Wehn
University of Kaiserslautern, Germany |
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11:10-11:30 |
MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation
A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin-Avot, R. Labayrade
Universite Paris VI, France |
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11:30-11:50 | A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template
Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Juergen Teich
University Erlangen-Nuremberg, Germany |
11:50-13:30 |
Lunch |
13:30-14:10 |
Session 3: Compilation and Programmability
Session Chair: Leandro Soares Indrusiak |
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13:30-13:50 |
Compilation Techniques for Configurable Architectures
Alberto Gallini, Alberto Rosti, Sara Bocchio
STMicroelectronics, Italy |
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13:50-14:10 |
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures
C. Morra, M. Sackmann, J. Becker, R. Hartenstein
Universität Karlsruhe, Germany |
14:10-15:30 |
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Panel Session
FPGA: Evolution or Revolution
Maxime Rocca, Xilinx, France
Patrizio Piasentin, Actel, France
Laurent Rougé, Menta, France
Xavier Mathes, Synplicity, France
Moderator : Lionel Torres, LIRMM, France |
15:30-16:00 |
Coffee Break & Poster Session |
16:00-17:00 |
Session 4: Security Issues in ReCoSoC Platforms
Session Chair: Francois Verdier |
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16:00-16:20 |
How to Secure Embedded Programmable Gate Arrays ?
N. Valette, L. Torres, G. Sassatelli, S. Bancel
STMicroelectronics, France
LIRMM, University of Montpellier II, France |
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16:20-16:40 |
Secure architecture in embedded systems: an overview
Romain Vaslin Guy Gogniat Jean-Philippe Diguet
University of South Brittany, France |
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16:40-17:00 |
Efficient combination of data encryption and integrity checking for embedded systems
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez
LIRMM, University of Montpellier II, France
STMicroelectronics, France |
19:00 |
Dining cocktail |
| Tuesday July 4th |
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8:45-9:30 |
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Keynote
Actel embedded FPGA
Fabrizio Piasentin
Actel, Country manager, France |
9:30-10:10 |
Session 5: Low Power Techniques
Session Chair: Michel Paindavoine |
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9:30-9:50 |
Mixed Gates: Leakage Reduction techniques applied to Switches for Networks-on-Chip
Frank Sill, Claas Cornelius, Stephan Kubisch, Dirk Timmermann
University of Rostock, Germany |
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9:50-10:10 |
Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design
Eric Senn, Nathalie Julien, David Elleouet, Yannig Savary, Nabil Abdelli
University of South Brittany, France
IETR Rennes, France
CEA LIST/LCEI, France
Thales Communications, France |
10:10-10:40 |
Coffee Break & Poster Session |
10:40-12:00 |
Session 6: Partial and Dynamic Reconfiguration
Session Chair: Gilles Sassatelli |
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10:40-11:00 |
Partial Reconfiguration for Core Reallocation and Flexible Communications
Yana E. Krasteva, Eduardo de la Torre, Teresa Riesgo
Universidad Politécnica de Madrid, Spain |
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11:00-11:20 |
Clear stream towards dynamically reconfigurable systems on chip
Nicolas Abel, Lounis Kessal, Sebastien Pillement, Didier Demigny
ENSEA, France
IUT Lannion, France |
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11:20-11:40 |
A Concept for a Profile-based Dynamic Reconfiguration Mechanism
Heiko Hinkelmann, Peter Zipf, Manfred Glesner
Technische Universität Darmstadt, Germany |
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11:40-12:00 |
Resource Management for Dynamic Reconfigurable Hardware Structures
Andreas Kühn, Felix Madlener, Sorin A. Huss
Technische Universität Darmstadt, Germany |
12:00-12:40 |
Session 7: Novel FPGA Architectures
Session Chair: Peeter Ellervee |
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12:00-12:20 |
Performance improvement of FPGA using novel multilevel hierarchical interconnection structure
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot
Universite Paris VI, France
CEA, France |
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12:20-12:40 |
Remanent SRAM Structure for Runtime Reconfigurable FPGA
N. Bruchon, L. Torres, G. Sassatelli, G. Cambon
LIRMM, University of Montpellier II, France |
12:40-14:10 |
Lunch |
14:10-15:30 |
Session 8: System Level Design Flows: Open Issues and Case Studies
Session Chair: Norbert Wehn |
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14:10-14:30 |
Towards a SystemC TLM based Methodology for Platform Design and IP Reuse: Application to Software Defined Radio
Grégory Gailliard, Bertrand Mercier, Michel Sarlotte, Bernard Candaele, François Verdier
Thales Communications, France
ENSEA, France |
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14:30-14:50 |
An approach to Co-design of Complex Adaptive Systems
C.A. DeJuan-Esteban, A. Rosado-Muñoz, E. Soria-Olivas, M. Bataller-Mompeán, J. Guerrero-Martínez
University of Valencia, Spain |
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14:50-15:10 |
FPGA Based Emulation Environment
Gert Jervan, Anton Arhipov, Peeter Ellervee
Tallinn University of Technology |
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15:10-15:30 |
Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding
Erwan Piriou, Christophe Jego, Patrick Adde, Michel Jezequel
ENST Bretagne, France |
15:30-16:10 |
Session 9: Exploring Parallelism in ReCoSoC Platforms
Session Chair: Pascal Benoit |
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15:30-15:50 |
Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms
Hua Zhong, Leandro Soares Indrusiak, Heiko Hinkelmann, Manfred Glesner
Technische Universität Darmstadt, Germany |
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15:50-16:10 |
Control unit for parallel embedded system
Stéphane Chevobbe, Raphael David, Frederic Blanc, Thierry Collette, Olivier Sentieys
CEA, France
IRISA, France |
16:10-16:50 |
Departure to the beach |
16:50-19:30 |
Discussions and Drinks on the beach |
19:30 |
Social Event |
| Wednesday July 5th |
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9:00-10:40 |
Session 10: Applications in Image Processing and Telecom
Session Chair: Javier Calpe |
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9:00-9:90 |
Design of a 10000 frames/s CMOS sensor with in situ image processing
Jerome Dubois, Dominique Ginhac, Michel Paindavoine
Universite de Bourgogne, France |
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9:20-9:40 |
Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations
Kurt Ackermann, Friedhelm Mayer, Leandro Soares Indrusiak, Manfred Glesner
Technische Universität Darmstadt, Germany
VITRONIC GmbH, Germany |
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9:40-10:00 |
SystemC design of a smart camera
Barthelemy Heyrman, Michel Paindavoine
Universite de Bourgogne, France |
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10:00-10:20 |
A Comparison Between NoC and Bus Architectures Based on a Real-Application
D. Puschini, F. Clermidy
CEA-LETI, France |
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10:20-10:40 |
Embedded system prototyping experience using multi-DSPs VHDL model
Vincent Brost, Fan Yang, Michel Paindavoine
Université de Bourgogne, France |
10:40-11:10 |
Coffee Break & Poster Session |
11:00-12:20 |
Panel Session
Upcoming challenges for future reconfigurable systems: Architectures, programming tools and technologies
Moderator: Michel robert, LIRMM, France |
12:20-12:50 |
Closing Session |
12:50-14:30 |
Lunch |
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| Posters |
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A Low Speed Digital Correlator Architecture Optimized For Resource Savings
J. Khan, Y. Elhillali, S.Niar, A. Rivenq
Université de Valenciennes et du Hainaut Cambresis (UVHC), France
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Integrated Evaluation Platform for Secured Devices
Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Assia Tria, Bruno Robisson, Jérôme Quartana and Selma Laabidi
CEA-LETI and Ecole Nationale Supérieure des Mines de St Etienne, France
SESAM Laboratory (joint R&D team CEA-LETI/EMSE)
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A Parallel and Secure Architecture for Asymmetric Cryptography
Benoît Badrignans, Daniel Mesquita, Jean-Claude Bajard, Lionel Torres, Gilles Sassatelli, Michel Robert
NETHEOS and LIRMM, University of Montpellier II, France
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FPGA Implementation of a Digital Jitter Measurement Method for SDH Data Streams
Jan Borgosz
University of Science and Technology, Kraków, Poland
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Power Macromodeling for High Level Power Estimation
Yaseer A. Durrani Teresa Riesgo
Universidad Politécnica de Madrid, Spain
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A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications
E. Faure, A. Greiner, D. Genius
Laboratoire LIP6/ASIM, Université Pierre et Marie Curie, France
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Flexible security and its technology limits
Viktor Fischer
LTSI, Jean Monnet University St.-Etienne,France
Lionel Torres, Daniel Mesquita
LIRMM, Univerisity of Montpellier II, France
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