GENERAL INFORMATION
Scope
VLSI-SOC 2001 is the 11th in a series of biennial international conferences on Very Large Scale Integration Systems and their designs, sponsored by IFIP TC 10 Working Group 10.5 (VLSI). Previous conferences have taken place in Edinburgh, Trondheim, Tokyo, Vancouver, Munich, Grenoble, Gramado and Lisbon. The next edition of the IFIP VLSI conference will be held in Montpellier, December 2001. It is organized by LIRMM ( Univ. Montpellier II ).
The purpose of the Conference is to provide a forum to exchange ideas and to show industrial and research results in the field of microelectronics design. All aspects of Microelectronics Design and Test are within the scope of the Conference.
Areas of interest
VLSI-SOC 2001 will be organized around two tracks: IP Core, Circuit and System Designs & Applications, and SOC Design Methods and CAD. Topics of interest include but are not limited to:
1. IP Core, Circuit and System Designs
Panels, embedded tutorials and
hot-topic sessions will discuss new trends, can be visionary
and/or controversial. A one-page abstract must be submitted.
Please contact
B. Rouzeyre or
C. Piguet
for any information and proposal. Capital of the
Languedoc-Roussillon, Montpellier has for centuries been a city where different
cultures meet. Today, it is a dynamic economy in which art and
science go hand in hand with advanced technology and the superb
Mediterranean style-life. Part of the great European Medieval
City tradition, open to the world, linked as much to the
Mediterranean as to northern Europe, it is forever welcoming and
assimilating new ideas, a melting pot of all that is best in
today's civilisation. Montpellier is both a city dedicated to
building a new Europe, and one of the southern Europe's main
metropolises. Montpellier is connected by 10 flights/day with
Paris airports.
1.1. Analog and Mixed-Signal IC Design
2. CAD & CAT Methods and Tools
1.2. Digital IC Design
1.3. Digital Signal Processing and Image Processing IC Design
1.4. Telecommunication Circuits and Applications
1.5. Special Architectures
1.6. Hardware Reconfiguration (FPGA-based circuits, systems & applications)
1.7. Micromechanical Systems
1.8. Systems On Chip (embedded systems, IPs, ...)
2.1. Modeling and Simulation
2.2. Deep Submicron Design & Modeling Issues
2.3. Verification
2.4. Low-Power Issues
2.5. Logic and High-Level Synthesis
2.6. Prototyping and Validation
2.7. Testability and Test
Special Sessions
Deadlines and Key Dates
May 27, 2001
June 15, 2001
July 20, 2001
September 28, 2001
Location :
Le Corum
, Montpellier