| 9:00 - 9:45 |
PLENARY SESSION C |
| |
Low-Voltage Embedded-RAM Technology: Present and Future
|
| |
K. Itoh, Hitachi
|
| |
|
|
| |
|
|
| |
Abstract |
| |
First, key issues for low-voltage (0.3 - 1V) embedded RAMs are summarized in terms of both stable operation and speed variation of memory cells and peripheral logic circuits against increases in leakage currents (gate-tunneling/subthreshold currents), variations of design parameters such as VT, and soft-errors.
Next, DRAM and SRAM cells to cope with the above issues, the circuit design and testing methodology focusing on subthreshold-current issue (such as dynamic circuits with a level holder, VBB dynamic control, gate-source back-biases, and IDDQ testing), suppression of or compensation for design-parameter variations to reduce the speed variations, and voltage converters for multi-supply voltage blocks are discussed, clarifying their limitations and challenges.
Finally, based on the above discussions, a perspective is given with emphasis on needs for simple/high signal-to-noise ratio memory cells (such as gain cells) with a pure logic compatible process, high-speed subthreshold-current reduction focusing on active mode, and memory-rich SOC architectures.
|
| |
|
|
| |
|
|
| |
Speaker's Biography |
| |
Dr. Kiyoo Itoh received the B.S. and Ph.D. Degrees in Electrical Engineering from Tohoku University, Japan, in 1963 and 1976. He is currently one of two Hitachi Fellows. He was a Visiting MacKay Lecturer at the University of California at Berkeley in 1994, a Visiting Professor of University of Waterloo, Canada, in1995, and is now a Consulting Professor at Stanford University.
Since 1972 he has led memory (especially DRAM) technology at Hitachi Ltd. He was the lead designer of the first prototype for eight generations of Hitachi DRAMs ranging from 4Kb to 64Mb. In addition, as a pioneer he has led low-power/low-voltage CMOS circuits focusing on subthreshold current reduction since as early as 1988.
He holds over 140 patents in both Japan and the US. The most important one is the folded data (or bit)-line circuit for DRAMs, invented in 1974. This circuit has become the universal approach in DRAMs because of its noise suppression and Vcc/2 sensing ability.
He and his team have led the developments of DRAM technology and low-voltage CMOS circuits through over 110 IEEE papers and presentations. He has authored and co-authored three books; VLSI Memory Design (Baifukan, in Japanese) in 1994, Low Power Design Methodology (Kluwer Academic Publishers) in 1995, and VLSI Memory Chip Design (Springer-Verlag) in 2001. Dr. Itoh has won many honors, including the IEEE Paul Rappaport Award in 1984, the Best Paper Award of the ESSCIRC90, and the 1993 IEEE Solid-State Circuits Award. He is an IEEE Fellow. In Japan, his awards include the Prize of the Governor of Tokyo in 1988; the National Invention Award in 1989; the Commendation by the Minister of State for Science and Technology (Person of Scientific and Technological Merits) in 1997, and a National Medal of Honor with Purple Ribbon in 2000.
|
| |
|
|
|
