Electrical Behavior of GOS Fault affected Domino Logic Cell
M. Comte (1), S. Ohtake (1), H. Fujiwara (1), M. Renovell (2)

(1) Graduate School of Information Science, Nara Institute of Science and Technology (NAIST), Japan. email: comte, ohtake, fujiwara@is.naist.jp
(2) Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM), France. email: renovell@lirmm.fr

Topic: Testing, Characterisation Testing, Performance Mo

Keywords: Domino logic, Gate-Oxide Short (GOS), Defect modeling, Electrical analysis Boolean test.

Abstract: Gate-Oxide Shorts (GOS) have an increasing impact on the integrated circuit production yield due to the reduction of the related dimensions. The detection of GOS is a challenging issue in the field of testing. This paper presents a detailed study of the impact of a GOS fault affecting a Domino logic circuit. Indeed, Domino logic specific clocked operating principle induces a different behavior from standard full CMOS cells under the effect of a GOS, which can enable GOS detection. Finally, some clues to enhance GOS detection in Domino cells are proposed.