Estimating Arithmetic: Hardware Designs and Applications

There are some computing applications where close enough is good enough.
Digital computer arithmetic design conventionally focuses on accuracy and then cost; however there are applications where speed, size and power efficiency are critical and errors, even gross errors, can be tolerated. We are currently working to design novel arithmetic hardware and to demonstrate its use in proof of concept designs. This seminar will present our most promising results to date: estimating adders and multi-operand adders and their use in a low density parity check (LDPC) decoder and a general purpose processor with speculative execution. The LDPC decoder has improved latency, area and power for little cost in terms of error performance. The general purpose processor promises improved throughput. Future directions for the work will be presented.

Short Bio: Braden Phillips is a lecturer in the School of Electrical and Electronic Engineering at the University of Adelaide. Prior to the completion of his PhD thesis, ’An Optimised Implementation of Public Key Cryptography for Smart Card Processors’, Braden worked as a process control engineer and was a founding partner in Current Dynamics, an electronic hardware design venture. In September 2000 he took up a lecturing position at Cardiff University in South Wales, a post he held for 2 years before returning to Adelaide. Braden’s research interests include digital arithmetic, digital microelectronics, computer architecture, real time systems and information security.

Contact: phillips@eleceng.adelaide.edu.au