Actualités
MAJ : 01/07/2009
Seminar
Pr. Juergen Becker, Karlsruhe University
EVOLVABLE RECONFIGURABLE COMPUTING SYSTEMS
July 2nd, 2009
4:00 pm
Seminars room, LIRMM
Abstract
The field of parallel embedded electronic systems is still emerging. Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore´s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. My view is of an “all-win-symbiosis” of future silicon-based processor technologies and parallel multi-core as well as reconfigurable circuits/architectures.
Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future systems. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter the so-called Nano Era. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), nano circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. The deployment of new 3-D nano structures and materials promises higher integration densities and is considered advantageous for signal delays. Yield is significantly lower, and could, as we define it in the classical sense, eventually be nil! Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. Thus, novel design methodologies, novel adaptive mechanisms which solve operation-time shortcomings, and novel computing paradigms are necessary. Fault tolerance/correction in all its facets is key and should be considered an inherent technique in any nano design/synthesis step.
This keynote will discuss the corresponding challenges and outline some arising perspectives for future multi-core and adaptive as well as reliable systems-on-chip (MCSoC), for application-tailored embedded and general purpose systems.
Bio
Juergen Becker received the Diploma degree in 1992, and his Ph.D. (Dr.-Ing.) degree in 1997, both at Kaiserslautern University, Germany. His research work focused on application development environments for reconfigurable accelerators and included hardware/software codesign, parallelizing compilers, customized computing, and high-level synthesis. He has been local administrator for the European Design Project EUROCHIP in 1993/95. In 1997 Dr. Becker joined the Institute of Microelectronic Systems at Darmstadt University of Technology, Germany, as assistant professor, where he taught CAD algorithms for VLSI design. He did research in Systems-on-Chip (SoC) architectures and reconfigurable technologies for mobile communication systems, including the development of corresponding IP-based CAD methods. Since 2001 Juergen Becker is professor for embedded electronic systems at the Institut fuer Technik der Informationsverarbeitung (ITIV) at the University of Karlsruhe. He gives lectures in digital design (undergraduate), in CAD algorithms for high-level synthesis and VLSI design, hardware/software codesign, as well as in bus interfaces and protocols. His actual research is focused on industrial-driven SoCs with emphasis on adaptive embedded systems, e.g. dynamically reconfigurable hardware architectures. This includes corresponding hardware/software codesign and co-synthesis techniques from high-level specifications, as well as low power SoC optimization. Prof. Becker is managing co-director of the International Department at the University of Karlsruhe and co-director of the Electronic Systems and Microsystems (ESM) group at the Computer Science Research Center (FZI) at the University of Karlsruhe. He is author and co-author of more than 100 scientific papers, published in peer-reviewed international journals and conferences and active in several technical program and steering committees of international conferences and workshops. He is a Member of the german GI and Senior Member of the IEEE. Prof. Becker is chair of the GI/ITG Technical Committee of 'Architekturen fuer hochintegrierte Schaltungen' and is member of "Editorial Board of IEEE Transaction on Computers" and "Executive Committee der Deutschen Sektion des IEEE". Prof. Becker starts in October 2004 as Vice President of Universität Karlsruhe (TH) responisble for the aresa Studies and Teaching.
EVOLVABLE RECONFIGURABLE COMPUTING SYSTEMS
July 2nd, 2009
4:00 pm
Seminars room, LIRMM
Abstract
The field of parallel embedded electronic systems is still emerging. Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore´s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. My view is of an “all-win-symbiosis” of future silicon-based processor technologies and parallel multi-core as well as reconfigurable circuits/architectures.
Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future systems. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter the so-called Nano Era. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), nano circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. The deployment of new 3-D nano structures and materials promises higher integration densities and is considered advantageous for signal delays. Yield is significantly lower, and could, as we define it in the classical sense, eventually be nil! Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. Thus, novel design methodologies, novel adaptive mechanisms which solve operation-time shortcomings, and novel computing paradigms are necessary. Fault tolerance/correction in all its facets is key and should be considered an inherent technique in any nano design/synthesis step.
This keynote will discuss the corresponding challenges and outline some arising perspectives for future multi-core and adaptive as well as reliable systems-on-chip (MCSoC), for application-tailored embedded and general purpose systems.
Bio
Juergen Becker received the Diploma degree in 1992, and his Ph.D. (Dr.-Ing.) degree in 1997, both at Kaiserslautern University, Germany. His research work focused on application development environments for reconfigurable accelerators and included hardware/software codesign, parallelizing compilers, customized computing, and high-level synthesis. He has been local administrator for the European Design Project EUROCHIP in 1993/95. In 1997 Dr. Becker joined the Institute of Microelectronic Systems at Darmstadt University of Technology, Germany, as assistant professor, where he taught CAD algorithms for VLSI design. He did research in Systems-on-Chip (SoC) architectures and reconfigurable technologies for mobile communication systems, including the development of corresponding IP-based CAD methods. Since 2001 Juergen Becker is professor for embedded electronic systems at the Institut fuer Technik der Informationsverarbeitung (ITIV) at the University of Karlsruhe. He gives lectures in digital design (undergraduate), in CAD algorithms for high-level synthesis and VLSI design, hardware/software codesign, as well as in bus interfaces and protocols. His actual research is focused on industrial-driven SoCs with emphasis on adaptive embedded systems, e.g. dynamically reconfigurable hardware architectures. This includes corresponding hardware/software codesign and co-synthesis techniques from high-level specifications, as well as low power SoC optimization. Prof. Becker is managing co-director of the International Department at the University of Karlsruhe and co-director of the Electronic Systems and Microsystems (ESM) group at the Computer Science Research Center (FZI) at the University of Karlsruhe. He is author and co-author of more than 100 scientific papers, published in peer-reviewed international journals and conferences and active in several technical program and steering committees of international conferences and workshops. He is a Member of the german GI and Senior Member of the IEEE. Prof. Becker is chair of the GI/ITG Technical Committee of 'Architekturen fuer hochintegrierte Schaltungen' and is member of "Editorial Board of IEEE Transaction on Computers" and "Executive Committee der Deutschen Sektion des IEEE". Prof. Becker starts in October 2004 as Vice President of Universität Karlsruhe (TH) responisble for the aresa Studies and Teaching.
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auteur :
Caroline Imbert
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