Nadine AZEMARD-CRESTANI   CNRS Researcher   Research Activities     Technological Assignment for Low Power : Performance Modelisation and Optimisation Delay and Power Modelisation in Submicronic CMOS Technology Delay-Power Optimisation Tool Development for Combinatorial Path Analysis - Path Classification - Critical Path Search - Performance Optimisation under Constraints - Path and Gate Sensibility - Bufferisation and Logic Restructuration - Convergence and Divergence Branches Management Technological Migration Delay Budgetisation DFM : Statistical Approach and Asynchronous Circuits Static analysis and Optimisation of Circuit Performances Optimisation and Design of Asynchronous Circuits