Books
.
[1]
S. Bernard, D. Guiraud, C. Azevedo, and D. Andreu,
“Principe de la stimulation électrique fonctionnelle. Exemples
d’application thérapeuthique,” in
Techniques de l’Ingénieur, vol.
RE127, p. 12, 2009.
.
[2]
F. Soulier, L. Gouyet, G. Cathébras, S. Bernard, D.
Guiraud, and Y. Bertrand, “Multipolar Electrode and Preamplifier
Design for ENG-Signal Acquisition,” in Biomedical Engineering
Systems and Technologies, vol. 25 of Communications in Computer
and Information Science, pp. 148–159, Springer, 2008.
[3] S. Bernard, P. Cauvet, and M.
Renovell, “SIP Test Architectures,” in System-on- chip Test
Architectures : Nanometer Design for Testability (Morgan Kaufmann
Publishers, ed.), pp. 405–441, Elsevier, Nov. 2007.
[4] F. Azaïs, S. Bernard, Y. Bertrand, M.
Flottes, P. Girard, C. Landrault, L. Latorre, S.
Pravossoudovitch, M. Renovell, and B. Rouzeyre, Test de Circuits
et de Sys- tèmes Intégrés. Collection EGEM, Ed.Hermès, 2004.
[5]
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell, “On-Chip
Generator of a Saw- Tooth Test Stimulus for ADC BIST,” in SoC
Design Methodologies - 11th Interna- tional Conference on Very
Large Scale Integration of Systems-on-Chips, pp. 425– 436,
Kluwer Academic Publishers, 2002.
Journals
.
[6]
P. Auvray, L. Rousseau, G. Lissorgues, F. Soulier, O.
Potin, S. Bernard, F. Dieu- leveult, E. Scorsone, P. Bergonzo, L.
Chicaud, et al., “A passive pressure sensor for continuously
measuring the intraocular pressure in glaucomatous patients,”
IRBM, 2012.
.
[7]
V. Kerzérho, M. Comte, F. Azaïs, P. Cauvet, S. Bernard, and
M. Renovell, “Digital Test Method for Embedded Converters with
Unknown-Phase Harmonics,” Journal of Electronic Testing : Theory
and Application (JETTA), June 2011, Vol. 27, Issue 3, pp.
335-350, 2011.
.
[8]
V. Kerzérho, V. Fresnaud, D. Dallet, S. Bernard, and L.
Bossuet, “Fast Digital Post-Processing Technique for INL
Correction of ADC : Validation on a 12-bit F&I ADC,” IEEE
Transactions on Instrumentation & Measurement, pp.
768–775, 2010.
.
[9]
L. Gouyet, G. Cathebras, S. Bernard, F. Soulier, D.
Guiraud, and Y. Bertrand, “Am- plificateur faible-bruit dédié à
l’enregistrement d’ENG à partir d’une électrode cuff hexagonale,”
revue de l’électricité et de l’électronique, vol. 06-07, June
2009.
.
[10]
V. Kerzérho, P. Cauvet, S. Bernard, F. Azais, M. Renovell,
M. Comte, and O. Cha- kib, “ADC Production Test Technique Using
Low-Resolution Arbitrary Waveform Generator,” VLSI Design, vol.
2008, no. Article ID 482159, p. 8, 2008.
.
[11]
V. Kerzérho, P. Cauvet, S. Bernard, F. Azais, M. Comte, and
M. Renovell, “Fully Digital Test Solution for a Set of ADCs and
DACs embedded in a SiP or SoC,” IET Computers & Digital
Techniques, vol. 1, pp. 146–153, May 2007.
.
[12]
V. Kerzérho, P. Cauvet, S. Bernard, F. Azais, M. Comte, and
M. Renovell, “A Novel DFT Technique to Test a Complete Set of
ADC’s and DAC’s Embedded in a Com- plex SiP,” IEEE Design &
Test of Computers (D&T), vol. 23, pp. 237–243, June
2006.
.
[13]
V. Kerzérho, S. Bernard, P. Cauvet, and J.-M. Janik, “A
First Step for an INL Spectral-Based BIST : The Memory
Optimization,” Journal of Electronic Testing : Theory and
Application (JETTA), vol. 22, no. 4-6, pp. 351–357, 2006.
.
[14]
F. Azaïs, S. Bernard, M. Comte, Y. Bertrand, and M.
Renovell, “Efficiency of Op- timized Dynamic Test Flows for ADCs
: Sensitivity to Specifications,” Journal of Electronic Testing :
Theory and Application (JETTA), vol. 21, no. 3, pp.
291–298, 2005.
.
[15]
P. Puyal, A. Konczykowska, P. Nouet, S. Bernard, S. Blayac,
F. Jorge, M. Riet, and J. Godin, “DC-100-GHz Frequency Doublers
in InP DHBT Technology,” IEEE Transactions on Microwave Theory
and Techniques, vol. 53, no. 4, pp. 1338– 1344, 2005.
.
[16]
F. Azaïs, S. Bernard, Y. Bertrand, M. Comte, and M.
Renovell, “Correlation Bet- ween Static and Dynamic Parameters of
A-to-D Converters : In the View of a Unique Test Procedure,”
Journal of Electronic Testing : Theory and Application (JETTA),
vol. 20, no. 4, pp. 375–387, 2004.
.
[17]
S. Bernard, M. Comte, F. Azaïs, Y. Bertrand, and M.
Renovell, “Efficiency of Spectral-based ADC Test Flows to Detect
Static Errors,” Journal of Electronic Testing : Theory and
Application (JETTA), vol. 20, no. 3, pp. 257–267, 2004.
.
[18]
F. Azaïs, S. Bernard, Y. Bertrand, M. Comte, and M.
Renovell, “A-to-D Converter Static Error Detection from Dynamic
Parameter Measurements,” MEJO : Microe- lectronics Journal, vol.
34, no. 10, pp. 945–953, 2003.
.
[19]
S. Bernard, F. AzaÏs, Y. Bertrand, and M. Renovell,
“On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC
BIST,” Journal of Electronic Testing : Theory and Application
(JETTA), vol. 19, no. 4, pp. 469–479, 2003.
.
[20]
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell, “Analog
Built-In Saw-Tooth Generator for ADC Histogram Test,” MEJO :
Microelectronics Journal, vol. 33, no. 10, pp. 781–789,
2002.
.
[21]
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell, “A
Low-Cost BIST Architecture for Linear Histogram Testing of ADCs,”
Journal of Electronic Testing : Theory and Application (JETTA),
vol. 17, pp. 139–147, April 2001.
.
[22]
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell,
“Optimizing Sinusoidal Histo- gram Test for Low Cost ADC BIST,”
Journal of Electronic Testing : Theory and Application (JETTA),
vol. 17, pp. 255–266, August 2001.
Patents
.
[23]
D. Andreu, M. Flottes, P. Cauvet, Z. Noun, and S. Bernard,
“System and method for wirelessly testing integrated circuits,”
US Patent US2011/0 244 814, 2011.
.
[24]
D. Guiraud, D. Andreu, J. Galy, Y. Bertrand, C. Cathebras,
J. Techer, and S. Ber- nard, “Device for Distributing Power
between Cathodes of a Multipolar Elec- trode, in Particular of an
Implant,” WO Patent WO/2006/027473 extension de FR04 09 351,
2006.
.
[25]
M. Renovell, F. Azaïs, S. Bernard, and Y. Bertrand, “Method
and device for inte- grated testing for an analog-to-digital
converter,” US Patent 6,642,870, 2003.
Invited papers
.
[26]
S. Bernard, “Testing SiP and SoC Wirelessly : an utopia ?,” in DTC’12 : European Nanoelectronics
Design Technology Conference, (Grenoble), June 2012.
.
[27]
S. Bernard and O. Romain, “Systèmes embarqués pour la santé
: Quels enjeux & quelles forces en présence,” in Colloque du
GDR SOC-SIP, May 2012.
.
[28]
F. Soulier, S. Bernard, G. Cathébras, and D. Guiraud,
“Advances in Implanted Functional Electrical Stimulation,” in
DTIS’11 : 6th IEEE International Confe- rence on Design and
Technology of Integrated Systems in Nanoscale Era, pp. 11–
17, April 2011.
.
[29]
S. Bernard and P. Cauvet, “Test and Dependability of
Microsystems,” in DTC’10 : European Nanoelectronics Design
Technology Conference, (Grenoble), June 2010.
.
[30]
S. Bernard, “Applications and Challenges of Electrical
Medical Implants,” in DTIS’10 : Design and Test of Integrated
Systems in Nanoscale Tehnology, 2010.
.
[31]
V. Kerzérho, P. Cauvet, S. Bernard, F. Azais, M. Comte, and
M. Renovell, “A Multi-Converter DFT Technique for Complex SIP :
Concepts and Validation,” in ECCTD’09 : European Conference on
Circuit Theory and Design, (Turkey), pp. 747–750, August
2009.
.
[32]
F. Soulier, F. Le Floch, S. Bernard, G. Cathebras, and D.
Guiraud, “New Depen- dability Approach for Implanted Medical
Devices,” in ICM : International Confe- rence on
Microelectronics, (Marrakech), pp. 18 – 21, 2009.
.
[33]
F. Soulier, O. Rossel, S. Bernard, G. Cathebras, and D.
Guiraud, “Design of Nerve Signal Biosensor,” in NEWCAS-TAISA’09 :
North-East Workshop on Circuits and Systems, Traitement
Analogique de l’Information, du Signal et ses Applications, pp.
400–403, 2009.
.
[34]
S. Bernard, “Biomedical Circuits : New Challenges for
Design and Test,” in
IMS3TW’08 : IEEE International
Mixed-Signals, Sensors and Systems Test Work- shop, (Canada),
June 2008.
.
[35]
S. Bernard, J. Palazin, and P. Cauvet, “Testing electronic
chips : Innovation for multimedia, automotive and healthcare
application,” in SERI’08 : European re- search & Innovation
exhibition, (Paris France), June 2008.
.
[36]
S. Bernard, L. Gouyet, G. Cathébras, F. Soulier, D.
Guiraud, and Y. Bertrand, “Low- Noise ASIC and New Layout of
Multipolar Electrode for Both High ENG Selec- tivity and
Parasitic Signal Rejection,” in ICECS’07 : International
Conference on Electronics, Circuits and Systems, pp. 74–77,
Dec. 2007.
.
[37]
S. Bernard and M. Renovell, “State of the Art in SoC
Testing : The Analog Chal- lenge,” in DTIS’06 : Design and Test
of Integrated Systems in Nanoscale Tehno- logy, pp.
100–106, 2006.
International Conferences (A rang)
.
[38]
H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzerho, O.
Potin, and M. Renovell, “Making predictive analog/RF alternate
test strategy independent of training set size,” in ITC’12 :
International Test Conference, pp. 10.1, 1–9, October 2012.
.
[39]
J. Coulombe, O. Rossel, S. Bernard, F. Soulier, and G.
Cathebras, “A New Shared- Input Architecture for Enhanced
Noise-Power Trade-off in Parallel Biosignal Am- plifiers,” in
ISCAS’12 : IEEE International Symposium on Circuits and Systems,
pp. 846–849, 2012.
.
[40]
H. Ayari, F. Azaïs, S. Bernard, M. Comte, M. Renovell, V.
Kerzerho, O. Potin, and C. Kelma, “Smart selection of indirect
parameters for DC-based alternate RF IC testing,” in VTS’12 :
IEEE VLSI Test Symposium, 2012.
.
[41]
F. Le Floch, S. Bernard, G. Bontorin, F. Soulier, and G.
Cathébras, “Global Stra- tegy to Guaranty Dependability of
Electrical Medical Implanted Devices,” in 5th International
IEEE/EMBS Conference on Neural Engineering (NER), (Mexico), pp.
515 – 518, may 2011.
.
[42]
O. Rossel, F. Soulier, S. Bernard, and G. Cathebras,
“Sensitivity of a Frequency- Selective Electrode Based on Spatial
Spectral Properties of the Extracellular AP of Myelinated Nerve
Fibers,” in EMBC’11 : 33rd Annual International Conference of the
IEEE Engineering in Medicine and Biology Society, (Boston,
États-Unis), pp. 5843–5846, Aug. 2011.
.
[43]
O. Rossel, F. Soulier, J. Coulombe, S. Bernard, and G.
Cathebras, “Fascicle- Selective Multi-Contact Cuff Electrode,” in
EMBC’11 : 33rd Annual International Conference of the IEEE
Engineering in Medicine and Biology Society, (Boston,
États-Unis), pp. 2989–2992, Aug. 2011.
.
[44]
G. Cathébras, F. Le Floch, S. Bernard, and F. Soulier, “Dependability
: a challenge for electrical medical implants,” in EMBC’10 :
Annual International Conference of the IEEE Engineering in
Medicine and Biology Society, pp. 5923–6, 2010.
.
[45]
G. Lissorgues, L. Rousseau, P. Poulichet, L. Valbin, S.
Picaud, L. Chicaud, S. Ber- nard, P. Bergonzo, F. Dedieuleveult,
and P. Auvray, “Continuous Intra Ocular Pres- sure Measurement
Sensor for Glaucoma Diagnostic,” in WCB’10 : 6th World Congress
of Biomechanics. August 1-6, 2010 Singapore, vol. 31 of IFMBE
Pro- ceedings, pp. 1282–1285, Springer, 2010.
.
[46]
O. Rossel, F. Soulier, B. Serge, and C. Guy, “New Electrode
Layout for Internal Selectivity of Nerves,” in EMBC’09 : Annual
International Conference of the IEEE Engineering in Medicine and
Biology Society, pp. 3798 – 3801, 2009.
.
[47]
F. Soulier, O. Rossel, S. Bernard, G. Cathébras, and D.
Guiraud, “An Optimized Layout for Multipolar Neural Recording
Electrode,” in IFESS’09 : Annual Confe- rence of the
International Functional Electrical Stimulation Society,
((Korea)), pp. 56–61, 2009.
.
[48]
Z. Noun, P. Cauvet, M.-L. Flottes, D. Andreu, and S.
Bernard, “Wireless Test Structure for Integrated Systems,” in
ITC’08 : IEEE International Test Confe- rence, p. Poster 25,
2008.
.
[49]
F. Soulier, L. Gouyet, G. Cathébras, S. Bernard, D.
Guiraud, and Y. Bertrand, “Considerations on Improving the Design
of Cuff Electrode for ENG Recording - Geometrical Approach,
Dedicated IC, Sensitivity and Noise Rejection,” in BIO-
DEVICES’08 : International Conference on Biomedical Electronics
and Devices, vol. 2, pp. 180–185, 2008.
.
[50]
F. Soulier, J.-B. Lerat, L. Gouyet, S. Bernard, and G.
Cathebras, “A Neural Stimu- lator Output Stage for Dodecapolar
Electrodes,” in ISVLSI’08 : IEEE Computer Society Annual
Symposium on VLSI, pp. 487–490, April 2008.
.
[51]
S. Bernard, Y. Bertrand, G. Cathébras, L. Gouyet, and D.
Guiraud, “A New Confi- guration of Multipolar Cuff Electrode and
Dedicated IC for Afferent Signal Re- cording,” in EMBC’07 : 3rd
International IEEE/EMBS Conference on Neural En- gineering, pp.
578–581, May 2007.
.
[52]
P. Cauvet, S. Bernard, and M. Renovell, “System-in-Package,
a Combination of Challenges and Solutions,” in ETS’07 : 12th IEEE
European Test Symposium, pp. 193–199, 2007.
.
[53]
V. Kerzerho, P. Cauvet, S. Bernard, F. Azaïs, M. Comte, and
M. Renovell, “"Ana- logue Network of Converters" : a
DFT Technique to Test a Complete Set of ADCs and DACs Embedded in
a Complex SiP or SOC. Best paper ETS’06,” in ETS’07 : 12th IEEE
European Test Symposium, pp. 211–216, 2007.
.
[54]
V. Fresnaud, L. Bossuet, D. Dallet, S. Bernard, J.-M.
Janik, B. Agnus, P. Cauvet, and P. Gandy, “A Low Cost Alternative
Method for Harmonics Estimation in a BIST Context,” in ETS’06 :
IEEE European Test Symposium, pp. 193–198, May 2006.
.
[55]
V. Kerzerho, P. Cauvet, S. Bernard, F. Azaïs, M. Comte, and
M. Renovell, “’Ana- logue Network of Converters’ : A DFT
Technique to Test a Complete Set of ADCs and DACs Embedded in a
Complex SiP or SOC,” in ETS’06 : IEEE European Test Symposium,
pp. 159–164, May 2006.
.
[56]
V. Puyal, A. Konczykowska, M. Riet, S. Bernard, P. Nouet,
and J. Godin, “InP HBT XOR and Phase-Detector for 40Gbit/s Clock
and Data Recovery (CDR),” in MI- KON’06 : International
Conference on Microwaves, Radar & Wireless Communi- cations,
pp. 1115–1118, May 2006.
.
[57]
S. Bernard, J.-D. Techer, G. Cathebras, Y. Bertrand, and D.
Guiraud, “Electrical Performances of a New Multipolar
Micro-Stimulator,” in IFESS’05 : 10th An- nual Conference of the
International Functional Electrical Stimulation Society, pp.
232–234, 2005.
.
[58]
V. Puyal, A. Konczykowska, P. Nouet, S. Bernard, M. Riet,
F. Jorge, and J. Godin,
“A
Broad-band Active Frequency Doubler Operating up to 120 ghz,” in
EuMC’05 : 35th European Microwave Conference, 2005.
.
[59]
V. Puyal, A. Konczykowska, P. Nouet, S. Bernard, S. Blayac,
F. Jorge, M. Riet, and J. Godin, “A DC-100 GHz Frequency Doubler
in InP DHBT Technology,” in IEEE MTT-S International Microwave
Symposium Digest, pp. 167–170, 2004.
.
[60]
J. Techer, S. Bernard, Y. Bertrand, G. Cathébras, and D.
Guiraud, “New Implan- table Stimulator for the FES of Paralyzed
Muscles,” in ESSCIRC’04 : 30th Euro- pean Solid-State Circuits
Conference, pp. 455–458, 2004.
.
[61]
S. Bernard, M. Comte, F. Azaïs, Y. Bertrand, and M.
Renovell, “A New Methodo- logy for ADC Test FLow Optimization,”
in ITC’03 : International Test Conference, pp. 201–209,
September 2003.
.
[62]
S. Bernard, F. Azaïs, Y. Bertrand, and M. Renovell, “A High
Accuracy Triangle- Wave Signal Generator for On-Chip ADC
Testing,” in ETW’02 : IEEE European Test Workshop, pp.
89–94, 2002.
.
[63]
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell,
“Implementation of a linear histogram BIST for ADCs,” in DATE’01
: Design, Automation and Test in Europe, pp. 590–595, 2001.
.
[64]
F. Azaïs, S. Bernard, Y. Bertrand, X. Michel, and M.
Renovell, “A low-cost adap- tive ramp generator for analog BIST
applications,” in VTS’01 : IEEE VLSI Test Symposium, pp.
266–271, 2001.
.
[65]
S. Bernard, F. Azaïs, Y. Bertrand, and M. Renovell, “Analog
BIST generator for ADC testing,” in DFT’01 : IEEE International
Symposium on Defect and Fault Tolerance in VLSI Systems, pp.
338–346, 2001.
.
[66]
F. Azaïs, S. Bernard, Y. Betrand, and M. Renovell, “Towards
an ADC BIST scheme using the histogram test technique,” in ETW’00
: IEEE European Test Workshop, pp. 53–58, 2000.
.
[67]
M. Renovell, F. Azaïs, S. Bernard, and Y. Bertrand,
“Hardware resource minimi- zation for histogram-based ADC BIST,”
in VTS’00 : IEEE VLSI Test Symposium, pp. 247–252, 2000.
International Conferences (B rang)
.
[68] Ayari ; Haithem, F.
Azaïs, S. Bernard, M. Comte, V. Kerzerho, O. Potin, and M. Re-
novell, “On the use of redundancy to reduce prediction error in
alternate ana- log/RF test,” in IMS3TW’12 : International
Mixed-Signals,Sensors and Systems Testing Workshop, pp.
1–5, 2012.
.
[69]
S. Bernard, F. Azaïs, M. Comte, O. Potin, V. Kerzerho, and
M. Renovell, “AdaptiveLUT-Based System for In Situ ADC Auto-correction,”
in IMS3TW’10 : In- ternational Mixed-Signals,Sensors
and Systems Testing Workshop, pp. 1–6, 2010.
.
[70]
V. Kerzerho, F. Azaïs, M. Comte, P. Cauvet, S. Bernard, and
M. Renovell, “ANC-Based Method for Testing Converters with
Random-Phase Harmonics,” in IMS3TW’10 : International
Mixed-Signals,Sensors and Systems
Testing Work- shop, pp. 1–5, 2010.
.
[71]
Z. Noun, P. Cauvet, M.-L. Flottes, D. Andreu, and S.
Bernard, “Wireless Wafer Test for Iterative Testing During System
Assembly,” in 3D-Test : First IEEE In- ternational Workshop on
Testing Three-Dimensional Stacked Integrated Circuits,
(États-Unis), Nov. 2010.
.
[72]
S. Bernard, F. Azaïs, M. Comte, Y. Bertrand, and M.
Renovell, “LH-BIST for Digital Correction of ADC Offset,” in
DTIS’06 : international Conference on Design and Test of
Integrated Systems in Nanoscale Tehnology, pp. 199–203,
2009.
.
[73]
L. Gouyet, G. Cathebras, S. Bernard, F. Soulier, D.
Guiraud, and Y. Bertrand, “Low-Noise Averaging Amplifier
Dedicated to ENG Recording with Hexagonal Cuff Electrode,” in
NEWCAS-TAISA’08 : IEEE Northeast Workshop on Circuits and Systems
-Traitement Analogique de l’Information, du Signal et ses
Applica- tions, pp. 161–164, June 2008.
.
[74]
F. Le Floch, S. Bernard, F. Soulier, and G. Cathébras,
“Dependability for Implan- ted Medical Devices,” in DECIDE’08 :
Second International Workshop on Depen- dable Circuit Design,
Nov. 2008.
.
[75]
Z. Noun, P. Cauvet, M.-L. Flottes, S. Bernard, D. Andreu,
and J. Galy, “Power Supply Investigation for Wireless Wafer
Test,” in LATW’08 : 9th Latin-American Test Workshop, pp.
165–170, March 2008.
.
[76]
L. Gouyet, G. Cathebras, S. Bernard, D. Guiraud, and Y.
Bertrand, “A Cuff Elec- trode Dedicated to ENG Recording with
Multipolar Configuration for Both Effi- cient Sensitivity and
High Rejection of EMG Parasitic Signals,” in 9th Vienna In-
ternational Workshop on Functional Electrical Stimulation, pp.
78–81, Nov. 2007.
.
[77]
V. Kerzerho, P. Cauvet, S. Bernard, F. Azaïs, M. Renovell,
and M. Comte, “Fully- Efficient ADC Test Technique for ATE with
Low Resolution Arbitrary Wave Gene- rators,” in IMSTW’07 :
International Mixed-Signals Testing Workshop, pp. 196– 201,
2007.
.
[78]
S. Bernard, D. Andreu, Z. Noun, M.-L. Flottes, P. Cauvet,
H. Fleury, and F. Verjus, “Testing System-In-Package Wirelessly,”
in DTIS’06 : International Conference on Design and Test of
Integrated Systems in Nanoscale Tehnology (IEEE, ed.), pp.
222–226, 2006.
.
[79]
V. Kerzérho, P. Cauvet, S. Bernard, F. Azaïs, M. Comte, and
M. Renovell, “Ex- perimental Validation of the "Analogue
Network of Converters" Technique to Test Complex SiP/SoC,”
in IMSTW’06 : IEEE International Mixed-Signals Testing Workshop,
pp. 84–88, June 2006.
.
[80]
S. Bernard, M.-L. Flottes, P.
Cauvet, P. Fleury, and F. Verjus, “Testing System-
in-Package Wirelessly,” in LATW’06 : 7th
IEEE Latin American Test Workshop, (Argentina), pp. 73–78,
2006.
.
[81]
S. Bernard, M. Comte, F. Azaïs, Y. Bertrand, and M.
Renovell, “Fast and Fully- Efficient Test Flow for ADCs,” in
IMSTW’05 : 11th IEEE International Mixed- Signals Testing
Workshop, pp. 244–249, 2005.
.
[82]
S. Bernard and P. Cauvet, “Built-in-Test Solutions for
SiP,” in KGD’05 : KGD Pa- ckaging & Test Workshop, pp.
105–109, 2005.
.
[83]
V. Kerzerho, S. Bernard, J. Janik, and P. Cauvet,
“Comparison Between Spectral- Based Methods for INL Estimation
and Feasibility of Their Implantation,” in IM- STW’05 : 11th IEEE
International Mixed-Signal Testing Workshop, pp. 270–275,
2005.
.
[84]
J.-D. Techer, S. Bernard, Y. Bertrand, G. Cathebras, and D.
Guiraud, “An Implan- table Asic for Neural Stimulation,” in IEEE
International Workshop on Biomedical Circuits and Systems, pp.
S1.7.INV–5–8, 2004.
.
[85]
S. Bernard, F. Azaïs, M. Comte, Y. Bertrand, and M.
Renovell, “An Automatic Tool for Generation of ADC BIST
Architecture,” in IMSTW’03 : 9th IEEE International Mixed-Signals
Testing Workshop, (France), pp. 79–84, June 2003.
.
[86]
S. Bernard, F. Azaïs, M. Comte, Y. Bertrand, and M.
Renovell, “Automatic Genera- tion of LH-BIST Architecture for ADC
Testing,” in IWADC’03 : IEEE International Workshop on ADC
Modelling and Testing, (France), pp. 7–12, September 2003.
.
[87]
M. Comte, S. Bernard, F. Azaïs, Y. Bertrand, and M.
Renovell, “A New Methodo- logy for ADC Test Flow Optimization,”
in ETW’03 : IEEE European Test Work- shop, (France), pp.
75–80, May 2003.
.
[88]
M. Comte, F. Azaïs, S. Bernard, Y. Bertrand, and M.
Renovell, “Analysis of the Specification Influence on the
Efficiency of an Optimized Test Flow for ADCs,” in IMSTW’03 : 9th
IEEE International Mixed-Signals Testing Workshop, (France), pp.
185–190, June 2003.
.
[89]
M. Comte, F. Azaïs, S. Bernard, Y. Bertrand, and M.
Renovell, “On the Efficiency of Measuring ADC Dynamic Parameters
to Detect ADC Static Errors,” in LATW’03 : 4th IEEE Latin
American Test Workshop, (France), pp. 198–203, February
2003.
.
[90]
F. Azaïs, S. Bernard, Y. Bertrand, M. Comte, and M.
Renovell, “Evaluation of ADC Static Parameters via Frequency
Domain,” in IMSTW’02 : 8th IEEE International Mixed-Signal
Testing Workshop, (France), pp. 165–169, june 2002.
.
[91]
F. Azaïs, S. Bernard, Y. Bertrand, M. Comte, M. Renovell,
and M. Lubaszewski, “Estimating Static Parameters of A-to-D
Converters from Spectral Analysis,” in LATW’02 : 3rd IEEE Latin
American Test Workshop, (France), pp. 174–179, Fe- bruary
2002.
.
[92]
M. Comte, F. Azaïs, S. Bernard, Y. Bertrand, and M.
Renovell, “On the Evalua- tion of ADC Static Parameters Through
Dynamic Testing,” in ADDA&EWADC’02 :
Advanced A/D and D/A Conversion
Techniques and Their Applications & ADC Modelling and
Testing, (France), pp. 95–98, June 2002.
.
[93]
F. Azaïs, S. Bernard, Y. Bertrand, X. Michel, and M.
Renovell, “On-chip Generation of High-Quality Ramp Stimulus with
Minimal Silicon Area,” in LATW’01 : atin American Test Workshop,
pp. 112–117, 2001.
.
[94]
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell,
“On-Chip Generator of a Saw- Tooth Test Stimulus for ADC BIST,”
in IFIP International Conference on Very Large Scale Integration
The Global System on Chip Design & CAD Conference, pp.
347–352, 2001.
.
[95]
S. Bernard, F. Azaïs, Y. Bertrand, and M. Renovell,
“Efficient on-chip generator for linear histogram BIST of ADCs,”
in IMSTW’01 :International Mixed-Signal
Testing Workshop, pp. 89–96, 2001.
.
[96]
F. Azaïs, S. Bernard, Y. Bertrand, and M. Renovell,
“Sinusoidal Histogram-based BIST for ADC Testing,” in DCIS’00 :
Design of Integrated Circuits and Systems, pp. 21–24, 2000.
.
[97]
Y. B. S. Bernard, F. Azaïs and M. Renovell, “Linear
Histogram Test for ADCs a BIST Implementation,” in IMSTW’00 :
Mixed-Signal Testing Workshop, pp. 40– 45, 2000.
.
[98]
S. Bernard, F. Azaïs, Y. Bertrand, and M. Renovell,
“Minimization the Hardware Overhead of a Histogram-Based BIST
Scheme for Analog-to-Digital Converters,” in LATW’00 : Latin
American Test Workshop, pp. 118–122, 2000.
