Luigi Dilillo Home page

My research work is currently done at ECS (Electronics and Computer Sciences) department of the University of Southampton (United Kingdom). The targets of my research are the reduction of power consumption and the reduction of temperature picks in memory test. Nowadays, many industrial results prove that, during the test of the integrated circuits (IC) and the Systems on Chip, the power dissipation can be several times higher than in normal functional mode. Consequently, the reduction of test power becomes a main concern. I have chosen to focus on memories because they represent more and more the principal contributor to the overall dissipation of complex systems and because of my background on memory test. My first purpose is the proposition of methods that reduce the test power in SRAM and, in particular, in the pre-charge circuits that are the principal contributor of the overall dissipation in memories. The action of the pre-charge circuits is essential for the correct operation of the memories. At this moment, I have proposed a new technique which strongly reduces the pre-charge activity during the test. This technique is based on the fact that in functional mode the cells are selected in random sequence, and therefore all pre-charge circuits need to be always active, while during the test mode the access sequence is known, and consequently, only the columns that are to be selected need to be pre-charged. I have implemented this low power test mode by using a modified pre-charge control circuitry.
Concerning the thermal stress during the test, my initial objective is the finding the most active memory devices and deducing where the hot spots are located. The hot spots on the silicon matrix are locations where the temperature raises more quickly than the average overheating of the circuit because of the non-uniform space distribution of the power consumption. On the base of this preliminary study, the final objective is the modification of the test sequences in order to distribute more rationally the activity in the memory, avoiding the hot spots and the premature aging.

Luigi Dilillo Home page
Microelectronics department	Version Française
	Contact informations: Luigi DILILLO
Personal Area Teaching activities Publications and Seminars Hobbies	Tel.		: +33 (0) 4 67 41 85 26
	Fax		: +33 (0) 4 67 41 85 00
	e-mail		dilillo@lirmm.fr
	address		LIRMM 161, rue Ada 34392 Montpellier
			FRANCE
Luigi Dilillo has been PHD student at the microelectronics department of LIRMM (Laboratoire de informatique, robotique et microelectronique de Montpellier) laboratory in Montpellier. After, he has been research fellow at the University of Sothampton (UK) and at CEA (French commission for Atomic Energy). At this moment, he is a permanent CNRS researcher at LIRMM. The fields of interest of his reserches are MEMS and digital circuits. His current studies are on delay-fault testing, memory testing, digital circuit testing, power and thermal constraint testing.
		Norway -June 2003

Memory Test With Thermal and Power Constraints
My research work is currently done at ECS (Electronics and Computer Sciences) department of the University of Southampton (United Kingdom). The targets of my research are the reduction of power consumption and the reduction of temperature picks in memory test. Nowadays, many industrial results prove that, during the test of the integrated circuits (IC) and the Systems on Chip, the power dissipation can be several times higher than in normal functional mode. Consequently, the reduction of test power becomes a main concern. I have chosen to focus on memories because they represent more and more the principal contributor to the overall dissipation of complex systems and because of my background on memory test. My first purpose is the proposition of methods that reduce the test power in SRAM and, in particular, in the pre-charge circuits that are the principal contributor of the overall dissipation in memories. The action of the pre-charge circuits is essential for the correct operation of the memories. At this moment, I have proposed a new technique which strongly reduces the pre-charge activity during the test. This technique is based on the fact that in functional mode the cells are selected in random sequence, and therefore all pre-charge circuits need to be always active, while during the test mode the access sequence is known, and consequently, only the columns that are to be selected need to be pre-charged. I have implemented this low power test mode by using a modified pre-charge control circuitry. Concerning the thermal stress during the test, my initial objective is the finding the most active memory devices and deducing where the hot spots are located. The hot spots on the silicon matrix are locations where the temperature raises more quickly than the average overheating of the circuit because of the non-uniform space distribution of the power consumption. On the base of this preliminary study, the final objective is the modification of the test sequences in order to distribute more rationally the activity in the memory, avoiding the hot spots and the premature aging. Keywords: SRAM, March Test, Low power, Thermal constraints, pre-charge
Test of Delay and Dynamic Faults in SRAM Memories
Embedded memories will continue to dominate the System-on-Chip silicon area in the next years. This is confirmed by the SIA Roadmap which forecasts a memory density approaching 94% in about ten years. Consequently, memories will be the main responsible of the overall System-on-Chip yield. It therefore becomes evident that the development of efficient test solutions and repair schemes for memories are essential. Memory test solutions are mostly oriented to static fault detection. These faults are sensitized by only one operation. Recent works show that VDSM (Very Deep Sub-Micron) technologies more frequently involve dynamic faults. They can be sensitized only by performing more than one operation in sequence and traditional tests are not made to detect them. Among the known dynamic faults that may affect SRAM memories, I concentrate my studies on those that affect the different devices inside the SRAM structure. In particular I have studied dynamic faults in the address decoders and in core-cell, where the information is physically stored and the pre-charge circuits. Concerning the address decoder I have produced a complete study on ADOFs (address decoder open faults) and resistive-ADOF. I have analyzed the electrical causes of these faults and I have produced efficient March test solutions. Concerning the SRAM core-cell, I have treated the behavior of this device in case of presence of resistive-open defects. In general these defects cause delay faults, but some of them involves dynamic faults as dynamic read destructive faults (dRDFs) and hard to detect data retention faults (DRFs). With a work of analysis and characterization, I have found the fault models relative to the defects and finally I have proposed efficient March test procedures to detect them. It is useful to observe that in most of cases the proposed March test procedures are based on modification existing March tests. I have chosen this kind of test because in spite of their low complexity they can be very efficient. My last studies concern the dynamic faults in precharge circuits of SRAMs. In this ambit I have produced an analysis and characterization of the faulty behaviour of the SRAM in case of resistive-open defects in the pre-charge circuit, and later I have proposed an efficient test algorithm called March Pre. My next targets are other SRAM circuits, such as the write drivers, the output sense amplifiers.I have produced large part of my research studies at LIRMM laboratory with Pr. S. Pravossoudovitch and Dr. P. Girard and in collaboration with Infineon Technology, Sophia Antipolis. My study on memory test is now mainly driven to thermal and power consumption parameters, in the team leaded by Pr. B. Al Hashimi at the University of Southampton. Keywords: SRAM, Dynamic Faults, Delay faults, March Test, Address Decoders, Core-cell, pre-charge