1. Bilan des Publications
Les sections ci-dessous fournissent un décompte par année des différents types de publications. Ces informations ne concernent que les documents d'ores et déjà publiés, ou sur le point de l'être.
2. Liste des Publications
Thèse de Doctorat
[TH1] “Test des Fautes Dynamiques dand les Mémoires SRAM”
Soutenue le 8 juin 2005
Ouvrages (Livre)
[OU1] Advanced Test Methods for SRAMs - Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies. - Bosio A., Dilillo L., Girard P., Pravossoudovitch S., Virazel A. - Springer Ed. (2009) 978-1-4419-0937-4 171 p.
Revues avec Comité de Lecture
[RE1] S. Borri,
M. Hage Hassan, L. Dilillo, P. Girard, S. Pravossoudovitch et A. Virazel, “Analysis of Dynamic Defects in Embedded-SRAMs:
Implications for Memory Test”, JETTA Journal of Electronic Testing - Theory and
Applications, Springer, Vol. 21, N° 2, pp. 169-179, Avril
2005.
[RE2] L. Dilillo, P.
Girard, S. Pravossoudovitch, A. Virazel,
S. Borri et M. Hage-Hassan,
“Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in
SRAM Memories”, JETTA Journal of Electronic Testing - Theory and Applications,
Springer, Vol. 21, N° 5, pp. 551-561, Octobre 2005.
[RE3] L. Dilillo, P.
Girard, S. Pravossoudovitch, A. Virazel,
S. Borri et M. Hage Hassan,
“ADOFs and Resistive-ADOFs
in SRAM Address Decoders: Test Conditions and March Solutions”, JETTA Journal
of Electronic Testing - Theory and Applications, Springer, Vol. 22, N° 3, pp.
287-296, June 2006.
[RE4] L. Dilillo, P. Rosinger, B.H. Al-Hashimi et P. Girard, “Reducing Power Dissipation in SRAM During
Test”, JOLPE - Journal on Low Power Electronics, American Scientific
Publishers, Vol. 2, N° 2, pp. 271-280, Août 2006.
[RE5] L. Dilillo, P.
Girard, S. Pravossoudovitch, A. Virazel
et M. Bastian, “A Novel March Procedure to Test
Address Decoder Open Faults in SRAM Memories”, JEC Journal of Embedded
Computing, 2007.
[RE6] L. Dilillo, P.
Girard, S. Pravossoudovitch, A. Virazel
et M. Bastian, “Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits”, JETTA Journal of Electronic
Testing - Theory and Applications, Springer, Vol. 23, N° 5, pp. 435-444, Octobre 2007.
[RE7] L. Dilillo, P.
Girard, S. Pravossoudovitch, A. Virazel,
S. Borri et M. Hage-Hassan,
“New March Elements for Address Decoder Open and Resistive Open Fault Detection
in SRAM Memories”, JICS Journal of Integrated Circuits and Systems, 3, 1 pp.7-12,
2008
[RE8] F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, X. Wen, N. Ahmed, “A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes”, Journal on Low Power Electronics, American Scientific Publishers, Volume 6, Number 2 (August 2010), pp 359–374.
[RE9] J. Vial, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovtich,
“SoC yield Improvement Using TMR Architectures for
Manufacturing Defect Tolerance in Logic Cores”, International
Journal on Advances in Systems and Measurements, IARIA publishing, vol. 1 nr.5,
2010.
[RE10] P. Rech, J-M. Galliere, P. Girard, F. Wrobel, F. Saigné, and L. Dilillo, “Impact of Resistive-Open Defects on SRAM Error Rate Induced by Alpha Particles and Neutrons”, IEEE Transaction on Nuclear Science, Volume: 58 , Issue: 3 , Part: 2 10.1109/TNS.2011.2123114, 2011 , Page(s): 855 - 861.
[RE12] A. Griffoni, J. van Duivenbode, D. Linten, E. Simoen, P. Rech, L. Dilillo, F. Wrobel, P. Verbist and G. Groeseneken,"Neutron-Induced Failure in Silicon IGBTs, Silicon Super-Junction and SiC MOSFETs", In press, IEEE Transaction on Nuclear Science, Digital Object Identifier: 10.1109/TNS.2011.2180924, 2012
[RE13] P-D Mauroux,
A. Virazel, A. Bosio, L.
Dilillo, P. Girard, S. Pravossoudovitch, B. Godard,
“Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACtm eFlash Memories" in press, JETTA Journal
of Electronic Testing - Theory and Applications, Springer,
[RE14] P. Rech, J-M. Galliere, P. Girard, A. Griffoni, J. Boch, F. Wrobel, F. Saigné, and L. Dilillo, “Multiple Bit Upsets on Two Commercial SRAMs under Dynamic-Stress”, IEEE Transaction on Nuclear Science, Issue: 99, Digital Object Identifier: 10.1109/TNS.2012.2187218,2012
[RE15] A. Todri, S. Kundu, P. Girard, A. Bosio, L. Dilillo, A. Virazel, “A Study of Tapered 3D TSVs for Power and Thermal Integrity”, in press, IEEE Transaction on Very Large scale Integration Systems, 2012
[RE16] R. A. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes” in press, Journal of Electronic Testing: Theory and Applications (JETTA), DOI: 10.1007/s10836-012-5291-6, 2012
[RE17] A. Todri, A. Bosio, L. Dilillo,, P. Girard, S. Pravossoudovitch, A. Virazel, “Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation”, in press, IEEE Transaction on Very Large scale Integration Systems, 2012
[RE18] D. Pantel, J-R. Vaillé, F. Wrobel, L. Dilillo, J-M. Gallière, J-L. Autran, P. Cocquerez, P. Chadoutaud, F. Saigne “Embedded Silicon Detector to Investigate the Natural Radiative Environment”, in press, Journal of Instrumentation (IOP), 2012
[RE19] L. Dilillo, A. Bosio, P. Rech, P. Girard, F. Wrobel, F. Saigne, “A Distributed SRAM-based Neutron Detection Platform and its Infrastructure for Robust Data Collection and Transfer,” submitted to Journal Microelectronics Reliability (ELSEVIER), 2011
[RE20] R. A. Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “Variability Analysis of an SRAM Test Chip,” submitted to Elsevier Journal of Microelectronics on Dec 2011
[RE21] R. A. Fonseca, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel, N. Badereddine, “Setting Stress Conditions for Improving SRAM Test Efficiency” submitted to IEEE Transaction on Very Large scale Integration Systems, Feb, 2012
tutorials
[TU1] A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, “Advanced Test Methods for SRAMs", IEEE Latin American Test Workshop, Porto de Galinhas, Brésil, Mars, 2011
[TU2] A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, “Advanced Test Methods for SRAMs", IEEE VLSI Test Symposium, Maui, Hawaii, USA, April, 2012, pp. 301-2
Conférences Invitées dans des Congrès
[IN1] L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel et M. Bastian Hage-Hassan, “Test Solutions for Dynamic Faults in SRAM
Memories”, MEDEA+ Design Automation Conference, Paris, France, 22-25 Mai 2005.
[IN2] L. Dilillo,
P. Girard, C. Landrault, S. Pravossoudovitch,
A. Virazel, M. Bastian et V. Gouin,
“Impact of Technology Scaling on Defects and Parameter Deviations in Embedded
SRAMs”, IEEE VLSI Test Symposium, Innovative Practice Session on “Testing
Embedded Memories”, Santa Clara, USA, Mai 2008.
[IN3] L. Dilillo, P. Rech, J-M. Galliere, P. Girard, F. Wrobel, F. Saigne, “Neutron Detection in Atmospheric Environment through Static and Dynamic SRAM-Based Test Bench”, IEEE Latin American Test Workshop, Porto de Galinhas, Brésil, Mars, 2011
[IN5] A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, K. Miyase, X. Wen, “Power-Aware Test Pattern Generation for At-Speed LOS Testing”, IEEE Asian Test Symposium, New Delhi, India, November, 2011
[CO1] L. Dilillo, P. Girard,
S. Pravossoudovitch, A. Virazel
et M. Bastian Hage-Hassan, “Resistive-Open Defect
Injection in SRAM Core-cell: Analysis and Comparison between 0.13 μm and 90 nm Technologies”, ACM/IEEE
Design Automation Conference, pp. 857-862, Anaheim, USA, 13-17 Juin 2005.
[CO2] L. Dilillo, P. Rosinger, P. Girard et B.M. Al-Hashimi,
“Minimizing Test Power in SRAM through Pre-charge Activity
Reduction”, ACM/IEEE Design, Automation and Test in Europe, pp. 1159-1165,
Munich, Allemagne, 6-10 Mars 2006.
[CO3] A. Ney, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch
et A. Virazel, “A Signature-based Approach for
Diagnosis of Dynamic Faults in SRAMs”,
IEEE International Conference on Design & Test of Integrated Systems, Touzeur, Tunisie, 25-27 Mars
2008.
[CO4] A. Ney, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch
et A. Virazel, M. Bastian “A History-Based Diagnosis
Technique for Static and Dynamic Faults in SRAMs”, IEEE International Test Conference, Santa Clara, USA, octobre, 2008.
[CO5] J. Vial, A. Virazel, A. Bosio, L. Dilillo, P.
Girard, S. Pravossoudovitch, “Using TMR Architectures
for SoC Yield Improvement”, VALID'09: International
Conference on Advances in System Testing and Validation Lifecycle, pp 155-160, Porto,
Portugal, Septembre 2009.
[CO6] A. Ney, L. Dilillo, P.
Girard, S. Pravossoudovitch et A. Virazel,
“A New Design-for-Test Technique for SRAM Core-Cell Stability Faults”, ACM/IEEE
Design, Automation and Test in Europe, Nice, France, Mars 2009.
[CO7] Y. Benabboud,
A. Bosio, P. Girard, S. Pravossoudovitch,
A. Virazel, L. Dilillo, “A Fault-Simulation-Based
Approach for Logic Diagnosis”,
IEEE International Conference on Design & Test of Integrated Systems, Le Caire, Egypte, 2009.
[CO8] J-M. Galliere, F. Azais, M. Renovell, L. Dilillo, “Influence of Gate Oxide Short
Defects on the Stability of Minimal Sized SRAM Core-Cell by Applying Non-Split
Models”, IEEE International
Conference on Design & Test of Integrated Systems, Le Caire,
Egypte, 2009.
[CO9] P-D Mauroux,
A. Virazel, A. Bosio, L.
Dilillo, P. Girard, S. Pravossoudovitch, B. Godard,
“NAND flash testing: A preliminary study on actual defects”, IEEE International Test Conference,
Austin, USA, 2009.
[CO10] R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “A Statistical Simulat ion Method for Reliability Analysis of SRAM Core-Cells”, International Design Automation Conference, Anaheim, CA USA, Juin 2010.
[CO11] P. Rech,
J-M. Galliere, P. Girard, F. Wrobel, F. Saigné, and
L. Dilillo, “Impact of Resistive-Open Defects on SRAM Error Rate Induced by Alpha Particles and Neutrons”, 11th IEEE European
Conference on Radiation and its
Effects on Components and Systems, septembre 2010.
[CO12] F. Wrobel, J-R. Vaillé, D. Pantel, L. Dilillo, P. Rech, J-M. Gallière, F. Saigné, A. Touboul, P. Chadoutaud, P. Cocquerez, M. Lacourty, T. Lam-Trong, J-L. Autran, C. Chatry, F. Laplanche, B. Azais, “Experimental Characterization of Atmospheric Radiation Environment with Stratospheric Balloon”, 11th IEEE European Conference on Radiation and its Effects on Components and Systems, septembre 2010.
[CO13] D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, H.-J. Wunderlich “Parity Prediction Synthesis for Nano-Electronic Gate Designs” International Test Conference, Austin TX, USA, 2010
[CO14] J-M. Galliere, P. Rech, P. Girard, L. Dilillo, “A Roaming Memory Test Bench for Detecting Particle Induced SEUs”, International Test Conference, Austin TX, USA, 2010.
[CO15] F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed, “Is Test Power Reduction Through X-Filling Good Enough?”, International Test Conference, Austin TX, USA, 2010.
[CO16] P. Rech, J-M. Galliere, P. Girard, F. Wrobel, F. Saigné, and L. Dilillo, “Dynamic-Stress Neutrons Test of Commercial SRAMs ”, IEEE Nuclear and Space Radiation Effects Conferencee, Las Vegas, CA, USA, 2011.
[CO17] R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “On Using Address Scrambling for Defect Tolerance in SRAMs”, International Test Conference, Anaheim, California, USA, 2011.
[CO18] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G. Prenat, K. Mackay, “Analysis of Resistive-Open Defects in Thermally-Assisted MRAM Array”,International Test Conference, Anaheim, California, USA, 2011.
[CO19] A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, “Power Supply Noise and Ground Bounce aware Pattern Generation for Delay Testing and Speed Binnings”, IEEE International NEWCAS conference, Bordeaux,, France, 2011.
[CO20] A. Griffoni, J. van Duivenbode, D. Linten, E. Simoen, P. Rech, Luigi Dilillo, F. Wrobel, P. Verbist, G. Groeseneken, “Neutron-Induced Failure in Super-Junction, IGBT, and SiC Power Devices ”, 12th IEEE European Conference on Radiation and its Effects on Components and Systems, septembre 2011.
[CO21] P. Rech, J-M. Galliere, P. Girard, A. Griffoni, F. Wrobel, F. Saigné, and L. Dilillo, “Neutron-Induced Multiple Bit Upsets on Dynamically-Stressed Commercial SRAM Arrays”, European Conference on Radiation and its Effects on Components and Systems, septembre 2011.
[CO22] J-M. Galliere and L. Dilillo, “Versatile March Test Generator for Hands-on Memory Testing Laboratory”, IEEE International Conference on Microelectronic Systems Education, June 5-6, San Diego, USA, 2011 ISBN: 978-1-4577-0550-2.
[CO23] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G. Prenat, K. Mackay, “Impact of Resistive-Open Defects
on the Heat Current of TAS-MRAM Architectures”, ACM/IEEE Design, Automation and Test in Europe, Dresden, Allemagne, 12-16 Mars 2012.
[CO24] F. Wrobel, L. Dilillo, A. D.Touboul, J-R. Vaillé and F. Saigné, "Characteristics of the Transient Currents Induced by Atmospheric Neutrons on a 40nm Electrode of an NMOS Transistor", IEEE Nuclear and Space Radiation Effects Conferencee, Miami, FL, USA, 2012.
[CO25] D. Pantel, J-R. Vaillé, F. Wrobel, L. Dilillo, J-M. Gallière, J-L. Autran, P. Cocquerez, P. Chadoutaud, F. Saigne, "A Silicon Diode Based Detector for the Natural Radiative Environment Measurement in Altitude", IEEE (Nuclear Plasma Society) Real Time Conference, Berkeley, CA, USA, 2012.
[CO26] A. Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel et S. Kundu, “Voltage Droop and Thermal Constraints Driven Optimization of 3D Power Delivery Networks”, ACM/IEEE Design Automation Conference, San Fransisco, USA, 3-8 Juin 2012.
Symposiums avec Comité de Lecture et Actes
[SY1] L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel et S. Borri, “Comparison
of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders”,
IEEE Asian Test Symposium, pp. 250-255, Xian, Chine, 16-19 Novembre
2003.
[SY2] L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel et S. Borri, “March iC-: An Improved Version of March C- for ADOFs Detection”, IEEE VLSI Test Symposium, pp. 129-134,
Napa, USA, 25-29 Avril 2004.
[SY3] L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri et M. Hage-Hassan, “Dynamic Read Destructive Faults in Embedded
SRAMs: Analysis and March Test Solution”, IEEE European Test Symposium, pp.
140-145, Ajaccio, France, pp. 140-145, 24-26 Mai 2004.
[SY4] L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel et S. Borri,
“Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test
Solution”, IEEE Asian Test Symposium, pp. 266-271, Kenting,
Taiwan, 15-17 Novembre 2004.
[SY5] L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel et M. Bastian Hage-Hassan,
“Data Retention Fault in SRAM Memories:
Analysis and Detection Procedures”, IEEE VLSI Test Symposium, pp.
183-188, Palm Springs, USA, 1-5 Mai 2005.
[SY6] L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel et M. Bastian Hage-Hassan,
“Resistive-Open Defect Influence in SRAM Pre-charge Circuits: Analysis and
Characterization”, IEEE European Test Symposium, pp. 116-121, Tallinn, Estonie, 22-25 Mai 2005.
[SY7] Y. Benabboud, A. Bosio, L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel, O. Riewer, I. Izaute, “Delay Fault Diagnosis in Sequential Circuits”,
IEEE Asian Test Symposium, Taichung, Taiwan, 2009.
[SY8] Y. Benabboud, A. Bosio, L. Dilillo,
P. Girard, S. Pravossoudovitch, A. Virazel, L. Bouzaida, I. Izaute,
“Comprehensive bridging fault diagnosis based on the SLAT paradigm”, IEEE
International Symposium on Design and Diagnostics of Electronic Circuits &
Systems, pp 264 - 269, Liberec, République Tchèque, 2009
[SY9] P. Rech, M. Grosso, F. Melchiori, D. Loparco, D. Appello, L. Dilillo, A. Paccagnella,
and M. Sonza Reorda, “Analysis
of Root Causes of Alpha Sensitivity Variations on Microprocessors Manufactured
using Different Cell Layouts”, IEEE International On-Line Testing Symposium, Corfu, Greece, Juillet,
2010.
[SY10] P-D Mauroux,
A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch,
B. Godard, G. Festes, L. Vachez,
“A Two-Layer SPICE Model of the ATMEL TSTAC eFlash
Memory Technology for Defect Injection and Faulty Behavior
Prediction”, IEEE European Test Symposium, Prague, République
Tchèque, Mai, 2010.
[SY11] R. Alves Fonseca, L.
Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A.
Virazel, N. Badereddine, “Analysis of Resistive-Bridging Defects in SRAM Core-Cells: A
Comparative Study from 90nm
down to 40nm Technology Nodes”, IEEE European Test Symposium, Prague,
République Tchèque, Mai, 2010.
[SY12] R. Alves Fonseca, L.
Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A.
Virazel, N. Badereddine, “Setting
Test Conditions for Improving SRAM Reliability”, IEEE European Test Symposium, Prague, République Tchèque, Mai, 2010.
[SY13] R. Alves Fonseca, L.
Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A.
Virazel, N. Badereddine, “Detecting NBTI Induced Failures in SRAM Core-Cells”, IEEE VLSI Test Symposium, pp 75-80, Santa
Cruz, USA, Avril, 2010.
[SY14] F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, J.
Ma, W. Zhao, M. Tehranipoor, X. Wen, “Analysis of
Power Consumption and Transition Fault Coverage for LOS and LOC Testing
Schemes”, IEEE International Symposium on Design and Diagnostics of Electronic
Circuits & Systems, pp 376 - 381, Vienne, Autriche, 2010
[SY15] R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “Impact of Resistive-Bridging Defects in SRAM Core-Cell”, IEEE International Symposium on Electronic Design, Test and Application, pp 265 - 269, Ho Chi Minh City, Vietnam, janvier, 2010.
[SY16] P. Rech,
A. Bosio, P. Girard, S. Pravossoudovitch,
A. Virazel, L. Dilillo, “A Memory Fault
Simulator for Radiation-Induced Effects
in SRAMs”, IEEE Asian Test Symposium, Shangai, Chine, 2010
[SY17] Y. Benabboud, A. Bosio,
L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, O. Riewer, “A
Comprehensive System-on-Chip Logic Diagnosis Approach”, IEEE Asian Test Symposium, Shangai, Chine, 2010
[SY18] M. Valka, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, E. Sanchez M. Sonza Reorda, “A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing”, IEEE European Test Symposium, Trondheim, Norway, May 2011
[SY19] A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, “A Study of Path Delay Variations in the Presence of
Uncorellated Power and Ground Supply Noise”, IEEE International Symposium on Design and Diagnostics of Electronic
Circuits & Systems, Cottbus, Germany, 2011
[SY20] L. B. Zordan , A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling”, IEEE International Symposium on Design and Diagnostics of Electronic
Circuits & Systems, Cottbus, Germany, 2011
[SY21] P-D Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes, L. Vachez, “On Using a SPICE-like TSTAC eFlash Model for Design and Test”, IEEE International Symposium on Design and Diagnostics of Electronic
Circuits & Systems, Cottbus, Germany, 2011
[SY22] L. Dilillo, A. Bosio, M. Valka, P. Girard, S. Pravossoudovitch A. Virazel , “Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector ”, IEEE DFT Symposium, Vancouver, Canada, 2011
[SY23] K. Miyase, Y. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, P. Girard, A. Virazel, “Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling”, IEEE Asian Test Symposium, New Delhi, India, November, 2011
[SY24] D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, H.-J. Wunderlich, “A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits”, IEEE Asian Test Symposium, New Delhi, India, November, 2011
[SY25] F. Wrobel, L. Dilillo, A. D.Touboul, J-R. Vaillé and F. Saigné, “Alpha particle-induced transient currents in 65 nm and 40 nm technologies”, Single Event Effects Symposium, San Diego, USA, April, 2012
[SY26] L. B. Zordan , A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Todri, A. Virazel, N. Badereddine, “Defect Analysis in Power Mode Control Logic of Low-Power SRAMs”, IEEE European Test Symposium, Annecy, France, 2012
[SY27] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, , G. Prenat, J. Alvarez-Herault, K. Mackay, “Coupling-Based Resistive-Open Defects in TAS-MRAM Architectures”, IEEE European Test Symposium, Annecy, France, 2012
[SY28] C. Metzler, A.Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “Through-Silicon-Via Resistive-Open Defect Analysis”, IEEE European Test Symposium, Annecy, France, 2012
[SY29] D.A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, M. Imhof et H.J. Wunderlich, "A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures", IEEE VLSI Test Symposium, Maui, Hawaii, USA, April, 2012
[SY30] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel, A. Touboul, F. Wrobel, F. Saigné, "Evaluation of Test Algorithms Stress Effect on SRAMs under Neutron Radiation", IEEE International On-Line Testing Symposium, Sitges, Spain, June,
2012.
Workshops avec Comité de Lecture et Actes
[WO1] L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel et
S. Borri, “March Tests Improvement for Address
Decoder Open and Resistive Open Fault Detection”, IEEE Latin American Test
Workshop, pp. 31-36, Cartagena, Colombie, 8-10 Mars
2004.
[WO2] L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel et
M. Bastian Hage-Hassan, “Efficient Test of Dynamic
Read Destructive Faults in SRAM Memories”, IEEE Latin American Test Workshop,
pp. 40-45, Salvador Bahia, Brésil, 30 Mars – 2 Avril 2005.
[WO3] L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel et
M. Bastian, “March Pre: an Efficient Test for Resistive-Open Defects in the SRAM
Pre-charge Circuit”, IEEE Workshop on Design and Diagnostics of
Electronic Circuits and Systems, pp. 256-261, Prague, République
Tchèque, Avril 2006.
[WO4] L. Dilillo, B.M. Al-Hashimi, P. Rosinger et P. Girard, “Leakage Read Fault in Nanoscale
SRAM: Analysis, Test and Diagnosis”, IEEE International Design and Test
Workshop, pp. 110-115, Dubai, Emirats Arabes Unis, 19-20 Novembre 2006.
[WO5] L. Dilillo, B. M. Al-Hashimi, “March CRF: an Efficient Test for
Complex Read Faults in SRAM Memories”, IEEE Workshop on Design and
Diagnostics of Electronic Circuits and Systems, pp. 256-261, Cracow, Polonie, Avril 2007.
[WO6] F. Wu, L. Dilillo, P. Girard,
S. Pravossoudovitch, A. Virazel,
A. Bosio, X. Wen,
“Trade-off between Power Dissipation and Delay Fault Coverage for LOS and LOS
Test Schemes”, International Workshop On Impact Of Low-Power Design On Test And
Reliability (Lpontr) Seville, Espagne,
Mai, 2009.
[WO7] L. Dilillo, F. Wrobel, J.-M. Galliere,
F. Saigne, “Neutron detection through an SRAM-based
test bench”, IEEE International Workshop on Advances in sensors and Interfaces, (IWASI),
pp. 64-69, Trani, Italie,
2009.
[WO8] F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen et N. Ahmed, “Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing”, International Workshop On Impact Of Low-Power Design On Test And Reliability (Lpontr) Prague, République Tchèque, Mai, 2010.
[WO9] R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “Setting Test Conditions for Detecting Faults Induced by Random Dopant Fluctuation in SRAM CoreCells”, European workshops on CMOS Variability. (VARI 2010 ) Montpellier, France, Mai, 2010.
[WO11] F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed, “Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing”, IEEE International Conference on Design & Test of Integrated Systems, Athens, Greece, April, 2011
[WO12] P-D Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, “ A Test Solution for Oxide Thickness Variations in the ATMEL T STAC eFlash Technology”, IEEE International Conference on Design & Test of Integrated Systems, Athens, Greece, April, 2011
[WO13] R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine,“Variability Analysis of an SRAM Test Chip”, workshop paper at IEEE European Test Symposium, Trondheim, Norway, May 2011
[WO14] L. Dilillo, A. Bosio, P. Rech, P. Girard, F. Wrobel, F. Saigne, “Robust Data Collection and Transfer Framework for a Distributed SRAM Based Neutron Sensor”, IEEE International Workshop on Advances in sensors and Interfaces, (IWASI), Savelletri, Italie, June, 2011
Colloques Nationaux et internationaux avec Actes à Diffusion Restreinte
[CNI1] L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri et M. Hage-Hassan, “Test March pour la Détection des Fautes Dynamiques dans les Décodeurs de Mémoires SRAM”,7ième Journées Nationales du Réseau Doctoral en Microélectronique, Marseille, 4-6 Mai 2004.
[CNI2] L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, et M. Hage-Hassan, “Incidence des Fautes Résistifs dans les Circuits de Precharge des Mémoires SRAM”, 8ième Journées Nationales du Réseau Doctoral en Microélectronique, Paris, 10-12 Mai 2005.
[CNI3] A. Ney, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch et A. Virazel, M. Bastian , “A History-Based Technique for Faults Diagnosis in SRAMs”, Colloque GDR SoC-SiP, Cergy, France, 4-6 juin, Paris, 2008
[CNI4] F.Wu, L.Dilillo, A.Bosio, P.Girard, S. Pravossoudovitch, A. Virazel, X. Wen, “Trade-off Between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing Schemes”, Colloque GDR SoC-SiP, Cergy, France, 10-12 juin, Paris, 2009
[CNI5] R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “Core-cell Quality Metrics”, Colloque GDR SoC-SiP, Cergy, France, 10-12 juin, Paris, 2009
[CNI6] P-D Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes, L. Vachez, “Analyse et modélisation des défauts résistifs affectant les mémoires Flash”, GDR SOC-SIP’10: Colloque GDR SoC-SiP, Cergy, France, 9-11 juin 2010
[CNI7] F.Wu, L.Dilillo, A.Bosio, P.Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed, “Test Relaxation and X-filling to Reduce Peak Power During At-Speed LOS Testing”, GDR SOC-SIP’10: Colloque GDR SoC-SiP, Cergy, France, 9-11 juin 2010
[CNI8] D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, H-J Wunderlich, “Tolérance aux fautes et rendement de fabrication”, GDR SOC-SIP’10: Colloque GDR SoC-SiP, Cergy, France, 9-11 juin 2010
[CNI9] P-D Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, “ Analysis and Fault Modeling of Actual Resistive Defects in Flash Memories”, 13ième Journées Nationales du Réseau Doctoral en Microélectronique, Montpellier, 7-11 Juin 2010
[CNI10] L. Dilillo, “Neutron detection through an SRAM-Based Test Bench”, GDR SOC-SIP’10: Colloque GDR SoC-SiP, Marseille, France, 6 mai 2010
[CNI11] L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, “A Robust Infrastructure for Data Collection and Transfer for a Distributed SRAM-based Neutron Detection Platform”, International Workshop on Dependability Issues in Deep-submicron Technologies, Trondheim, Norway, 26-27 mai 2011
[CNI12] J-M Galliere and L.Dilillo, “Séquence pédagogique dédiée à l'apprentissage des techniques de test des mémoires”, 9e Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes, Trois Rivières, Canada, 23-26 October 2012
[CNI13] D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, HJ. Wunderlich, “A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits”, GDR SOC-SIP’11: Colloque GDR SoC-SiP, Lyon, France, 15-17 juin 2011
[CNI14] L. Bonet Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, N. Badereddine, “Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling”, GDR SOC-SIP’11: Colloque GDR SoC-SiP, Lyon, France, 15-17 juin 2011
[CNI15] J. Azevedo, A. Virazel, P. Girard, A. Bosio, S. Pravossoudovitch, L. Dilillo, “Test and Reliability of Magnetic Random Access Memories”, GDR SOC-SIP’11: Colloque GDR SoC-SiP, Lyon, France, 15-17 juin 2011
[CNI16] L. Dilillo, “Impact of Atmospheric Neutrons on SRAMs through a Modular Test Bench”, RADSOL 2011, 4eme Colloque sur l'Electronique et rayonnements naturels au niveau du sol, june 14-15, Paris, France, 2011
[CNI17] M. Imhof, H-J Wunderlich, D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, “Ein Pseudo-Dynamischer Komparator zur Fehlererkennung in fehlertoleranten Architekturen”, Workshop: Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen 2012, February 26-28, Cottbus, Germany
[CNI18] L. Dilillo, “An Error Resilient Platform for Data Transfer and Power Management for a Distributed SRAM-based Neutron Detection Test Bench”, RADSOL 2012, 5eme Colloque sur l'Electronique et rayonnements naturels au niveau du sol, june 14-15, Paris, France, 2012
Rapports de Contrat
[RC1] P. Girard, S. Bernard, A.Bosio, L. Dilillo, M.L. Flottes, S. Pravossoudovitch, M. Renovell, B. Rouzeyre, A. Virazel - Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+ (2009)
[RC2] P. Girard, F. Azais, S.Bernard, A. Bosio, L. Dilillo, G. Di Natale, M.L. Flottes, S. Pravossoudovitch, M. Renovell, B. Rouzeyre. et al - TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-Rapport Technique de Fin d'année (2009)
[RC3] P. Girard, S. Bernard, F. Azais, A. Bosio, L. Dilillo, G. Di Natale, M.L. Flottes, M. Renovell, B. Rouzeyre, A. Virazel - TOETS CT302 - Programme CEE CATRENE - Summary Technical Report Contrat (Rapport Intermédiaire), (Juillet 2011)
[RC4] P. Girard, S. Bernard, F. Azais, A. Bosio, L. Dilillo, G. Di Natale, M.L. Flottes, M. Renovell, B. Rouzeyre et A. Virazel, Rapport technique de fin d’année, Contrat TOETS CT 302, Programme CEE CATRENE, (Janvier 2011)
[RC5] P. Girard, S. Bernard, F. Azais, A. Bosio, L. Dilillo, G. Di Natale, M.L. Flottes, M. Renovell, B. Rouzeyre et A. Virazel, Rapport technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE, (Juillet 2011)
[RC6] P. Girard, S. Bernard, F. Azais, A. Bosio, L. Dilillo, G. Di Natale, M.L. Flottes, M. Renovell, B. Rouzeyre et A. Virazel, Rapport technique de fin d’année, Contrat TOETS CT 302, Programme CEE CATRENE, (Janvier 2012).