|
Summary
| Book | Journal |
Proceedings | Presentations |
|
| Year | Chapter | Journal |
Conference | Symposium | Workshop |
Tutorial | Workshop | Poster | Demo |
Total |
| 2000 |
0 | 0 |
2 | 0 | 2 |
0 | 0 | 0 | 0 |
4 |
| 2001 |
0 | 1 |
2 | 2 | 2 |
0 | 0 | 0 | 0 |
7 |
| 2002 |
0 | 1 |
2 | 1 | 0 |
0 | 0 | 0 | 0 |
4 |
| 2003 |
0 | 2 |
1 | 3 | 1 |
0 | 0 | 0 | 0 |
7 |
| 2005 |
0 | 0 |
2 | 1 | 2 |
0 | 0 | 0 | 0 |
5 |
| 2006 |
0 | 0 |
3 | 5 | 2 |
0 | 0 | 0 | 0 |
10 |
| 2007 |
0 | 1 |
0 | 2 | 1 |
0 | 3 | 0 | 0 |
7 |
| 2008 |
0 | 2 |
2 | 5 | 1 |
0 | 4 | 0 | 2 |
16 |
| 2009 |
0 | 2 |
0 | 0 | 1 |
2 | 0 | 0 | 2 |
7 |
| 2010 |
1 | 0 |
0 | 2 | 1 |
1 | 1 | 1 | 0 |
7 |
| 2011 |
1 | 1 |
2 | 2 | 2 |
0 | 1 | 0 | 0 |
9 |
| 2012 |
0 | 2 |
1 | 2 | 1 |
0 | 0 | 1 | 0 |
4 |
| Total |
2 |
12 |
59 |
18 |
91 |
Book chapters
| [2, B/11-1] |
K. Bousselam, G. Di Natale, M.-L. Flottes, B. Rouzeyre
On Countermeasures Against Fault Attacks on Advanced Encryption Standard,
To be published in "Fault Analysis in Cryptography", in the series "Springer-Verlag's Information Security and Cryptography", March 2011
|
| [1, B/10-1] |
K. Bousselam, G. Di Natale, M.-L. Flottes and B. Rouzeyre
Fault Detection in Crypto-Devices,
In book "Fault Detection", Wei Zhang (Ed.), ISBN: 978-953-307-037-7, InTech, March 2010
|
Journals
| [12, J/12-2] |
R. Possamai Bastos, G. Di Natale, M. Flottes, F. Lu, B. Rouzeyre
A New Recovery Scheme against Short-to-Long Duration Transient Faults in Combinational Logic,
Journal of Electronic Testing (JETTA), Springer, Accepted for publication
|
| [11, J/12-1] |
R. Possamai Bastos, F. Sill Torres, G. Di Natale, M. Flottes, B. Rouzeyre
Novel Transient-Fault Detection Circuit Featuring Enhanced Bulk Built-in Current Sensor with Low-Power Sleep Mode,
Microelectronics Reliability (Elsevier), DOI: 10.1016/j.microrel.2012.06.149
|
| [10, J/11-1] |
A. Savino, S. Di Carlo, G. Politano, A. Benso, A. Bosio, G. Di Natale
Statistical reliability estimation of microprocessor-based systems,
IEEE Transaction on Computer, Volume PP, Issue 99, October 2011, DOI: 10.1109/TC.2011.188
Watch the video on "Computing now"
|
| [9, J/09-2] |
G. Di Natale, M. Doulcier, M. L. Flottes, B. Rouzeyre
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard,
Journal of Electronic Testing (JETTA), Springer, Volume 25 Issue 4-5, August 2009, pp. 269-278, DOI: 10.1007/s10836-009-5106-6
|
| [8, J/09-1] |
G. Di Natale, M. Doulcier, M. L. Flottes, B. Rouzeyre
Self-Test Techniques for Crypto-Devices,
IEEE Transaction on VLSI Systems, pp. 1-5, 2009, DOI: 10.1109/TVLSI.2008.2010045
|
| [7, J/08-2] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto
March Test Generation Revealed,
IEEE Transaction on Computer, Volume 57, Issue 12, Dec. 2008 Page(s):1704 - 1713, DOI: 10.1109/TC.2008.105
|
| [6, J/08-1] |
A. Bosio, G. Di Natale
March Test BDN: A new March Test for Dynamic Faults,
Journal of Control Engineering and Applied Informatics (CEAI),
Nr.2, Volume 10, June 2008, pp. 3-9
|
| [5, J/07-1] |
A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto
March AB, a State-of-the-Art March Test for Realistic Static Linked Faults and Dynamic Faults in SRAMs,
IEE Proceedings Computers and Digital Techniques, Vol. 1, No. 3, May 2007, pp. 237-245
|
| [4, J/03-2] |
A. Benso, S. Di Carlo, G. Di Natale, M. Lobetti Bodoni, P. Prinetto,
Programmable Built-In Self-Testing of Embedded RAM Clusters in System-on-Chip Architectures,
IEEE Communications Magazine, Vol. 41, N. 9, September 2003, pp. 90-97
|
| [3, J/03-1] |
A. Benso, S. Di Carlo, G. Di Natale, J.F. Panico, P. Prinetto,
On-Line Self-Repair of Finite Impulse Response Filters,
IEEE Design and Test of Computers, May-June 2003, pp. 50-57
|
| [2, J/02-1] |
A. Benso, S. Chiusano, G. Di Natale, P. Prinetto,
An On-line BISTed RAM Architecture with Self Repair Capabilities,
IEEE Transaction on Reliability, Vol. 51 Issue. 1, Mar 2002, pp. 123, 128
|
| [1, J/01-1] |
A. Benso, S. Chiusano, G. Di Natale, M. Lobetti-Bodoni, P. Prinetto,
On-line & Off-line BIST in IP-Core Design,
IEEE Design and Test of Computers, September/October 2001, Vol. 18, N. 5, pp. 92-99
|
Conferences, Symposium, Workshops, Presentations
| [76, C/12-01] |
J. Darolt, A. Das, G. Di Natale, M.-L. Flottes, B. Rouzeyre, I. Verbauwhede
A New Scan Attack on Elliptic Curve Cryptosystems in presence of Industrial Design for Testability Structures,
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'12)
|
| [75, W/12-01] |
J. Darolt, A. Das, G. Di Natale, M.-L. Flottes, B. Rouzeyre, I. Verbauwhede
A New Scan Attack on RSA in Presence of Industrial Countermeasures,
Third International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE'12), Lecture Notes in Computer Science Volume 7275, pp. 89-104
|
| [74, S/12-02] |
J. Darolt, G. Di Natale, M-L. Flottes, B. Rouzeyre
On-chip test comparison for protecting confidential data in secure ICs,
IEEE European Test Symposium 2012 (ETS'12), DOI: 10.1109/ETS.2012.6233039
|
| [73, S/12-01] |
J. Darolt, G. Di Natale, M-L. Flottes, B. Rouzeyre
Are advanced DfT structures sufficient for preventing scan-attacks,
IEEE VLSI Test Symposium 2012 (VTS'12), pp. 246-251, DOI: 10.1109/VTS.2012.6231061
|
| [72, P/12-01] |
G. Di Natale, M. L. Flottes, R. Giroudeau, F. Hernandez
Exact Wafer Matching Process for 3D Wafer-to-Wafer Integration,
3D Integration: Applications, Technology, Architecture, Design, Automation, and Test Workshop (poster)
|
| [71, C/11-02] |
R. Possamai Bastos, G. Di Natale, M-L. Flottes, B. Rouzeyre
A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies,
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Vancouver (Canada), 3-5 Oct. 2011, pp.302-308, DOI: 10.1109/DFT.2011.15
|
| [70, C/11-01] |
R. Possamai Bastos, G. Di Natale, M-L. Flottes, B. Rouzeyre
How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?,
RADECS'2011: Conference on Radiation Effects on Components and Systems, Sevilla (Spain), pp. 635-642, DOI: 10.1109/RADECS.2011.6131361
|
| [69, P/11-01] |
J. Darolt, G. Di Natale, M-L. Flottes, B. Rouzeyre
New side-channel attack against scan chains,
CryptArchi'11: Cryptographic Architectures Embedded in Reconfigurable Devices, Germany (2011)
|
| [68, S/11-02] |
J. Darolt, G. Di Natale, M.L. Flottes, B. Rouzeyre
New security threats against chips containing scan chain structures,
IEEE International Symposium on Hardware-Oriented Security and Trust 2011 (HOST'11), June 2011 (San Dieog, CA, USA), pp. 105-110, DOI: 10.1109/HST.2011.5955005
|
| [67, S/11-01] |
J. Darolt, G. Di Natale, M.L. Flottes, B. Rouzeyre
Scan attacks and countermeasures in presence of scan response compactors,
IEEE European Test Symposium 2011 (ETS'11), May 2011 (Trondheim, Norwey), pp. 19-24, DOI: 10.1109/ETS.2011.30
|
| [66, W/11-02] |
G. Di Natale, M.L. Flottes, B. Rouzeyre, D. Real
Power Consumption Traces Realignment to Improve Differential Power Analysis,
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'11), April 2010, Cottbus (Germany)
|
| [65, W/11-01] |
R. Possamai Bastos, G. Di Natale, M-L. Flottes, B. Rouzeyre
Timing issues for an efficient use of concurrent error detection codes,
IEEE Latin American Test Workshop 2011 (LATW'11), pp. 1-6, DOI: 10.1109/LATW.2011.5985933
|
| [64, W/10-01] |
A. Bosio, G. Di Natale
Parallel Test of Identical Cores using Test Elevators in 3D circuits extended abstract,
IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST'10), Austin (Texas), October 2010
|
| [63, S/10-02] |
K. Bousselam, G. Di Natale, M.L. Flottes, B. Rouzeyre
Evaluation of Concurrent error detection techniques on the Advanced Encryption Standard,
IEEE International On-Line Testing Symposium 2010 (IOLTS,10), July 2010, Corfu, pp. 223-228, DOI: 10.1109/IOLTS.2010.5560196
|
| [62, P/10-03] |
G. Di Natale, M-L. Flottes, B. Rouzeyre
Waveforms re-alignment to improve DPA attacks,
CryptArchi'10: Cryptographic Architectures Embedded in Reconfigurable Devices, France (2010)
|
| [61, P/10-02] |
K. Bousselam, G. Di Natale, M.L. Flottes, B. Rouzeyre
Evaluation of Concurrent error detection techniques on the Advanced Encryption Standard,
IEEE European Test Symposium 2010 (ETS'10), May 2010 (Praha), pp. 252-252 (Poster), DOI: 10.1109/ETSYM.2010.5512741
|
| [60, P/10-01] |
G. Di Natale, M.-L. Flottes, B. Rouzeyre
Ensuring high testability without degrading security: Embedded Tutorial on "Test and Security",
Presented to IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10), April 2010, Vienna (Austria), DOI: 10.1109/DDECS.2010.5491831
|
| [59, S/10-01] |
G. Di Natale, M.L. Flottes, B. Rouzeyre
Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers,
IEEE International Symposium on Electronic Design, Test & Applications (DELTA 2010), Vietnam (Ho Chi Minh City), January 2010, pp. 256-261
|
| [58, P/09-05] |
G. Di Natale, M.L. Flottes, P. Maistri
Embedded Tutorial on "Test and Security",
Presented to IEEE European Test Symposium 2009 (ETS'09)
|
| [57, P/09-4] |
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
An Integrated Validation Environment for Differential Power Analysis,
DATE 2010, University Booth
|
| [56, P/09-3] |
Alberto Bosio, Giorgio Di Natale
LIFTING: an Open-Source Logic Simulator,
DATE 2010, University Booth
|
| [55, P/09-02] |
G. Di Natale, M.L. Flottes
Embedded Tutorial on "Test and Security",
Presented to IEEE Latin American Test Workshop 2009 (LATW'09)
|
| [54, W/09-01] |
G. Di Natale, M. L. Flottes, B. Rouzeyre
Execution Time Reduction of Differential Power Analysis Experiments,
IEEE Latin American Test Workshop 2009 (LATW'09)
|
| [53, W/08-14] |
Philipp Öhler, Sybille Hellebrand, Alberto Bosio, Giorgio Di Natale
Modularer Selbsttest und optimierte Reparaturanalyse für eingebettete Speicher,
Zuverlässigkeit und Entwurf, September 2008, pp. 49-56
|
| [52, C/08-13] |
G. Di Natale, M. L. Flottes, B. Rouzeyre
A Reliable Architecture for Substitution Boxes in Integrated Cryptographic,
International Conference on Design of Circuits and Integrated Systems, Grenoble, 2008
|
| [51, S/08-12] |
Stefano Di Carlo, Giorgio Di Natale, Riccardo Mariani
On-Line Instruction-checking in Pipelined Microprocessors,
IEEE International Asian Test Symposium (ATS 2008), 2008
|
| [50, S/08-11] |
Alberto Bosio, Giorgio Di Natale
LIFTING: a Flexible Open-Source Fault Simulator,
IEEE International Asian Test Symposium (ATS 2008), 2008
|
| [49, P/08-10] |
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
An Integrated Validation Environment for Differential Power Analysis,
SAME (Sophia Antipolis Micro Electronics) 2008 Forum
|
| [48, P/08-9] |
Alberto Bosio, Giorgio Di Natale
LIFTING: an Open-Source Logic Simulator,
SAME (Sophia Antipolis Micro Electronics) 2008 Forum
|
| [47, P/08-8] |
Di Natale G., Flottes M-L, Rouzeyre B.
An Integrated Validation Environment for Differential Power Analysis,
CryptArchi'08: Cryptographic Architectures Embedded in Reconfigurable Devices, France (2008)
|
| [46, P/08-7] |
G. Di Natale, M. L. Flottes, B. Rouzeyre
Stuck-at-Faults Test using Differential Power Analysis,
Low Power design on Test & Reliability Workshop (LPonTR 2008)
|
| [45, P/08-6] |
G. Di Natale, M. Doulcier, M. L. Flottes, B. Rouzeyre
Low-Cost Self-Test of Crypto Devices,
Workshop on Dependable and Secure Nanocomputing (wDSN 2008)
|
| [44, S/08-5] |
Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand
A Modular Memory BIST for Optimized Memory Repair,
IEEE International On-Line Testing Symposium (IOLTS 2008), July 2008, pp. 171-172
|
| [43, C/08-4] |
A. Bosio, G. Di Natale
March Test BDN: A new March Test for Dynamic Faults,
IEEE International Conference on Automation, Quality & Testing, Robotics (AQTR'08), May 2008, pp. 85-89
|
| [42, S/08-3] |
G. Di Natale, M. Doulcier, M.-L. Flottes, B. Rouzeyre
A Reliable Architecture for the Advanced Encryption Standard,
IEEE European Test Symposium 2008 (ETS'08), May 2008, pp. 13-18
|
| [41, P/08-2] |
G. Di Natale, M.-L. Flottes, B. Rouzeyre
Observability of Stuck-at-Faults with Differential Power Analysis,
IEEE Latin-American Test Workshop (LATW 2008), Puebla (Mexico), February 2008
|
| [40, S/08-1] |
G. Di Natale, M.-L. Flottes, B. Rouzeyre
An Integrated Validation Environment for Differential Power Analysis,
IEEE International Symposium on Electronic Design, Test & Applications (DELTA 2008), Hong Kong, January 2008, pp. 527-532
|
| [39, S/07-1] |
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
An On-Line Fault Detection Scheme for SBoxes in Secure Circuits,
IEEE International On-Line Testing Symposium (IOLTS 2007), Heraklion (Crete, Greece), July 2007, pp. 57-62
|
| [38, S/07-2] |
Mohammad Hosseinabady, M. H. Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC,
IEEE International On-Line Testing Symposium (IOLTS 2007), Heraklion (Crete, Greece), July 2007, pp. 205-206
|
| [37, P/07-3] |
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
A Dependable Parallel Architecture for SBoxes,
Reconfigurable Communication-Centric SoCs (ReCoSoc 2007), Montpellier : France (2007)
|
| [36, P/07-4] |
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
On-Line Self-Test of AES Hardware Implementations,
Workshop on Dependable and Secure Nanocomputing (DSN 2007), Edinburgh (UK)
|
| [35, P/07-5] |
Flottes M-L, Di Natale G., Rouzeyre B., Doulcier M.
Test and Security,
CryptArchi'07: Cryptographic Architectures Embedded in Reconfigurable Devices, France (2007)
|
| [34, W/07-6] |
Di Natale G., Flottes M.-L., Rouzeyre B.
A Novel Parity Bit Scheme for SBOX in AES Circuits,
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07), April 2007, pp. 267-271
|
| [33, C/06-1] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto
Automatic March Tests Generations for Static Linked Faults in SRAMs,
IEEE Design Automation and Test Conference in Europe (DATE 2006), Munich (D), March 2006, pp. 1-6
|
| [32, S/06-2] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto
22n March Test for Realistic Static Linked Faults in SRAMs,
IEEE European Test Symposium 2006 (ETS’06), May 2006, pp. 49-54
|
| [31, S/06-3] |
M. Hosseinabady, P. Lotfi-Kamran, G. Di Natale, S. Di Carlo, A. Benso, P. Prinetto
Single-Event Upset Analysis and Protection in High Speed Circuits,
IEEE European Test Symposium 2006 (ETS’06), May 2006, pp. 29-34
|
| [30, S/06-4] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto
Memory Fault Simulator for Static-Linked Faults,
IEEE Asian Test Symposium (ATS 2006), Fukuoka (J), November 2006
|
| [29, S/06-5] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto
ATPG For Dynamic Burn-In Test in Full-Scan Circuits,
IEEE Asian Test Symposium (ATS 2006), Fukuoka (J), November 2006
|
| [28, S/06-6] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto
Automatic March Tests Generation for Multi-Port SRAMs,
IEEE International Workshop on Electronic Design, Test & Applications (DELTA 2006), January 2006
|
| [27, W/06-7] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs,
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’06), April 2006, pp. 155-156
|
| [26, C/06-8] |
G. Di Natale, A. Serra, C. Turcotti
A board implementation for Fast APA Acoustic Echo Canceller using ADSP-21065L DSP,
IEEE International Conference on Automation, Quality & Testing, Robotics (AQTR’06), May 2006
|
| [25, W/06-9] |
A. Bosio, S. Di Carlo, G. Di Natale, M. Fischerova, T. Pikula, M. Simlastik
Interactive Educational Tool for Memory Testing,
6th European Workshop on Microelectronics Education (EWME’06), Stockholm (Sweden), June 2006
|
| [24, C/06-10] |
M. Fischerova, T. Pikula, M. Simlastik, A. Bosio, S. Di Carlo, G. Di Natale
A tool for teaching memory testing based on BIST,
Baltic Electronics Conference, 2006 International, Oct. 2006, pp. 1-4
|
| [23, S/05-1] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto,
Automatic March Tests Generation for Static and Dynamic Faults in SRAMs,
IEEE European Test Symposium, 2005, May 22-25 2005, pp. 122-127
|
| [22, W/05-2] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto,
AFSM-Based Deterministic Hardware TPG,
8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), April 13-16 2005, pp. 178-181
|
| [21, W/05-3] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri, C. Tibaldi,
PROMON: A Profile Monitor of Software Applications,
8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’05), April 13-16 2005, pp. 81-86
|
| [20, C/05-4] |
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto,
March AB, March AB1: New March Tests for Unlinked Dynamic Memory Faults,
IEEE International test Conference, Austin (Texas, USA), October 2005
|
| [19, C/05-5] |
T. Pikula, G. Di Natale, E. Gramatová,
Built-in Self-Test Generation for Delay Faults - a case study,
5th Electronic Circuits and Systems Conference (ECS’05), September 8-9, 2005, Bratislava (Repubblica Slovacca)
|
| [18, S/03-5] |
F. Bertuccelli, F. Bigongiari, A. Brogna, G. Di Natale, P. Prinetto, R. Saletti,
Exhaustive test of several dependable memory architectures designed by GRAAL tool,
IEEE 12th Asian Test Symposium, Nov. 2003, pp. 32-35
|
| [17, W/03-4] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri,
Data Criticality Estimation in Software Applications,
IEEE European Test Workshop, May 2003, Maastricht (NL), pp. 231-236
|
| [16, S/03-3] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, I. Solcia, L. Tagliaferri,
FAUST: FAUlt-injection Script-based Tool,
IEEE On-line Test Symposium, Kos (GR), July 2003, p. 160
|
| [15, S/03-2] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto,
A Watchdog Processor to Detect Data and Control Flow Errors,
IEEE On-line Test Symposium, Kos (GR), July 2003, pp. 144-148
|
| [14, C/03-1] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri,
Data Criticality Estimation in Software Applications,
IEEE International Test Conference, Charlotte (NC), October 2003, pp. 802-810
|
| [13, C/02-1] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto,
An Optimal Algorithm for the Automatic Generation of March Tests,
IEEE Design Automation and Test Conference in Europe (DATE 2002), Paris (F), February 2002, pp. 938-943
|
| [12, C/02-2] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto,
Static Analysis of SEU Effects on Software Applications,
IEEE International test Conference, Baltimore (Maryland), October 2002, pp. 500-508
|
| [11, S/02-3] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto,
Specification and Design of a new Memory Fault Simulator,
IEEE Asian Test Symposium (ATS 2002), November 2002, pp. 92-97
|
| [10, C/01-1] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto,
SEU Effect Analysis in Open-Source Router via a Distributed Fault Injection Environment,
IEEE Design Automation and Test Conference in Europe (DATE 2001), Munich (D), February 2001, pp. 219-223
|
| [9, W/01-2] |
A. Benso, S. Di Carlo, G. Di Natale, L. Tagliaferri, P. Prinetto,
Validation of a Software Dependability Tool via Fault Injection Experiments,
IEEE International On-Line Test Workshop (IOLTW 2001), Italy, July 2001, pp. 3-8
|
| [8, S/01-3] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri,
Control-Flow Checking Via Regular Expressions,
IEEE Asian Test Symposium (ATS 2001), Kyoto (J), November 2001, pp. 299-303
|
| [7, S/01-4] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto,
Memory Read Faults: Taxonomy and Automatic Test Generation,
IEEE Asian Test Symposium (ATS 2001), Kyoto (J), November 2001, pp. 157-163
|
| [6, W/01-5] |
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri,
Software Dependability Techniques validated via Fault Injection Experiments,
Proc. RADECS 2001, Grenoble (F), September 2001, pp. 269-274
|
| [5, C/01-6] |
G. Di Natale, S. Chiusano, P. Prinetto, F. Bigongiari,
GRAAL: a Tool for Highly Dependable SRAMs Generation,
IEEE International Test Conference (ITC01), USA, October 2001
|
| [4, W/00-1] |
A. Benso, S. Chiusano, S. Di Carlo, G. Di Natale, P. Prinetto, M. Lobetti-Bodoni,
An effective distributed BIST architecture for RAMs,
IEEE European Test Workshop (ETW00), Lisbon (P), May 2000, pp. 119-124
|
| [3, W/00-2] |
A. Benso, S. Chiusano, G. Di Natale, M. Lobetti-Bodoni, P. Prinetto,
A family of Self-Repair SRAM cores,
International On-Line Test Workshop (IOLTW00), Majorca (ES), July 2000, pp. 214-218
|
| [2, C/00-3] |
A. Benso, S. Di Carlo, G. Di Natale, M. Lobetti-Bodoni, P. Prinetto,
A programmable BIST architecture for clusters of Multiple-Port SRAMs,
IEEE International Test Conference (ITC00), Atlantic City (NJ), USA, October 2000, pp. 557-566
|
| [1, C/00-4] |
A. Benso, R. Mariani, G. Di Natale, P. Prinetto,
On Evaluating DSP-based Architectures for Space Application,
XV Conference on Design of Circuits and Integrated Systems (DCIS’2000), Montpellier (F), November 2000, pp. 421-426
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