Today at LIRMM lab
My current research activity investigates new energy-efficient and adaptive multiprocessor system architectures for high-performance computing applications. This activity is conducted within the Adaptive Computing group (ADAC) of the SysMIC team-project.
With the increase in the integration of functions, modern embedded systems have become very smart and sophisticated. The typical examples of this tendency are last generation mobile phones, which provide users with a large panel of facilities for communication, music, video display, built-in camera, Internet access, etc. These facilities are achieved by applications processing huge amounts of information, referred to as data-intensive applications. Such applications are also characterized by multi-clock behaviors since they often include components operating at different activation rates during execution.
Embedded systems often have real-time constraints. For instance, in a video processing application, there are usually rate or deadline constraints imposed to image display. For this purpose, execution platforms must provide the required computational power. Parallelism plays a central role in the answer to this expectation. The integration of multiple cores or processors on a single chip, referred to as multiprocessor systems-on-chip (MPSoCs) is a key solution to provide applications with sufficient performance at lower energy costs for execution. In order to find a good compromise between performance and energy consumption, resource heterogeneity is exploited in MPSoCs by including processing elements with different characteristics. For example, core processing units are combined with accelerators such as graphic processing units or field-programmable gate arrays. Besides heterogeneity, adaptivity is another important feature of modern embedded systems. It enables to manage in a flexible manner the performance parameters w.r.t. variations of system environment and execution platform.
In such a context, the development of modern embedded systems has become very complex. It raises a number of challenges considered in the contributions of this document, as follows:
- First, since MPSoCs are distributed systems, how can one successfully address their design correctness, such that the functional properties of deployed multi-clock applications can be guaranteed? This is studied by considering a correct-by-construction design methodology for these applications on multiprocessor platforms.
- Second, for data-intensive applications to be executed on such platforms, the next question is how can one adequately deal with their design and analysis, while fully taking into account their reactive nature and their potential parallelism?
- Third, when considering the execution of these applications on MPSoCs, the final question is how can one analyze their non functional properties (for instance, execution time or energy) in order to predict their execution performances? The answer to this question is expected to serve for the exploration of complex design spaces.
My research activity aims to answer the above three challenges in a pragmatic way, by adopting a model-based vision. For this purpose, it considers two complementary dataflow modeling paradigms: the polychronous modeling related to the synchronous reactive approach, and the repetitive structure modeling related to array-oriented data parallel programming. The former paradigm enables to reason on multi-clock systems in which components interact without assuming the existence of a global or reference clock. The latter paradigm offers a powerful specification of the massive parallelism in a system as factorized repetitive dependency relations over multidimensional structures.