Current Management Positions

co-Director of the European Associated Laboratory (LEA) "LAFISI" LEA LAFISI web site

Deputy Director of the GDR SoC-SiP (French Network for Microelectronics Research) GDR SOCSIP web site

Member of the Scientific Council of the INS2I Institute of CNRS CSI of INS2I web site

Head of Microelectronics Department - LIRMM Laboratory MICROELECTRONICS DEPT. web site

Manager of the research group "Test, Reliability and Power Consumption of Digital Systems and Memories" - LIRMM Laboratory

Academic Positions

Since 2005 : CNRS Research Director in the Microelectronics Department of LIRMM

1994-2005 : CNRS Researcher in the Microelectronics Department of LIRMM

1992-1994: Associate Professor, EERIE (Engineering School in Electronics and Computer Science), Nîmes, France

Biography

Patrick GIRARD received a M.Sc. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier, France, in 1988 and 1992 respectively. He also received the “Habilitation à Diriger des Recherches” degree from the University of Montpellier, France, in 2003. He is currently Research Director at CNRS (French National Center for Scientific Research), and Head of the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) - France. He is also co-Director of the European Associated Laboratory « LAFISI » (French-Italian Research Laboratory on Hardware-Software Integrated Systems) created in 2012 by the CNRS with the Politecnico di Torino, Italy. His research interests include all aspects of digital testing and memory testing, with emphasis on critical constraints such as timing and power. Reliability and fault tolerance, power modeling and estimation, as well as design and test of 3D ICs are also part of his new research activities.
Patrick Girard is Technical Activities Chair of the Test Technology Technical Council (TTTC) of the IEEE Computer Society. From 2006 to 2010, he was Vice-Chair of the European TTTC (ETTTC) of the IEEE Computer Society. He has served on numerous conference committees including ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design Automation and Test in Europe (DATE), IEEE International Test Conference (ITC), IEEE International Conference on Computer Design (ICCD), IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), and ACM/IEEE International Symposium on Low Power Electronic Design (ISLPED). Patrick Girard is the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE). He is an Associate Editor of the IEEE Transactions on VLSI Systems and the Journal of Electronic Testing – Theory and Applications (JETTA - Springer). From 2005 to 2009, he was an Associate Editor of the IEEE Transactions on Computers. He is co-editor of the book “Power-Aware Testing and Test Strategies for Low Power Devices” and co-author of the book “Advanced Test Methods for SRAMs – Effective Solutions for Dynamic Fault Detection in Nanoscale Technologies”, both published by Springer in 2009.
Patrick Girard has been involved in several European research projects (ESPRIT III ATSEC, EUREKA MEDEA, MEDEA+ ASSOCIATE, IST MARLOW, MEDEA+ NanoTEST, CATRENE TOETS, ENIAC ELESIS) and has managed industrial research contracts with major companies like Infineon Technologies, Intel, Atmel, ST-Ericsson, STMicroelectronics, etc. He has supervised 28 PhD dissertations and has published 6 books or book chapters, 44 journal papers, and more than 160 conference and symposium papers on these fields. Patrick Girard is a Senior Member of IEEE and a Golden Core Member of the IEEE Computer Society.