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F. Azais, S. Bernard, Y. Bertrand, M.L.
Flottes, P. Girard, C. Landrault, L. Latorre, S. Pravossoudovitch, M.
Renovell, et B. Rouzeyre, “Test de Circuits et de Systèmes Intégrés”,
ISBN 2-7462-0864-4, Editions Hermes Science, 2004.
P. Girard, X. Wen et N. Touba, chapter “Low
Power Testing” de l’ouvrage “System-on-Chip Test Architectures:
Nanometer Design for Testability”, ISBN: 978-0-12-373973-5, Morgan
Kaufmann - Elsevier, 2007.
N. Badereddine, P. Girard, S.
Pravossoudovitch, A. Virazel et C. Landrault, chapter “Scan Cell
Reordering for Peak Power Reduction during Scan Test Cycles” de
l’ouvrage “Vlsi-Soc: From Systems To Silicon”, ISBN 978-0-387-73660-0,
Springer, Boston, 2007.
P. Girard, N. Nicolici and X. Wen,
“Power-Aware Testing and Test Strategies for Low Power Devices”, ISBN:
978-1-4419-0927-5, Springer, New York, 2009.
A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch et A. Virazel, “Advanced Test Methods for SRAMs –
Effective Solutions for Dynamic Fault Detection in Nanoscale
Technologies”, ISBN: 978-1-4419-0937-4, Springer, New York,
2009.
P. Girard et H.J. Wunderlich, chapter
“Models
for Power-Aware Testing” de l’ouvrage “Models in Hardware Testing”,
ISBN: 978-90-481-3281-2, Springer Netherlands, 2009.
Y. Cheng, A. Todri-Sanial, A. Bosio, P. Girard, A. Virazel, P. Vivet et M. Belleville,
chapter “Electromigration Alleviation Techniques for 3D Integrated Circuits” of the book
“High Performance Computing for Big Data: Methodologies and Applications”, ISBN 9781498783996,
Chapman & Hall / CRC Press, Taylor and Francis Group, 2017.
D. Auvergne, M. Renovell, T. Riesgo et P.
Girard, Actes “DCIS: Conference on Design of Circuits and Integrated
Systems, Montpellier, France, 21-24 Novembre 2000”.
Département Microélectronique du LIRMM, Actes
“VLSI-SOC'01: 11th IFIP International Conference on Very Large Scale
Integration, Montpellier, France, 3-5 Décembre 2001”.
P. Girard, A. Osseiran et M.T. Chew, Actes
“IEEE International Workshop on Electronic Design, Test and
Applications, Kuala Lumpur, Malaisie, 17-19 Janvier 2006”, ISBN
0-7695-2500-8, IEEE Computer Society.
P. Girard, M. Masmoudi, J. Mouine et M.
Renovell, Actes “IEEE International Conference on Design & Test of
Integrated Systems in Nanoscale Technology, Tunis, Tunisie, 5-7
Septembre 2006”, ISBN 0-7803-9726-6, IEEE CAS Society.
E. Gramatova, A. Pawlak, P. Girard, A.
Krasniewski et T. Garbolino, Actes “IEEE Workshop on Design and
Diagnostics of Electronic Circuits and Systems, Cracovie, Pologne,
11-13 Avril 2007”, ISBN 1-4244-1161-0, IEEE Computer
Society.
M. Sonza Reorda, P. Girard, Z. Peng, C.
Landrault et C. Metra, Actes “IEEE European Test Symposium, Verbania,
Italie, 25-29 Mai 2008”, ISBN 978-0-7695-3150-2, IEEE
Computer Society.
L. Anghel, P. Girard, M. Violante, B. Becker et G. Di Natale, Actes
“IEEE European Test Symposium, Annecy, France, 28-31 Mai 2012”, ISBN
978-1-4673-0696-6, publié par IEEE Computer Society.
P. Girard, Z. Peng, M. Sonza Reorda et G. Di Natale, Actes “IEEE
European Test Symposium, Avignon, France, 27-31 Mai 2013”, ISBN
978-1-4673-6375-4, publié par IEEE Computer Society.
S. Mohanty, N. Ranganathan, S. Bhanja, S. Kundu, P. Girard et P.
Ghosal, Actes “IEEE Computer Society Annual Symposium on VLSI, Tampa,
Floride, USA, 9-11 Juillet 2014”, ISBN 978-1-4799-3763-9, publié par
IEEE Computer Society.
A. Todri, G. Di Natale, P. Girard, M. Belleville, S. Mohanty et M.
Comte, Actes “IEEE Computer Society Annual Symposium on VLSI,
Montpellier, France, 8-10 Juillet 2015”, ISBN 978-1-4799-8718-4, publié
par IEEE Computer Society.
P. Girard, C. Landrault et S. Pravossoudovitch,
“A Reliable Method for Delay-Fault Diagnosis”, IEE Electronics Letters,
Vol. 27, N° 20, pp. 1841-1843, Septembre 1991.
P. Girard, C. Landrault et S. Pravossoudovitch,
“Delay-Fault Diagnosis by Critical Path Tracing”, IEEE Design &
Test of Computers, Vol. 9, N° 4, pp. 27-32, Décembre 1992.
P. Cavallera, P. Girard, C. Landrault et S.
Pravossoudovitch, “Delay Fault Propagation in Synchronous Sequential
Circuits”, IEE Electronics Letters, Vol. 30, N° 10, pp. 765-767, Mai
1994.
P. Girard, C. Landrault et S. Pravossoudovitch,
“An Advanced Diagnostic Method for Delay Faults in Combinational Faulty
Circuits”, JETTA Journal of Electronic Testing - Theory and
Applications, Kluwer, Vol. 6, N° 3, pp. 277-294, Juin 1995.
P. Girard, C. Landrault, S. Pravossoudovitch et
B. Rodriguez, “Delay Fault Diagnosis in Sequential Circuits Based on
Path Tracing”, INTEGRATION, the VLSI journal, Vol. 19, N° 3, pp.
199-218, Novembre 1995.
P. Girard, C. Landrault, S. Pravossoudovitch et
D. Severac, “Technique for Reducing Power Consumption in CMOS
Circuits”, IEE Electronics Letters, Vol. 33, N° 6, pp. 485-486, Mars
1997.
P. Girard, C. Landrault, V. Moreda et S.
Pravossoudovitch, “BIST Test Pattern Generator for Delay Testing”, IEE
Electronics Letters, Vol. 33, N° 17, pp. 1429-1430, Août 1997.
P. Girard, C. Landrault, S. Pravossoudovitch et
D. Severac, “Reduction of Power Consumption during Test Application by
Test Vector Ordering”, IEE Electronics Letters, Vol. 33, N° 21, pp.
1752-1754, Octobre 1997.
P. Girard, C. Landrault, S. Pravossoudovitch et
D. Severac, “A Non-Iterative Gate Resizing Algorithm for High Reduction
in Power Consumption”, INTEGRATION, the VLSI journal, Vol. 24, N° 1,
pp. 37-52, Décembre 1997.
P. Girard, C. Landrault, V. Moreda, S.
Pravossoudovitch and A. Virazel, “A Scan-BIST Structure to Test Delay
Faults in Sequential Circuits”, JETTA Journal of Electronic Testing -
Theory and Applications, Kluwer, Vol. 14, N° 1/2, pp. 95-102, Avril
1999.
S. Manich, A. Gabarro, M. Lopez, J. Figueras,
P. Teixeira, M.B. Santos, P. Girard, L. Guiller, C. Landrault et S.
Pravossoudovitch, “Low Power BIST by Filtering Non-Detecting Vectors”,
JETTA Journal of Electronic Testing - Theory and Applications, Kluwer,
Vol. 16, N°3, pp. 193-202, Juin 2000.
A. Virazel, R. David, P. Girard, C. Landrault
et S. Pravossoudovitch, “Delay Fault Testing: Choosing Between Random
SIC and Random MIC Test Sequences”, JETTA Journal of Electronic Testing
- Theory and Applications, Kluwer, Vol. 17, N°3/4, pp. 233-241, Août
2001.
R. David, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “Random Adjacent Sequences: An
Efficient Solution for Logic BIST”, SOC Design Methodology, revue
publiée par Kluwer Academic Publishers, ISBN 1-4020-7148-5, pp.
413-424, Janvier 2002.
P. Girard, “Survey of Low-Power Testing of
VLSI Circuits”, IEEE Design & Test of Computers, Vol. 19, N° 3, pp.
82-92, mai-juin 2002.
R. David, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “Hardware Generation of Random Single
Input Change Test Sequences”, JETTA Journal of Electronic Testing -
Theory and Applications, Kluwer, Vol. 18, N° 2, pp. 145-157, Avril 2002.
P. Girard, C. Landrault, S. Pravossoudovitch,
A. Virazel et H.J. Wunderlich, “High Defect Coverage with Low-Power
Test Sequences in a BIST Environment”, IEEE Design & Test of
Computers, Vol. 19, N° 5, pp. 44-52, Septembre-octobre 2002.
C. Fagot, O. Gascuel, P. Girard et C.
Landrault “A Ring Architecture Strategy for BIST Test Pattern
Generation”, JETTA Journal of Electronic Testing - Theory and
Applications, Kluwer, Vol. 19, N° 3, pp. 223-231, Juin 2003.
Y. Bonhomme, P. Girard, L. Guiller, C.
Landrault et S. Pravossoudovitch, “Power-Driven Routing-Constrained
Scan Chain Design”, JETTA Journal of Electronic Testing - Theory and
Applications, Kluwer, Vol. 20, N° 6, pp. 647-660, Decembre 2004.
P. Girard, O. Héron, S. Pravossoudovitch et M.
Renovell, “Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAS”,
JETTA Journal of Electronic Testing - Theory and Applications,
Springer, Vol. 21, N° 1, pp. 43-55, Février 2005.
S. Borri, M. Hage Hassan, L. Dilillo, P.
Girard, S. Pravossoudovitch et A. Virazel, “Analysis of Dynamic Defects
in Embedded-SRAMs: Implications for Memory Test”, JETTA Journal of
Electronic Testing - Theory and Applications, Springer, Vol. 21, N° 2,
pp. 169-179, Avril 2005.
P. Girard et Y. Bonhomme, “Scan Chain Design
Based on Efficient Tradeoff Between Test Power and Scan Routing”, JOLPE
- Journal on Low Power Electronics, American Scientific Publishers,
Vol. 1, N° 1, pp. 85-95, Avril 2005.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel, S. Borri et M. Hage-Hassan, “Efficient March Test Procedure
for Dynamic Read Destructive Fault Detection in SRAM Memories”, JETTA
Journal of Electronic Testing - Theory and Applications, Springer, Vol.
21, N° 5, pp. 551-561, Octobre 2005.
Y. Bonhomme, P. Girard, L. Guiller, C.
Landrault, S. Pravossoudovitch et A. Virazel, “A Gated Clock Scheme for
Low Power Testing of Logic Cores”, JETTA Journal of Electronic Testing
- Theory and Applications, Springer, Vol. 22, N° 1, pp. 89-99, Février
2006.
P. Girard, O. Héron, S. Pravossoudovitch et M.
Renovell, “An Efficient BIST Architecture for Delay Faults in the Logic
Cells of Symmetrical SRAM-Based FPGAs”, JETTA Journal of Electronic
Testing - Theory and Applications, Springer, Vol. 22, N° 2, pp.
161-172, Avril 2006.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel, S. Borri et M. Hage Hassan, “ADOFs and Resistive-ADOFs in SRAM
Address Decoders: Test Conditions and March Solutions”, JETTA Journal
of Electronic Testing - Theory and Applications, Springer, Vol. 22, N°
3, pp. 287-296, June 2006.
L. Dilillo, P. Rosinger, B.H. Al-Hashimi et P.
Girard, “Reducing Power Dissipation in SRAM During Test”, JOLPE -
Journal on Low Power Electronics, American Scientific Publishers, Vol.
2, N° 2, pp. 271-280, Août 2006.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et M. Bastian, “Analysis and Test of Resistive-Open Defects in
SRAM Pre-Charge Circuits”, JETTA Journal of Electronic Testing - Theory
and Applications, Springer, Vol. 23, N° 5, pp. 435-444, Octobre 2007.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel, S. Borri et M. Hage-Hassan, “New March Elements for Address
Decoder Open and Resistive Open Fault Detection in SRAM Memories”, JICS
Journal of Integrated Circuits and Systems, Vol. 3, N° 1, pp. 7-12,
2008.
N. Badereddine, Z. Wang, P. Girard, K.
Chakrabarty, A. Virazel, S. Pravossoudovitch et C. Landrault, “A
Selective Scan Slice Encoding Technique for Test Data Volume ane Test
Power Reduction”, JETTA Journal of Electronic Testing - Theory and
Applications, Special Issue on “Low Power Test”, Springer, Vol. 24, N°
4, pp. 353-364, August 2008.
A. Ney, P. Girard, S. Pravossoudovitch, A.
Virazel et M. Bastian, “Analysis of Resistive-Open Defects in SRAM
Sense Amplifiers”, IEEE Transactions on VLSI, Vol. 17, N° 10, pp.
1556-1559, October 2009.
O. Ginez, J.M. Daga, P. Girard, C. Landrault,
S. Pravossoudovitch et A. Virazel, “A SPICE-Like 2T-FLOTOX Core-Cell
Model for Defect Injection and Faulty Behavior Prediction in eFlash”,
JETTA Journal of Electronic Testing - Theory and Applications,
Springer, Vol. 25, N° 2-3, pp. 127-144, Juin 2009.
J.Vial, A. Virazel, A. Bosio, P. Girard, C.
Landrault, et S. Pravossoudovitch, “Is TMR Suitable for Yield
Improvement?”, IET Computers & Digital Techniques, Vol. 3, N° 6, pp
581-592,
Revue publiée par IET, ISSN 1751-8601, Novembre 2009.
K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S.
Kajihara, P. Girard, L.T. Wang, et M. Tehranipoor, “High Launch
Switching Activity Reduction in At-Speed Scan Testing using CTX: A
Clock-Gating-Based Test Relaxation and X-Filling Scheme”, IEICE Trans.
On Fundamentals/Commun./Electron./Inf. & Syst., Vol.E93-D, N° 1,
Janvier 2010.
A. Bosio, P. Girard, S. Pravossoudovitch et A.
Virazel, “A Comprehensive Framework for Logic Diagnosis of Arbitrary
Defects”, IEEE Transactions on Computers, Vol. 59, N° 3, pp 289-300,
Mars 2010.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Virazel, M. Tehranipoor, X. Wen et N. Ahmed, “A
Comprehensive Analysis of Transition Fault Coverage and Test Power
Dissipation for LOS and LOC Schemes”, ASP Journal of Low Power
Electronics, Vol. 6, N° 2, pp 359-374, Août 2010.
J.Vial, A. Virazel, A. Bosio, L. Dilillo, P.
Girard, et S. Pravossoudovitch, “SoC yield Improvement Using TMR
Architectures for Manufacturing Defect Tolerance in Logic Cores”,
IARIA International Journal On Advances in Systems and Measurements,
Vol. 1 & 2, Juillet 2010.
P. Rech, J.M. Gallière, P. Girard, F.
Wrobel, F. Saigné et L. Dilillo,“Impact of Resistive-Open Defects on
SRAM Error Rate Induced by Alpha Particles and Neutrons”, IEEE
Transactions on Nuclear Sciences, Vol. 58, N° 3, Part 2, pp. 855-861,
2011.
J. Ma, M. Tehranipoor et P. Girard, “A Layout-Aware Pattern Grading
Procedure for Critical Paths Considering Power Supply Noise and
Crosstalk”, JETTA Journal of Electronic Testing - Theory and
Applications, Springer, Vol. 28, N° 2, pp. 201-214, Avril 2012.
P.D. Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch, B. Godard, G. Feste et L. Vachez “Analysis and Fault
Modeling of Actual Resistive Defects in ATMEL eFlash
Memories”, JETTA Journal of Electronic Testing - Theory and
Applications, Springer, Vol. 28, N° 2, pp. 215-228, Avril 2012.
H. Salmani, W. Zhao, M. Tehranipoor, S. Chakravarty, P. Girard and X.
Wen, “Layout-Aware Pattern Evaluation and Analysis for Power-Safe
Application of TDF Patterns”, JOLPE - Journal on Low Power Electronics,
American Scientific Publishers, Vol. 8, N° 2, pp. 248-258, Avril 2012.
P. Rech, J.M. Gallière, P. Girard, A. Griffoni, J. Boch, F. Wrobel, F.
Saigné et L. Dilillo, “Neutron-Induced Multiple Bit Upsets on Two
Commercial SRAMs under Dynamic-Stress”, IEEE Transactions on Nuclear
Science, Vol. 54, N° 12, pp. 893 – 899, Août 2012.
R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Virazel et N. Badereddine, “Impact of Resistive-Bridging Defects in
SRAM at Different Technology Nodes”, JETTA Journal of Electronic
Testing - Theory and Applications, Springer, Vol. 28, N° 3, pp.
317-329, 2012.
A.
Todri, A. Bosio, L. Dilillo, P. Girard et A. Virazel, “Uncorrelated
Power Supply Noise and Ground Bounce Consideration for Test Pattern
Generation”, IEEE Transactions on VLSI Systems, Vol. 21, N° 5, pp.
958-970, May 2013.
G.
Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel, S.
McClure, A.D. Touboul, F. Wrobel et F. Saigné, “Testing a Commercial
MRAM under Neutron and Alpha Radiation in Dynamic Mode”, IEEE
Transactions on Nuclear Sciences, Vol. 60, N° 4, pp. 2617-2622, Août
2013.
P. Bernardi, M. De Carvalho, E. Sanchez, M. Sonza Reorda, A. Bosio, L.
Dilillo, M. Valka and P. Girard, “Fast Power Evaluation for Effective
Generation of Test Programs Maximizing Peak Power Consumption”, JOLPE -
Journal on Low Power Electronics, American Scientific Publishers, Vol.
9, N° 2, pp. 253-263, Août 2013.
J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G.
Prenat, J.Alvarez-Herault et K. McKay, “A Complete Resistive-Open
Defect Analysis for Thermally Assisted Switching MRAMs”, IEEE
Transactions on VLSI Systems, Vol. 22, N° 11, pp. 2326-2335, Novembre
2014.
A. Todri, S. Kundu, P. Girard, A. Bosio, L. Dilillo et A. Virazel,
“Globally Constrained Locally Optimized 3D Power Delivery Networks”,
IEEE Transactions on VLSI Systems, Vol. 22, N° 10, pp. 2131-2144,
Octobre 2014.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri, A. Virazel, J. Mekki, M. Brugger, F. Wrobel et F. Saigné, “An
SRAM Based Monitor for Mixed-Field Radiation Environments”, IEEE
Transactions on Nuclear Science, Vol. 61, N° 4, pp. 1663-1671, Août
2014.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri, A. Virazel, H. Puchner, C. Frost, F. Wrobel et F. Saigné,
“Multiple Cell Upset Classification in Commercial SRAMs”, IEEE
Transactions on Nuclear Science, Vol. 61, N° 4, pp. 1747-1755, Août
2014.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri, A. Virazel, J. Mekki, M. Brugger, F. Wrobel et F. Saigné,
“Evaluating a Radiation Monitor for Mixed-Field Environments based on
SRAM Technology”, IOP Journal of Instrumentation (JINST), Vol. 9, N° 5,
pp. C05052, Mai 2014.
D.A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, S.
Pravossoudovitch et H.J. Wunderlich, “A New Hybrid Fault-Tolerant
Architecture for Digital CMOS Circuits and Systems”, JETTA Journal of
Electronic Testing - Theory and Applications, Springer, Vol. 30, N° 4,
pp. 401-413, Août 2014.
A. Tomita, X. Wen, Y. Sato, S. Kajihara, K. Miyase, S. Holst, P.
Girard, M. Tehranipoor et L.T. Wang, “On Achieving Capture Power Safety
in At-Speed Scan-Based Logic BIST”, IEICE Trans. On
Fundamentals/Commun./Electron./Inf. & Syst., Vol.E97-D, N° 10,
Octobre 2014.
J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard,
J.Alvarez-Herault et K. McKay, “Dynamic Compact Model of
Self-Referenced Magnetic Tunnel Junction”, IEEE Transactions on
Electron Devices, Vol. 61, N° 11, pp. 3877-3882, Novembre 2014.
Z. Sun, A. Bosio, L. Dilillo, P. Girard, A. Virazel, S.
Pravossoudovitch et E. Auvray, “Intra-Cell Defects Diagnosis”, JETTA,
Journal of Electronic Testing - Theory and Applications, Springer, Vol.
30, N° 5, pp. 541-555, 2014.
L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Virazel et N.
Baderedddine, “On the Test and Mitigation of Malfunctions in Low-Power
SRAMs”, JETTA, Journal of Electronic Testing - Theory and Applications,
Springer, Vol. 30, N° 5, pp. 611-627, 2014.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Virazel, P. Cocquerez, J.L. Autran, A. Litterio, F. Wrobel et F.
Saigné, “90nm SRAM Static and Dynamic mode Real-Time Testing at
Concordia Station in Antarctica”, IEEE Transactions on Nuclear Science,
Vol. 61, N° 6, pp. 3389-3394, Décembre 2014.
G.
Tsiligiannis, L. Dilillo, V. Gupta, A. Bosio, P. Girard, A. Virazel, H.
Puchner, A. Bosser, A. Javanainen, A. Virtanen, C. Frost, F. Wrobel, L.
Dusseau et F. Saigné, “Dynamic Test Methods for COTS SRAMs”, IEEE
Transactions on Nuclear Science, Vol. 61, N° 6, pp. 3095-3102, Décembre
2014.
M. Valka, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Debaut et
S. Guilhot “Design for Test and Diagnosis of Power Switches”, Journal
of Circuits, Systems, and Computers, Octobre 2015 (Vol. 25, N° 3, Mars 2016).
I. Wali, A. Virazel, A. Bosio, P. Girard, S. Pravossoudovitch et M.
Sonza Reorda, “A Hybrid Fault-Tolerant Architecture for Highly Reliable
Processing Cores”, JETTA, Journal of Electronic Testing - Theory and
Applications, Springer, Vol. 32, N° 2, pp. 147-161, Avril 2016.
K. Juneja, D. Adil Patel, R. Kumar Immadi, B. Singh, S. Naudet, P.
Agarwal, A. Virazel et P. Girard, “An Effective Power-Aware At-Speed
Test Methodology for IP Qualification and Characterization”, JETTA,
Journal of Electronic Testing - Theory and Applications, Springer, Vol.
32, N° 6, pp.721-733, Décember 2016.
I. Wali, B. Deveautour, A. Virazel, A. Bosio, P. Girard et M. Sonza
Reorda, “A Low-cost Reliability vs. Cost Trade-off Methodology for
Selectively Harden Logic Circuits”, JETTA, Journal of Electronic
Testing - Theory and Applications, Springer, Vol. 33, N° 1, pp. 25-36,
Février 2017.
A. Nocua, A. Virazel, A. Bosio, P. Girard et C. Chevalier, “HPET: A
Hybrid Power Estimation Technique to Improve IP Power Models Accuracy”,
ASP Journal of Low Power Electronics, American Scientific Publishers,
Vol. 13, N° 2, pp. 10-28, Mars 2017.
A. Nocua, A. Virazel, A. Bosio, P. Girard et C. Chevalier, “HPET: An
Efficient Hybrid Power Estimation Technique to Improve High-Level Power
Characterization”, Journal of Circuits, Systems, and Computers, Vol.
26, N° 8, Août 2017.
A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi et M. Sonza
Reorda, “Microprocessors Testing: Functional meets Structural Test”,
Journal of Circuits, Systems, and Computers, Vol. 26, N° 8, Août 2017.
A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi, M. Sonza
Reorda et E. Auvray, “Scan-Chain Intra-Cell Aware Testing”, IEEE
Transactions on Emerging Topics in Computing, Vol. 6, N° 2, Avril-Juin 2018.
B. Deveautour, A. Virazel, P. Girard, et V. Gherman, “Exploring
Advantages of Approximate Computing in Selective Hardening of
Arithmetic Circuits”, JETTA, Journal of Electronic Testing - Theory and
Applications, Springer, révisions mineures, soumis en Mai 2019.
M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “A Test
Pattern Generation Technique for Approximate Circuits Based on an
ILP-formulated Pattern Selection Procedure”, IEEE Transactions on
Nanotechnology, DOI: 10.1109/TNANO.2019.2923040, Juin 2019.
M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “A
Survey of Testing Techniques for Approximate Integrated Circuits”,
Proceedings of IEEE (IF=10.69), accepté et à paraître, Septembre 2019.
Aibin Yan, Yuanjie Hu, Jie Cui, Zhili Chen, P. Girard et Xiaoqing Wen,
“Information Assurance through Redundant Design: A Novel TNU Error
Resilient Latch for Harsh Radiation Environment”, IEEE Transactions on
Computers, revisions majeures, soumis en Avril 2019.
Aibin Yan, Kang Yang, Jie Cui, P. Girard et Xiaoqing Wen, “A Novel
Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch
Design for Space Applications”, proposé à IEEE Transactions on
Aerospace and Electronic Systems, Mai 2019.
Aibin Yan, Kang Yang, Jie Song, Yafei Ling, P. Girard et Xiaoqing Wen,
“Novel Effective Soft Error Rate Estimation based on Vectors and
Probability for Nano-Scale CMOS Circuits”, proposé à IEEE Transactions
on Device and Materials Reliability, Juin 2019.
Aibin Yan, Yafei Ling, Jie Cui, Zhili Chen, Jie Song, P. Girard et
Xiaoqing Wen, “Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells
based Multiple-Node-Upset-Tolerant Latch Designs”, proposé à IEEE
Transactions on Circuits and Systems I, Août 2019.
Aibin Yan, Zhen Wu, Jie Cui, Hao Zheng, P. Girard et Xiaoqing Wen,
“Novel SEDU Self-Recoverable and SET Pulse Filterable Latch Designs for
Low Power IoT Applications”, proposé à IEEE Transactions on VLSI
Systems, Août 2019.
B. Deveautour, M. Traiola, A. Virazel et P. Girard, “A Novel Low-Cost
High-Efficiency Approximate-TMR Architecture”, proposé à Future
Generation Computer Systems - The International Journal of eScience,
Springer (IF=5.768), September 2019.
M.
Valka, P. Debaud, S. Guilhot, M. Broutin, A. Bosio et P. Girard,
“Efficient Power Suppy Noise Measurement Based on Timing Uncertainty”,
Patent n° 13756337.5 - 1560, 8 Août 2013.
M. Valka, P. Debaud, S. Guilhot, A. Bosio et P. Girard, “Adaptive
Voltage Scaling Mechanism Based on Voltage Shoot Measurement”, Patent
n° PCT/EP2013/066669, 8 Août 2013.
N. Badereddine, L. Zordan, P. Girard et A. Bosio, “A Built-in Scheme
for Testing and Repairing Voltage Regulators of Low-Power SRAMs”,
Patent N° 13/862,513, Avril 2013.
N. Badereddine, L. Zordan, P. Girard et A. Bosio, “Assist Circuits for
SRAM Testing”, Patent N° 14/270,555, Mai 2014.
P. Girard, “Low Power Testing of VLSI Circuits:
Problems and Solutions”, IEEE International Symposium on Quality of
Electronic Design, pp. 173-179, San Jose, USA, 20-22 Mars 2000.
Y. Bonhomme, P. Girard, C. Landrault et S.
Pravossoudovitch, “Power Conscious Testing”, East-West Design and Test
Conference, pp. 29-31, Yalta, Ukraine, 17-21 Septembre 2003.
P. Girard, O. Héron, S. Pravossoudovitch et M.
Renovell, “High Quality TPG for Delay Faults in Look-Up Tables of
FPGAS”, IEEE International Workshop on Electronic Design, Test &
Applications, pp. 83-88, Perth, Australie, 28-30 Janvier 2004.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et M. Bastian Hage-Hassan, “Test Solutions for Dynamic Faults
in SRAM Memories”, MEDEA+ Design Automation Conference, Paris, France,
22-25 Mai 2005.
A. Rousset, P. Girard, S. Pravossoudovitch, C.
Landrault et A. Virazel, “A Unified Framework for Logic Diagnosis”,
IEEE East-West Design and Test Workshop, pp. 47-52, Sochi, Russie,
Septembre 2006.
P. Girard, C. Landrault, S. Pravossoudovitch et
A. Virazel, “Low Power Testing”, Invited Address, IEEE Workshop on RTL
and High Level Testing, pp. 3-4, Fukuoka, Japon, Novembre 2006.
L. Dilillo, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel, M. Bastian et V. Gouin, “Impact of
Technology Scaling on Defects and Parameter Deviations in Embedded
SRAMs”, IEEE VLSI Test Symposium, Innovative Practice Session on
“Testing Embedded Memories”, Santa Clara, USA, Mai 2008.
P. Girard, “Power: The New Dimension of Test”,
Invited Address, IEEE Workshop on RTL and High Level Testing, Sapporo,
Japon, 27 Novembre 2008.
L. Dilillo, P. Rech, J-M. Galliere, P. Girard, F. Wrobel et F. Saigné,
“Neutron Detection in Atmospheric Environment through Static and
Dynamic SRAM-Based Test Bench”, IEEE Latin-American Test Workshop, pp.
266-272, Porto De Galinhas, Brésil, 27-30 Mars 2011.
L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et N.
Badereddine, “Failure Analysis and Test Solutions for Low-Power SRAMs”,
IEEE Asian Test Symposium, Special Session on “Memory BIST Advances for
Nanoscale Technologies”, New Delhi, Inde, 21-23 Novembre 2011.
A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, K. Miyase et X.
Wen, “Power-Aware Test Pattern Generation for At-Speed LOS Testing”,
IEEE Asian Test Symposium, Special Session on “Power-Aware Testing”,
New Delhi, Inde, 21-23 Novembre 2011.
A. Bosio, L. Dilillo, P. Girard, A. Todri et A. Virazel, “An
Introduction to Why and How Controlling Power Consumption During Test”,
IEEE Asian Test Symposium, Special Session on “Power-Aware Testing:
Present and Future”, Niigata, Japon, 19-22 Novembre 2012.
P. Girard, “Test of Low Power Devices: Constraints and Industrial
Practices”, Keynote, IEEE International Conference on Microelectronics,
Casablanca, Maroc, 20-23 December 2015.
P. Girard, “Test of Low Power Memories: Constraints and Industrial
Practices”, Invited Address, IEEE International Workshop on Spintronic
Memory and Logic, Pekin, Chine, 30 Avril - 3 Mai 2016.
P. Girard, A. Bosio et A. Virazel, “Test of Low Power Circuits: Issues
and Industrial Practices”, IEEE International Conference on
Electronics, Circuits and Systems, Special Session “Techniques and
Trends Towards Resilient and Energy Efficient Embedded Electronic
Systems”, Monte Carlo, Monaco, 11-14 Decembre 2016.
A. Bosio, P. Girard et A. Virazel, “Approximate Computing: Design &
Test for Integrated Circuits”, IEEE Latin-American Test Symposium, DOI:
10.1109/LATW.2017.7906737, Bogota, Colombie, 13-15 Mars 2017.
P. Girard, “Testing Approximate Digital Circuits”, Invited Talk, IEEE
Workshop on RTL and High Level Testing, Taipei, Taiwan, 30 Novembre
2017.
P. Girard, “Test and Reliability of MRAM Memories”, Invited Talk, IEEE
International Workshop on Spintronic Memory and Logic, Pekin, Chine,
15-19 Octobre 2018.
P. Girard, “Machine Learning Techniques for Improving Fault Diagnosis
in SoCs”, Invited Talk, 1st International Workshop on AI Chip Design,
Nanjing, Chine, 5 juin 2019
M.L. Flottes, P. Girard, C. Landrault et S.
Pravossoudovitch, “A New Reliable Method for Delay-Fault Diagnosis”,
IEEE International Conference on VLSI design, pp. 12-16 Bangalore,
Inde, 4-7 Janvier 1992.
P. Girard, C. Landrault et S. Pravossoudovitch,
“An Alternative to Fault Simulation for Delay-Fault Diagnosis”, IEEE
European Design Automation Conference, pp. 274-279, Bruxelles,
Belgique, 16-19 Mars 1992.
P. Girard, C. Landrault et S. Pravossoudovitch,
“A Novel Approach to Delay-Fault Diagnosis”, ACM/SIGDA Design
Automation Conference, pp. 357-360, Anaheim, USA, 8-12 Juin 1992.
P. Girard, C. Landrault et S. Pravossoudovitch,
“A Reconvergent Fanout Analysis for the CPT Algorithm Used in
Delay-Fault Diagnosis”, IEEE European Test Conference, pp. 83-88,
Rotterdam, Pays-Bas, 19-24 Avril 1993.
D. Dumas, P. Girard, C. Landrault et S.
Pravossoudovitch, “An Implicit Delay-Fault Simulation Method with
Approximate Detection Threshold Calculation”, IEEE International Test
Conference, pp. 705-713, Baltimore, USA, 17-21 Octobre 1993.
D. Dumas, P. Girard, C. Landrault et S.
Pravossoudovitch, “Effectiveness of a Variable Sampling Time Strategy
for Delay Fault Diagnosis”, IEEE European Design and Test Conference,
pp. 518-523, Paris, France, 28 Février-3 Mars 1994.
P. Girard, C. Landrault, S. Pravossoudovitch et
B. Rodriguez, “A Trace-Based Method for Delay Fault Diagnosis in
Synchronous Sequential Circuits”, IEEE European Design and Test
Conference, pp. 526-532, Paris, France, 20-23 Février 1995.
P. Cavallera, P. Girard, C. Landrault et S.
Pravossoudovitch, “DFSIM: a Gate Delay Fault Simulator for Sequential
Circuits”, IEEE European Design and Test Conference, pp. 79-85, Paris,
France, 11-14 Mars 1996.
P. Girard, C. Landrault, S. Pravossoudovitch et
B. Rodriguez, “A Diagnostic ATPG for Delay Faults Based on Genetic
Algorithms”, IEEE International Test Conference, pp. 286-293,
Washington, USA, 22-24 Octobre 1996.
P. Girard, C. Landrault, S. Pravossoudovitch
et D. Severac, “A Technique to Reduce Power Consumption in CMOS
Circuits”, CPDA Design of Integrated Circuits and Systems Conference,
pp. 697-698, Barcelone, Espagne, 20-22 Novembre 1996.
C. Fagot, P. Girard et C. Landrault, “On Using
Machine Learning for Logic BIST”, IEEE International Test Conference,
pp. 338-346, Washington, USA, 3-5 Novembre 1997.
P. Girard, L. Guiller, C. Landrault, S.
Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira et M. Santos,
“Low Power Pseudo-Random BIST: On Selecting the LFSR Seed”, CPDA Design
of Integrated Circuits and Systems Conference, pp. 166-172, Madrid,
Espagne, 17-20 Novembre 1998.
S. Manich, A. Gabarro, J. Figueras, P. Girard,
L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira et M.
Santos, “Energy and Average Power Consumption Reduction in LFSR Based
BIST Structures”, CPDA Design of Integrated Circuits and Systems
Conference, pp. 651-656, Palma de Mallorce, Espagne, 16-18 Novembre
1999.
P. Girard, L. Guiller, C. Landrault et S.
Pravossoudovitch, “ Low Power BIST Design by Circuit
Partitioning: Methodology and Architecture”, IEEE International
Test Conference, pp. 652-661, Atlantic City, USA, 3-5 Octobre 2000.
R. David, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “RSIC Generation: A Solution for Logic
BIST”, IFIP International Conference on VLSI, pp. 111-117, Montpellier,
France, 3-5 Décembre 2001.
Y. Bonhomme, P. Girard, C. Landrault et S.
Pravossoudovitch, “Power Driven Chaining of Flip-flops in Scan
Architectures”, IEEE International Test Conference, pp. 796-803,
Baltimore, USA, 8-10 Octobre 2002.
Y. Bonhomme, P. Girard, L. Guiller, C.
Landrault et S. Pravossoudovitch, “Efficient Scan Chain Design for
Power Minimization During Scan Testing Under Routing Constraint”, IEEE
International Test Conference, pp. 488-493, Charlotte, USA, 30
Septembre - 2 Octobre 2003.
Y. Bonhomme, P. Girard, L. Guiller, C.
Landrault, S. Pravossoudovitch et A. Virazel, “Design of
Routing-Constrained Low Power Scan Chains”, ACM/IEEE Design, Automation
and Test in Europe, pp. 62-67, Paris, France, 16-20 Février 2004.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et M. Bastian Hage-Hassan, “Resistive-Open Defect Injection in
SRAM Core-cell: Analysis and Comparison between 0.13 μm and 90 nm
Technologies”, ACM/IEEE Design Automation Conference, pp. 857-862,
Anaheim, USA, 13-17 Juin 2005.
N. Badereddine, P. Girard, S.
Pravossoudovitch, A. Virazel et C. Landrault, “Power-Aware Scan Testing
for Peak Power Reduction”, IFIP VLSI-SOC Conference, pp. 441-446,
Perth, Australia, 17-19 Octobre 2005.
L. Dilillo, P. Rosinger, P. Girard et B.M.
Al-Hashimi, “Minimizing Test Power in SRAM through Pre-charge Activity
Reduction”, ACM/IEEE Design, Automation and Test in Europe, pp.
1159-1165, Munich, Allemagne, 6-10 Mars 2006.
N. Badereddine, P. Girard, S.
Pravossoudovitch, C. Landrault, A. Virazel et H.J. Wunderlich,
“Minimizing Peak Power Consumption during Scan Testing: Structural
Technique for Don’t Care Bits Assignment”, IEEE Conference on
Ph.D. Research in Microelectronics and Electronics, pp. 65-68, Otranto,
Italy, 12-15 Juin 2006.
N. Badereddine, P. Girard, S.
Pravossoudovitch, C. Landrault, A. Virazel et H.J. Wunderlich,
“Minimizing Peak Power Consumption during Scan Testing: Test Pattern
Modification with X Filling Heuristics”, IEEE International
Conference on Design & Test of Integrated Systems, pp. 259-264,
Tunis, Tunisie, 5-7 Septembre 2006.
O. Ginez, J.M. Daga, P. Girard, C. Landrault,
S. Pravossoudovitch et A. Virazel, “Embedded Flash Testing: Overview
and Perspectives”, IEEE International Conference on Design & Test
of Integrated Systems, pp. 210-215, Tunis, Tunisie, 5-7 Septembre 2006.
N. Badereddine, P. Girard, S.
Pravossoudovitch, C. Landrault, A. Virazel et H.J. Wunderlich,
“Structural-Based Power-Aware Assignement of Don’t Cares for Peak Power
Reduction during Scan Testing”, IFIP VLSI-SOC Conference, pp. 403-408,
Nice, France, 16-18 Octobre 2006.
A. Ney, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel et M. Bastian, “Slow Write Driver Faults
in 65nm SRAM Technology: Analysis and March Test Solution”, ACM/IEEE
Design, Automation and Test in Europe, pp. 528-533, Nice, France, 16-20
Avril 2007.
X. Wen, K. Miyase, S. Kajihara, T. Suzuki, Y.
Yamato, P. Girard, Y. Oosumi et L.T. Wang, “A Novel Scheme to Reduce
Power Supply Noise for High-Quality At-Speed Scan Testing”, IEEE
International Test Conference, papier 25.1, CDRom Proceedings, Santa
Clara, USA, 23-25 Octobre 2007.
O. Ginez, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Viraze et J.M. Daga, “A Concurrent Approach for
Testing Address Decoder Faults in eFlash Memories”, IEEE International
Test Conference, papier 3.2, CDRom Proceedings, Santa Clara, USA, 23-25
Octobre 2007.
A. Ney, P. Girard, S. Pravossoudovitch, A.
Virazel, M. Bastian et V. Gouin, “A Design-for-Diagnosis Technique for
SRAM Write Drivers”, ACM/IEEE Design, Automation and Test in Europe,
pp. 1480-1485, CDRom Proceedings, Munich, Allemagne, 10-14 Mars 2008.
A. Ney, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch et A. Virazel, “A Signature-based Approach for
Diagnosis of Dynamic Faults in SRAMs”, IEEE International Conference on
Design & Test of Integrated Systems, Touzeur, Tunisie, 25-27 Mars
2008.
A. Ney, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch, A. Virazel et M. Bastian, “A History-Based Diagnosis
Technique for Static and Dynamic Faults in SRAMs”, IEEE International
Test Conference, papier 3.2, CDRom Proceedings, Santa Clara, USA, 28-30
Octobre 2008.
J. Vial, A. Bosio, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “SoC Yield Improvement: Redundant
Architectures to the Rescue?”, IEEE International Test Conference,
papier PO.7, CDRom Proceedings, Santa Clara, USA, 28-30 Octobre 2008.
A. Ney, L. Dilillo, P. Girard, S.
Pravossoudovitch, A. Virazel, M. Bastian et V. Gouin, “A New
Design-for-Test Technique for SRAM Core-Cell Stability Faults”,
ACM/IEEE Design, Automation and Test in Europe, pp. 1344-1349, CDRom
Proceedings, Nice, France, 20-24 Avril 2009.
Y. Benabboud, A. Bosio, P. Girard, S.
Pravossoudovitch et A. Virazel, “A Fault-Simulation-Based Approach for
Logic Diagnosis”, IEEE International Conference on Design & Test of
Integrated Systems, pp. 216-221, Le Caire, Egypte, 6-10 Avril 2009.
J. Vial, A. Virazel, A. Bosio, L. Dilillo, P.
Girard et S. Pravossoudovitch, “Using TMR Architectures for SoC yield
Improvement”, IARIA International Conference on Advances in System
Testing and Validation Lifecycle, Porto, Portugal, 20-25 Septembre 2009.
P.D. Mauroux, A. Virazel, A. Bosio, L.
Dilillo, P. Girard, S. Pravossoudovitch et B. Godard, “NAND Flash
Testing: A Preliminary Study on Actual Defects”, IEEE International
Test Conference, CDRom Proceedings, Austin, USA, 1er November 2009.
R. Alves Fonseca, L. Dilillo, A. Bosio, P.
Girard, S. Pravossoudovitch, A. Virazel et N. Badereddine, “A
Statistical Simulation Method for Reliability Analysis of SRAM
Core-Cells”, IEEE/ACM Design Automation Conference, CDRom, Anaheim,
USA, 13- 18 Juin 2010.
P. Rech, J-M. Galliere, P. Girard, F. Wrobel,
F. Saigné et L. Dilillo, “Impact of Resistive-Open Defects on SRAM
sensitivity to Soft Errors”, 11th European Conference on Radiation
Effects on Components and Systems, Langenfeld, Autriche, 27-29
Septembre 2010.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen et N.
Ahmed, “Is Test Power Reduction Through X-Filling Good Enough?”, IEEE
International Test Conference, CDRom Proceedings, Austin, USA, 1-5
November 2010.
D.-A. Tran, A. Virazel, A. Bosio, L. Dilillo,
P. Girard, S. Pravossoudovitch et H.-J. Wunderlich, “Parity Prediction
Synthesis for Nano-Electronic Gate Designs”, IEEE International Test
Conference, CDRom Proceedings, Austin, USA, 1-5 November 2010.
J-M. Galliere, P. Rech, P. Girard et L.
Dilillo, “A Roaming Memory Test Bench for Detecting Particle-induced
SEUs”, IEEE International Test Conference, CDRom Proceedings, Austin,
USA, 1-5 November 2010.
P.D. Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch, B. Godard, G. Feste et L. Vachez “A DfT Solution for
Oxide Thickness Varitions in ATMEL eFlash Technology”, IEEE
International Conference on Design & Test of Integrated Systems,
CDRom Proceedings, Athènes, Grèce, Avril 2011.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A.
Virazel, M. Tehranipoor, K. Miyase, X. Wen et N. Ahmed, “Power
Reduction Through X-filling of Transition Fault Test Vectors for LOS
Testing”, IEEE International Conference on Design & Test of
Integrated Systems, CDRom Proceedings, Athènes, Grèce, Avril 2011.
P. Rech, J-M. Galliere, P. Girard, F. Wrobel, F. Saigné et L. Dilillo,
“Dynamic-Stress Neutrons Test of Commercial SRAMs”, IEEE Nuclear and
Space Radiation Effects Conference, CDRom Proceedings, Las Vegas, USA,
25-29 Juillet 2011.
A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch et A.
Virazel, “Power Supply Noise and Ground Bounce Aware Pattern Generation
for Delay Testing”, IEEE International NEWCAS Conference, pp. 73-76,
Bordeaux, France, 26-29 June 2011.
P. Rech, J-M. Galliere, P. Girard, A. Griffoni, F. Wrobel, F. Saigné et
L. Dilillo, “Neutron-Induced Multiple Bit Upsets on
Dynamically-Stressed Commercial SRAM Arrays”, 20th European Conference
on Radiation Effects on Components and Systems (RADECS), 19-23
Septembre 2011.
R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Virazel et N. Badereddine, “On Using Address Scrambling to Implement
Defect Tolerance in SRAMs”, IEEE International Test Conference, CDRom
Proceedings, Anaheim, USA, 18-23 September 2011.
J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G.
Prenat et K. McKay, “Analysis of Resistive-Open Defects in TAS-MRAM
Array”, IEEE International Test Conference, CDRom Proceedings, Anaheim,
USA, 18-23 September 2011.
J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G.
Prenat, J. Alvarez-Herault et K. Mackay, “Impact of Resistive-Open
Defects on the Heat Current of TAS-MRAM Architectures”, IEEE/ACM Design
Automation and Test in Europe, Dresde, Allemagne, pp. 532-537, 12-16
Mars 2012.
X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor
et L.T. Wang, “On Pinpoint Capture Power Management in At-Speed Scan
Test Generation”, accepté à IEEE International Test Conference,
Anaheim, USA, 4-9 Novembre 2012.
L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, et N.
Badereddine, “Low-Power SRAMs Power Mode Control Logic: Failure
Analysis and Test Solutions”, accepté à IEEE International Test
Conference, Anaheim, USA, 4-9 Novembre 2012.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel,
F. Wrobel et F. Saigné, “SRAM Core-Cell Sensitivity to Neutron at 40nm
Technology Node”, 21st European Conference on Radiation and
its Effects on Components and Systems (RADECS), Biarritz, France, 24-28
Septembre 2012.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel,
A. D. Touboul, F. Wrobel et F. Saigné, “Neutron impact on a Commercial
4Mb MRAM”, 21st European Conference on Radiation and its
Effects on Components and Systems (RADECS), Biarritz, France, 24-28
Septembre 2012.
C.
Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard, et A. Virazel,
“Resistive-Open Defect Analysis for Through-Silicon-Vias”, 27th
Conference on Design of Circuits and Integrated Systems, Avignon,
France, 28-30 Novembre 2012.
L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, et N.
Badereddine, “Test Solution for Data Retention Faults in Low-Power
SRAMs”, IEEE/ACM Design Automation & Test in Europe (DATE)
Conference, Grenoble, France, 18-22 Mars 2013.
A. Todri, P. Girard, A. Bosio, L. Dilillo, A. Virazel, P. Vivet et M.
Belleville, “Fast and Accurate Electro-Thermal Analysis of
Three-Dimensional Power Delivery Networks”, IEEE International
Conference on Thermal, Mechanical and Multi-Physics Simulation,
Wrocław, Pologne, 15-17 Avril 2013.
E.I. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel,
et N. Badereddine, “Analyzing the Effect of Concurrent Variability in
the Core Cells and Sense Amplifiers on SRAM Read Access Failures”, IEEE
International conference on Design & Technology of Integrated
Systems in nanoscale era (DTIS'13), Abu Dhabi, UAE, 26-28 Mars 2013.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri, A. Virazel, C. Frost, F. Wrobel et F. Saigné, “Temperature
Impact on the Neutron SER of a commercial 90nm SRAM”, IEEE Nuclear and
Space Radiation Effects Conference, CDRom Proceedings, San Francisco,
USA, 8-12 Juillet 2013.
A. Todri, A. Bosio, L. Dilillo, P. Girard et A. Virazel, “Worst-Case
Power Supply Noise and Temperature Distribution Analysis for 3D PDNs
with Multiple Clock Domains”, IEEE International NEWCAS Conference, pp.
1-4, Paris, France, 16-19 Juin 2013.
L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, et N.
Badereddine, “On the Reuse of Read and Write Assist Circuits to Improve
Test Efficiency in Low-Power SRAMs”, IEEE International Test
Conference, Anaheim, USA, 10-12 Septembre 2013.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri, A. Virazel, J. Mekki, M. Brugger, F. Wrobel et F. Saigné,
“SEU Monitoring in Mixed-Field Radiation Environments of Particle
Accelerators”, 22nd European Conference on Radiation and its Effects on
Components and Systems (RADECS), Oxford, Grande Bretagne, 23-27
Septembre 2013.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri, A. Virazel, C. Frost, F. Wrobel et F. Saigné,
“Multiple-Cell-Upsets on a commercial 90nm SRAM in Dynamic Mode”, 22nd
European Conference on Radiation and its Effects on Components and
Systems (RADECS), Oxford, Grande Bretagne, 23-27 Septembre 2013.
J. Azevedo, A. Virazel, Y. Cheng, A. Bosio, L. Dilillo, P. Girard, A.
Todri et J. Alvarez-Herault, “Performance Characterization of TAS-MRAM
Architectures in Presence of Capacitive Defects”, IARIA International
Conference on Advances in System Testing and Validation Lifecycle,
Venise, Italie, 27 Octobre- 1er Novembre 2013.
Y. Cheng, A. Todri, A. Bosio, L. Dilillo, P. Girard et A. Virazel,
“Power Supply Noise-Aware Workload Assignments for Homogenous 3D MPSoCs
with Thermal Consideration”, IEEE Asian and South Pasific Design
Automation Conference, pp.544-549, Singapour, 20-23 Janvier 2014.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri, A. Virazel, V. Gupta, H. Puchner, A. Bosser, J. Arno, A.
Virtanen, L. Dusseau, F. Wrobel et F. Saigné, “Novel Dynamic Test
Methods for COTS SRAMs Under Heavy Ion Irradiation”, IEEE Nuclear and
Space Radiation Effects Conference, CDRom Proceedings, Paris, France,
14-18 Juillet 2014.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri, A. Virazel, P. Cocquerez, J.L. Autran, A. Litterio, F. Wrobel
et F. Saigné, “Real-Time Testing of 90nm COTS SRAMs at Concordia
Station in Antarctica”, IEEE Nuclear and Space Radiation Effects
Conference, CDRom Proceedings, Paris, France, 14-18 Juillet 2014.
A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, et
M. Sonza Reorda, “Exploring the Impact of Functional Test Programs
Re-Used for Power-Aware Testing”, EDAA/IEEE/ACM Design Automation &
Test in Europe (DATE) Conference, CDRom Proceedings, Grenoble, France,
9-13 Mars 2015.
A.
Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi et M. Sonza
Reorda, “An effective ATPG flow for Gate Delay Faults”, IEEE
International conference on Design & Technology of Integrated
Systems in nanoscale era (DTIS), Naples, Italie, 21-23 Avril 2015.
A. Touati,
A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi et M. Sonza
Reorda, “Scan-Chain Intra-Cell Defects Grading”, IEEE International
conference on Design & Technology of Integrated Systems in
nanoscale era (DTIS), Naples, Italie, 21-23 Avril 2015.
I. Wali, A. Virazel, A. Bosio et P. Girard, “An Experimental
Comparative Study of Fault-Tolerant Architectures”, IARIA International
Conference on Advances in System Testing and Validation Lifecycle, pp.
1-6, Barcelone, Espagne, 15-20 Novembre 2015.
A. Nocua, A. Virazel, A. Bosio, P. Girard et C. Chevalier, “An
Efficient Hybrid Power Modeling Approach for Accurate Gate-Level Power
Estimation”, IEEE International Conference on Microelectronics, pp.
17-20, Casablanca, Maroc, 20-23 Decembre 2015.
A. Bosio, P. Debaud, P. Girard, S. Guilhot, M. Valka et A. Virazel,
“Auto-Adaptive Ultra-Low Power IC”, IEEE International conference on
Design & Technology of Integrated Systems in nanoscale era (DTIS),
Istanboul, Turquie, 12-14 Avril 2016.
A. Nocua, A. Virazel, A. Bosio, P. Girard et C. Chevalier, “A
Cross-Level Power Estimation Technique to Improve IP Power Models
Quality”, IFIP/IEEE International Conference on Very Large Scale
Integration, DOI: 10.1109/VLSI-SoC.2016.7753582, Tallin, Estonie, 26-28
Septembre 2016.
G. Harcha, A. Bosio, P. Girard, A. Virazel et P. Bernardi, “An
Effective Fault-Injection Framework for Memory Reliability Enhancement
Perspectives”, IEEE International conference on Design & Technology
of Integrated Systems in nanoscale era (DTIS), Palma de Mallorque, Espagne, 4-6 Avril 2017.
B. Deveautour, A. Virazel, P. Girard, et S. Pravossoudovitch, “Is
Aproximate Computing suitable for Selective Hardening of Arithmetic
Circuits?”, IEEE International conference on Design & Technology of
Integrated Systems in nanoscale era (DTIS), Taormina, Italy, 10-12
Avril 2018.
T.P. Ho, E. Faehn, A. Virazel, A. Bosio et P. Girard, “An Effective
Intra-Cell Diagnosis Flow for Industrial SRAMs”, IEEE International
Test Conference, Pheonix, USA, 30 Octobre-3 Novembre 2018.
B. Deveautour, A. Virazel, A. Bosio et P. Girard, “On Using Approximate
Computing for Error Detection Schemes of Arithmetic Circuits”, IEEE
International Conference on Electronics Circuits and Systems (NEWCAS),
Bordeaux, France, 9-12 Décembre 2018.
A. Aziza, M. Moreau, J.M. Portal, A. Virazel, et P. Girard, “A
Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks”, IEEE
International Conference on Electronics Circuits and Systems (NEWCAS),
Munich, Allemagne, 23-26 Juin 2019.
Aibin Yan, Xiangfeng Feng, Jie Cui, Zhili Chen, P. Girard et Xiaoqing
Wen, “N-1 Faults Interceptive Multiple-Modular-Redundancy Voter Designs
for Safety-Critical Applications”, proposé à EDAA/IEEE/ACM Design
Automation & Test in Europe (DATE) Conference, Grenoble, France,
9-13 Mars 2020.
M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio,
“Achieving Full Gains in Yield for Approximate Circuits: a New Test
Application Technique”, proposé à EDAA/IEEE/ACM Design Automation &
Test in Europe (DATE) Conference, Grenoble, France, 9-13 Mars 2020.
Aibin Yan, Kang Yang, Jie Cui, P. Girard et Xiaoqing Wen, “HITTSFL:
Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and
SET-Filterable Latch for Safety-Critical Applications”, proposé à
ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, USA,
19-23 Juillet 2020.
P. Girard, C. Landrault et S. Pravossoudovitch,
“Delay-Fault Diagnosis Based on Critical Path Tracing from Symbolic
Simulation”, IEEE/ACM International Symposium on Circuits And Systems,
pp. 1133-1136, San Diego, USA, 10-13 Mai 1992.
P. Cavallera, P. Girard, C. Landrault et S.
Pravossoudovitch, “Delay Fault Propagation in Synchronous Sequential
Circuits”, IEEE Asian Test Symposium, pp. 20-25, Nara, Japon, 15-17
Novembre 1994.
P. Girard, C. Landrault, S. Pravossoudovitch et
B. Rodriguez, “Diagnostic of Path and Gate Delay Faults in Non-Scan
Sequential Circuits”, IEEE VLSI Test Symposium, pp. 380-386, Princeton,
USA, 30 Avril- 3 Mai 1995.
S. Cremoux, C. Fagot, P. Girard, C. Landrault
et S. Pravossoudovitch, “A New Test Pattern Generation Method for Delay
Fault Testing”, IEEE VLSI Test Symposium, pp. 296-301, Princeton, USA,
28 Avril- 1 Mai 1996.
P. Girard, C. Landrault, V. Moreda et S.
Pravossoudovitch, “An optimized BIST Test Pattern Generator for Delay
Testing”, IEEE VLSI Test Symposium, pp. 94-100, Monterey, USA, 27-30
Avril 1997.
P. Girard, C. Landrault, S. Pravossoudovitch et
D. Severac, “A Gate Resizing Technique for High Reduction in Power
Consumption”, ACM / SIGDA International Symposium on Low Power
Electronics and Design, pp. 281-286, Monterey, USA, 18-20 Août 1997.
P. Girard, C. Landrault, S. Pravossoudovitch et
D. Severac, “A Technique to Reduce Power Consumption in CMOS Circuits”,
IEE International Symposium on IC Technology, Systems &
Applications, pp. 526-529, Singapour, 10-12 Septembre 1997.
P. Girard, C. Landrault, S. Pravossoudovitch et
D. Severac, “Reducing Power Consumption during Test Application by Test
Vector Ordering”, IEEE International Symposium on Circuits and Systems,
CD-ROM, Monterey, USA, 1-3 Juin 1998.
C. Fagot, O. Gascuel, P. Girard et C.
Landrault, “A Ring Architecture Strategy for BIST Test Pattern
Generation”, IEEE Asian Test Symposium, pp. 418-423, Singapour, 2-4
Décembre 1998.
P. Girard, C. Landrault, V. Moreda, S.
Pravossoudovitch et A. Virazel, “A BIST Structure to Test Delay Faults
in a Scan Environment”, IEEE Asian Test Symposium, pp. 435-439,
Singapour, 2-4 Décembre 1998.
P. Girard, L. Guiller, C. Landrault et S.
Pravossoudovitch, “A Test Vector Ordering Technique for Switching
Activity Reduction during Test Operation”, IEEE Great Lake Symposium on
VLSI, pp. 24-27, Ann Arbor, USA, 4-6 Mars 1999.
P. Girard, L. Guiller, C. Landrault et S.
Pravossoudovitch, “A Test Vector Inhibiting Technique for Low Energy
BIST Design”, IEEE VLSI Test Symposium, pp. 407-412, Dana Point, USA,
26-28 Avril 1999.
P. Girard, L. Guiller, C. Landrault, S.
Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira et M. Santos,
“Low-Energy BIST Design: Impact of the LFSR TPG Parameters on the
Weighted Switching Activity”, IEEE International Symposium on Circuits
and Systems, CD-ROM, Orlando, USA, 31 Mai -2 Juin 1999.
P. Girard, L. Guiller, C. Landrault et S.
Pravossoudovitch, “Circuit Partitioning for Low Power BIST Design
with Minimized Peak Power Consumption”, IEEE Asian Test Symposium, pp.
89-94, Shanghai, Chine, 16-18 Novembre 1999.
L. Bréhelin, O. Gascuel, G. Caraux, P. Girard
et C. Landrault, “Hidden Markov and Independence Models with Patterns
for Sequential BIST”, IEEE VLSI Test Symposium, pp. 359-367, Montreal,
Canada, 30 Avril-4 Mai 2000.
P. Girard, L. Guiller, C. Landrault et S.
Pravossoudovitch, “An Adjacency-Based Test Pattern Generator for Low
Power BIST Design”, IEEE Asian Test Symposium, pp. 459-464, Taipei,
Taiwan, 4-6 Décembre 2000.
P. Girard, L. Guiller, C. Landrault, S.
Pravossoudovitch et H.J. Wunderlich, “A Modified Clock Scheme for a Low
Power BIST Test Pattern Generator”, IEEE VLSI Test Symposium, pp.
306-311, Los Angeles, USA, 29 Avril-3 Mai 2001.
Y. Bonhomme, P. Girard, L. Guiller, C.
Landrault et S. Pravossoudovitch, “A Gated Clock Scheme for Low Power
Scan Testing of Logic ICs or Embedded Cores”, IEEE Asian Test
Symposium, pp. 253-258, Kyoto, Japon, 19-21 Novembre 2001.
C. Fagot, O. Gascuel, P. Girard et C.
Landrault, “A Ring Architecture Strategy for BIST Test Pattern
Generation”, 10th Anniversary Compendium of Selected Papers From IEEE
Asian Test Symposium (1992-2001), pp. 269-274 (Originally Published in
Proceedings of ATS'1998).
P. Girard, L. Guiller, C. Landrault et S.
Pravossoudovitch, “Circuit Partitioning for Low Power BIST Design
with Minimized Peak Power Consumption”, 10th Anniversary Compendium of
Selected Papers From IEEE Asian Test Symposium (1992-2001), pp. 296-301
(Originally Published in Proceedings of ATS'1999).
R. David, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “On Using Efficient Test Sequences for
BIST”, IEEE VLSI Test Symposium, pp. 145-150, Monterey, USA, 28 Avril-2
Mai 2002.
P. Girard, O. Héron, S. Pravossoudovitch et M.
Renovell, “Defect Analysis for Delay-Fault BIST in FPGAs”, IEEE
International On-Line Testing Symposium, pp. 124-128, Kos, Grèce, 7-9
Juillet 2003.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et S. Borri, “Comparison of Open and Resistive-Open Defect Test
Conditions in SRAM Address Decoders”, IEEE Asian Test Symposium, pp.
250-255, Xian, Chine, 16-19 Novembre 2003.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et S. Borri, “March iC-: An Improved Version of March C- for
ADOFs Detection”, IEEE VLSI Test Symposium, pp. 129-134, Napa, USA,
25-29 Avril 2004.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel, S. Borri et M. Hage-Hassan, “Dynamic Read Destructive Faults
in Embedded SRAMs: Analysis and March Test Solution”, IEEE European
Test Symposium, pp. 140-145, Ajaccio, France, pp. 140-145, 24-26 Mai
2004.
Y. Bonhomme, T. Yoneda, H. Fujiwara et P.
Girard, “An Efficient Scan Tree Design for Test Time Reduction”, IEEE
European Test Symposium, pp. 174-179, Ajaccio, France, 24-26 Mai 2004.
P. Girard, O. Héron, S. Pravossoudovitch et M.
Renovell, “Manufacturing-Oriented Testing of Delay Faults in the Logic
Architecture of Symmetrical FPGAs”, IEEE European Test Symposium, pp.
52-57, Ajaccio, France, 24-26 Mai 2004.
P. Girard, O. Héron, S. Pravossoudovitch et M.
Renovell, “BIST of Delay Faults in the Logic Architecture of
Symmetrical FPGAs”, IEEE International On-Line Testing Symposium, pp.
187-192, Madeire, Portugal, 12-14 Juillet 2004.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et S. Borri, “Resistive-Open Defects in Embedded-SRAM Core
Cells: Analysis and March Test Solution”, IEEE Asian Test Symposium,
pp. 266-271, Kenting, Taiwan, 15-17 Novembre 2004.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et M. Bastian Hage-Hassan, “Data Retention Fault in SRAM
Memories: Analysis and Detection Procedures”, IEEE VLSI Test
Symposium, pp. 183-188, Palm Springs, USA, 1-5 Mai 2005.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et M. Bastian Hage-Hassan, “Resistive-Open Defect Influence in
SRAM Pre-charge Circuits: Analysis and Characterization”, IEEE European
Test Symposium, pp. 116-121, Tallinn, Estonie, 22-25 Mai 2005.
O. Ginez, J.M. Daga, M. Comte, P. Girard, C.
Landrault, S. Pravossoudovitch et A. Virazel, “An Overview of Failures
Mechanisms in Embedded Flash Memories”, IEEE VLSI Test Symposium, pp.
108-113, Berkeley, USA, 30 Avril-4 Mai 2006.
N. Badereddine, Z. Wang, P. Girard, K.
Chakrabarty, A. Virazel S. Pravossoudovitch et C. Landrault,
“Power-Aware Test Data Compression for Embedded IP Cores”, IEEE Asian
Test Symposium, pp. 5-10, Fukuoka, Japon, 20-23 Novembre 2006.
O. Ginez, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel et J.M. Daga, “Retention and Reliability
Problems in Embedded Flash Memories: Analysis and Test of Defective
2T-FLOTOX Tunnel Window”, IEEE VLSI Test Symposium, pp. 47-52,
Berkeley, USA, 6-10 Mai 2007.
A. Ney, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel et M. Bastian, “Un-Restored Destructive
Write Faults due to Resistive-Open Defects in the Write Driver of
SRAMs”, IEEE VLSI Test Symposium, pp. 361-366, Berkeley, USA, 6-10 Mai
2007.
O. Ginez, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel et J.M. Daga, “Electrical Simulation Model
of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior
Prediction in eFlash Memories”, IEEE European Test Symposium, pp.
77-82, Freiburg, Allemagne, 20-24 Mai 2007.
A. Ney, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel et M. Bastian, “Dynamic Two-Cell Incorrect
Read Fault due to Resistive-Open Defects in the Sense Amplifiers of
SRAMs”, IEEE European Test Symposium, pp. 97-102, Freiburg, Allemagne,
20-24 Mai 2007.
A. Rousset, A. Bosio, P. Girard, C. Landrault,
S. Pravossoudovitch et A. Virazel, “DERRIC: a Tool for Unified Logic
Diagnosis”, IEEE European Test Symposium, pp. 13-18, Freiburg,
Allemagne, 20-24 Mai 2007.
M. Bastian, V. Gouin, P. Girard, C. Landrault,
A. Ney, S. Pravossoudovitch et A. Virazel, “Influence of Threshold
Voltage Deviations on 90nm SRAM Core-Cell Behavior”, IEEE Asian Test
Symposium, Pekin, Chine, pp. 501-504, 9-11 Octobre 2007.
A. Rousset, A. Bosio, P. Girard, C. Landrault,
S. Pravossoudovitch et A. Virazel, “Fast Bridging Fault Diagnosis Using
Logic Information”, IEEE Asian Test Symposium, Pekin, Chine, pp. 33-38,
9-11 Octobre 2007.
A. Ney, P. Girard, S. Pravossoudovitch, A.
Virazel, M. Bastian et V. Gouin, “An SRAM Design-for-Diagnosis Solution
based on Write Driver Voltage Sensing”, IEEE VLSI Test Symposium, pp.
89-94, San Diego, USA, 4-8 Mai 2008.
A. Rousset, A. Bosio, P. Girard, C. Landrault,
S. Pravossoudovitch et A. Virazel, “Improving Diagnosis Resolution
Without Physical Information”, IEEE International Symposium on
Electronic Design, Test & Applications, pp. 210-215, Hong Kong,
Chine, 23-25 Janvier 2008.
J. Vial, A. Bosio, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “Fault-Tolerance Architecture: The
Challenge for Yield Improvement”, IEEE International On-Line Testing
Symposium, pp. 165-166, Crête, Grece, 7-9 Juillet 2008.
J. Vial, A. Bosio, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “Using TMR Architectures for Yield
Improvement”, IEEE International Symposium on Defect and Fault
Tolerance in VLSI Systems, pp. 7-15, Cambridge, USA, 1-3 Octobre, 2008.
H. Furukawa, X. Wen, K. Miyase, Y. Yamato, S.
Kajihara, P. Girard, L.T. Wang, et M. Tehranipoor, “CTX: A
Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing
Yield Loss Risk in At-Speed Scan Testing”, IEEE Asian Test Symposium,
pp. 297-402, Saporo, Japon, 24-27 Novembre 2008.
Y. Benabboud, A. Bosio, P. Girard, S.
Pravossoudovitch, L. Bouzaida et I. Izaute, “A Case Study on Logic
Diagnosis for System-on-Chip”, IEEE International Symposium on Quality
of Electronic Design, pp. 253-260, San Jose, USA, 2009.
Y. Benabboud, A. Bosio, L. Dilillo, P. Girard,
S. Pravossoudovitch, A. Virazel, L. Bouzaida et I. Izaute,
“Comprehensive Bridging Fault Diagnosis based on the SLAT Paradigm”,
IEEE Symposium on Design and Diagnostics of Electronic Circuits and
Systems, pp. 1-6, Liberec, République Tcheque, Avril 2009.
A. Bosio, P. Bernardi, P. Girard, S.
Pravossoudovitch et M. Sonza Reorda, “An Efficient Fault Simulation
Technique for Transition Faults in Non-Scan Sequential Circuits”, IEEE
Symposium on Design and Diagnostics of Electronic Circuits and Systems,
pp. 7-12, Liberec, République Tcheque, Avril 2009.
Y. Benabboud, A. Bosio, L. Dilillo, P. Girard,
S. Pravossoudovitch, A. Virazel et O. Riewer, “Delay Fault Diagnosis in
Sequential Circuits”, IEEE Asian Test Symposium, Taichung, Taiwan, pp.
355-360, 23-26 Novembre 2009.
P. Bernardi, A. Bosio, P. Girard, S.
Pravossoudovitch et M. Sonza Reorda, “An Exact and Efficient Critical
Path Tracing Algorithm”, IEEE International Symposium on Electronic
Design, Test & Applications, pp. 164-170, Ho Chi Minh City,
Vietnam, 13-15 Janvier 2010.
R. Alves Fonseca, L. Dilillo, A. Bosio, P.
Girard, S. Pravossoudovitch, A. Virazel et N. Badereddine, “Impact of
Resistive-Bridging Defects in SRAM Core-Cell”, IEEE International
Symposium on Electronic Design, Test & Applications, pp. 265-270,
Ho Chi Minh City, Vietnam, 13-15 Janvier 2010.
R. Alves Fonseca, L. Dilillo, A. Bosio, P.
Girard, S. Pravossoudovitch, A. Virazel et N. Badereddine, “Detecting
NBTI Induced Failures in SRAM Core-Cells”, IEEE VLSI Test Symposium,
papier 2B.3, CDRom proceedings, Santa Cruz, USA, 18-21 Avril 2010.
P.D. Mauroux, A. Virazel, A. Bosio, L.
Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes et L.
Vachez, “A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Technology
for Defect Injection and Faulty Behavior Prediction”, IEEE European
Test Symposium, pp. 81-86, Prague, République Tchèque, 24-28 Mai 2010.
R. Alves Fonseca, L. Dilillo, A. Bosio, P.
Girard, S. Pravossoudovitch, A. Virazel et N. Badereddine, “Setting
Test Conditions for Improving SRAM Reliability”, IEEE European Test
Symposium, pp. 257-258, Prague, République Tchèque, 24-28 Mai 2010.
R. Alves Fonseca, L. Dilillo, A. Bosio, P.
Girard, S. Pravossoudovitch, A. Virazel et N. Badereddine, “Analysis of
Resistive-Bridging Defects in SRAM Core-Cells: A Comparative Study from
90nm down to 40 nm Technology Nodes”, IEEE European Test Symposium, pp.
132-137, Prague, République Tchèque, 24-28 Mai 2010.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao et X. Wen,
“Analysis of Power Consumption and Transition Fault Coverage for LOS
and LOC Testing Schemes”, IEEE Symposium on Design and Diagnostics of
Electronic Circuits and Systems, pp. 376-381, Vienne, Autriche, 14-16
Avril 2010.
J. Ma, J. Lee, N. Ahmed, P. Girard et M.
Tehranipoor, “Pattern Grading for Testing Critical Paths Considering
Power Supply Noise and Crosstalk Using a Layout-Aware Quality Metric”,
IEEE Great Lake Symposium on VLSI, pp. 127-130, Providence, USA, 16-18
Mai 2010.
P. Rech, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Virazel et L. Dilillo, “A Memory Fault Simulator
for Radiation-Induced Effects in SRAMs”, IEEE Asian Test Symposium, pp.
100-105, Shanghai, Chine, 1-4 Decembre 2010.
Y. Benabboud, A. Bosio, L. Dilillo, P. Girard,
S. Pravossoudovitch, A. Virazel et O. Riewer, “A Comprehensive
System-on-Chip Logic Diagnosis Approach”, IEEE Asian Test Symposium,
pp. 237-242, Shanghai, Chine, 1-4 Decembre 2010.
X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P.
Girard, et M. Tehranipoor, “Power-Aware Test Generation with Guaranteed
Launch Safety for At-Speed Scan Testing”, IEEE VLSI Test Symposium, pp.
166-171, Dana Point, USA, 2-4 Mai 2011.
M. Valka, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel, E. Sanchez et M. Sonza Reorda, “A Functional Power Evaluation
Flow for Defining Test Power Limits During At-Speed Delay Testing”,
IEEE European Test Symposium, Trondheim, pp. 153-158, Norvège, 23-27
Mai 2011.
L.B. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et N. Badereddine, “Optimized March Test Flow for Detecting
Memory Faults in SRAM Devices Under Bit Line Coupling”, IEEE Symposium
on Design and Diagnostics of Electronic Circuits and Systems, pp.
353-358, Cottbus, Allemagne, 13-15 Avril 2011.
P.D. Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch, B. Godard, G. Festes et L. Vachez, “On Using a
SPICE-like TSTAC eFlash Model for Design and Test”, IEEE Symposium on
Design and Diagnostics of Electronic Circuits and Systems, pp. 359-364,
Cottbus, Allemagne, 13-15 Avril 2011.
A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch et A.
Virazel, “A Study of Path Delay Variations in the Presence of
Uncorellated Power and Ground Supply Noise”, IEEE Symposium on Design
and Diagnostics of Electronic Circuits and Systems, pp. 189-194,
Cottbus, Allemagne, 13-15 Avril 2011.
P. Bernardi, M. Sonza Reorda, A. Bosio, P. Girard et S.
Pravossoudovitch, “On the Modeling of Gate Delay Faults by means of
Transition Delay Faults”, IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems, pp. 226-232,
Vancouver, Canada,
3-5 Octobre 2011.
L. Dilillo, A. Bosio, M. Valka, P. Girard, S. Pravossoudovitch et A.
Virazel, “Error Resilient Infrastructure for Data Transfer in a
Distributed Neutron Detector”, IEEE International Symposium on Defect
and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 294-301,
Vancouver,
Canada, 3-5 Octobre 2011.
D.-A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch et H.-J. Wunderlich, “A Hybrid Fault Tolerant
Architecture for Robustness Improvement of Digital Circuits Parity
Prediction Synthesis for Nano-Electronic Gate Designs”, IEEE Asian Test
Symposium, pp. 136-141, New Delhi, Inde, 21-23 Novembre 2011.
K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara,
F. Wu, L. Dilillo, A. Bosio, P. Girard, et A. Virazel, “Effective
Launch-to-Capture Power Reduction for LOS Scheme with
Adjacent-Probability-Based X-Filling”, IEEE Asian Test Symposium, pp.
90-95, New
Delhi, Inde, 21-23 Novembre 2011.
N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, A. Virazel S.
Pravossoudovitch et C. Landrault, “Power-Aware Test Data Compression
for Embedded IP Cores”, 20th Anniversary Compendium of Selected Papers
From IEEE Asian Test Symposium (2002-2011), pp. 179-184 (Originally
Published in Proceedings of ATS'2006).
D.A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, M.
Imhof et H.J. Wunderlich, “A Pseudo-Dynamic Comparator for Error
Detection in Fault Tolerant Architectures”, IEEE VLSI Test Symposium,
pp. 50-55, Hawai, USA, 23-25 Avril 2012.
L. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Todri, A. Virazel, et N. Badereddine, “Defect Analysis in Power Mode
Control Logic of Low-Power SRAMs”, IEEE European Test Symposium, CDRom
Proceedings, Annecy, France, 28-31 Mai 2012.
C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard, et A. Virazel,
“Resistive-Open Defect Analysis for Through-Silicon-Vias”, IEEE
European Test Symposium, CDRom Proceedings, Annecy, France, 28-31 Mai
2012.
J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G.
Prenat, J. Alvarez-Herault, et K. Mackay, “Coupling-Based
Resistive-Open Defects in TAS-MRAM Architectures”, IEEE European Test
Symposium, CDRom Proceedings, Annecy, France, 28-31 Mai 2012.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel,
A. Touboul, F. Wrobel et F. Saigné, “Evaluation of Test Algorithms
Stress Effect on SRAMs under Neutron Radiation”, IEEE International
On-Line Testing Symposium, CDRom Proceedings, Sitges, Espagne, 27-29
Juin 2012.
Z. Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et E.
Auvray, “Fault Localization Improvement through an Intra-Cell Diagnosis
Approach”, 38th International Symposium for Testing and
Failure Analysis, Phoenix, USA, 15-11 Novembre 2012.
J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G.
Prenat, J. Alvarez-Herault et K. Mackay, “Impact of Resistive-Bridge
Defects in TAS-MRAM Architectures”, IEEE Asian Test Symposium, pp.
125-130, Niigata, Japon, 19-22 Novembre 2012.
M. Valka, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, P.
Debaud et S. Guilhot, “Power Supply Noise Sensor based on Timing
Uncertainty Measurements”, IEEE Asian Test Symposium, pp. 161-166,
Niigata, Japon, 19-22 Novembre 2012.
P. Bernardi, M. De Carvalho, E. Sanchez, M. Sonza Reorda, A. Bosio, L.
Dilillo, P. Girard et M. Valka, “Peak Power Estimation: a Case Study on
CPU Cores”, IEEE Asian Test Symposium, pp. 167-172, Niigata, Japon,
19-22 Novembre 2012.
Z. Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et E.
Auvray, “Effect-Cause Intra-Cell Diagnosis at Transistor Level”, IEEE
International Symposium on Quality Electronic Design, pp. 476-483,
Santa Clara, USA, 4-6 Mars 2013.
L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et N.
Badereddine, “A Built-in Scheme for Testing and Repairing Voltage
Regulators of Low-Power SRAMs”, IEEE VLSI Test Symposium, pp. 1-6,
Berkeley, USA, 29 Avril - 2 Mai 2013.
C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P.
Vivet et M. Belleville, “Computing Detection Probability of Delay
Defects in Signal Line TSVs”, IEEE European Test Symposium, CDRom
Proceedings, Avignon, France, 28-30 Mai 2013.
I. Vatajelu, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et
N. Badereddine, “Analyzing SRAM Resistive-Open Defects Under the Effect
of Process Variability”, IEEE European Test Symposium, CDRom
Proceedings, Avignon, France, 28-30 Mai 2013.
Y. Cheng, A. Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P.
Vivet et M. Belleville, “Mitigate TSV Electromigration for 3D ICs -
From the Architecture Perspective”, IEEE International Symposium on
VLSI, pp. 121-126, Natal, Brésil, 5-7 Août 2013.
G. Tsiligiannis, E.I. Vatajelu, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Todri, A. Virazel, F. Wrobel et F. Saigné, “SRAM
SER Evaluation Under Atmospheric Neutron Radiation and PVT variations”,
IEEE International On-Line Testing Symposium, pp. 145-150, Chania,
Grèce, 8-10 Juillet 2013.
E.I. Vatajelu, G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Todri, A. Virazel, F. Wrobel et F. Saigné,
“Investigating the Correlation of a 40nm SRAM’s Static Noise Margin and
its Soft Error Rate”, IEEE International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems, New York, USA, 2-4
Octobre 2013.
E.I. Vatajelu, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel et
N. Badereddine, “Adaptive Source Bias for Improved Resistive-Open
Defect Coverage during SRAM Testing”, IEEE Asian Test Symposium, pp.
109-114, Yilan, Taiwan, 18-22 Novembre 2013.
A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor et
L.T. Wang, “On Achieving Capture Power Safety in At-Speed Scan-Based
Logic BIST”, IEEE Asian Test Symposium, pp. 19-24, Yilan, Taiwan, 18-22
Novembre 2013.
C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard et A. Virazel,
“TSV Aware Timing Analysis in Paths with Multiple TSVs”, IEEE VLSI Test
Symposium, Napa, USA, 13-17 Avril 2014.
M. Valka, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, P.
Debaud et S. Guilhot, “iBoX – Jitter based Power Supply Noise sensor”,
IEEE European Test Symposium, pp. 1-2, Paderborn, Allemagne, 26-30 Mai
2014.
M. Valka, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, P.
Debaud et S. Guilhot, “Test and Diagnosis of Power Switches”, IEEE
Symposium on Design and Diagnostics of Electronic Circuits and Systems,
pp. 213-218, Varsovie, Pologne, 23-25 Avril 2014.
A. Asokan, A. Todri, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch et A. Virazel, “Path Delay Test in the Presence of
Multi-Aggressor Crosstalk, Power Supply Noise and Ground Bounce Test
and Diagnosis of Power Switches”, IEEE Symposium on Design and
Diagnostics of Electronic Circuits and Systems, pp. 207-212, Varsovie,
Pologne, 23-25 Avril 2014.
C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard et A. Virazel,
“Timing-aware ATPG for Critical Paths with Multiple TSVs”, IEEE
Symposium on Design and Diagnostics of Electronic Circuits and Systems,
pp. 116-121, Varsovie, Pologne, 23-25 Avril 2014.
I. Wali, A. Virazel, A. Bosio, L. Dilillo, P. Girard et A. Todri,
“Protecting Combinational Logic in Pipelined Processor Cores Against
Transient and Permanent Faults”, IEEE Symposium on Design and
Diagnostics of Electronic Circuits and Systems, pp. 223-225, Varsovie,
Pologne, 23-25 Avril 2014.
S. Bernabovi, P. Bernardi, A. Bosio, L. Dilillo, P. Girard, A. Todri et
A. Virazel, “An Intra-Cell Defect Grading Tool”, IEEE Symposium on
Design and Diagnostics of Electronic Circuits and Systems, pp. 298-301,
Varsovie, Pologne, 23-25 Avril 2014.
A. Asokan, A. Todri, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch et A. Virazel, “A Delay Probability Metric for Input
Pattern Ranking Under Process Variation and Supply Noise”, IEEE
Computer Society Annual Symposium on VLSI, pp. 226-231, Tampa, Floride,
USA, 9-11 Juillet 2014.
Z. Sun, A. Bosio, L. Dilillo, P. Girard, A. Virazel et E. Auvray, “On
the Generation of Diagnostic Test Set for Intra-Cell Defects”, IEEE
Asian Test Symposium, pp. 312-317, Hangzhou, Chine, 16-19 Novembre 2014.
S.
Clerc, F. Abouzeid, D. Adil Patel, J.M. Daveau, C. Bottoni, L.
Ciampolini, F. Giner, D. Meyer, R. Wilson, P. Roche, S. Naudet, A.
Virazel et P. Girard, “Design and Performance Parameters of an
Ultra-Low Voltage, Single Supply 32bit Processor implemented in 28nm
FDSOI Technology”, IEEE International Symposium on Quality Electronic
Design, pp. 366-370, Santa Clara, USA, 2-4 Mars 2015.
I.
Wali, A. Virazel, A. Bosio, L. Dilillo et P. Girard, “An Effective
Hybrid Fault-Tolerant Architecture for Pipeline Cores”, IEEE European
Test Symposium, Cluj-Napoca, Roumanie, 25-29 Mai 2015. DOI:
10.1109/ETS.2015.7138733.
M. Valka, A.
Bosio, L. Dilillo, P. Girard, A. Virazel, P. Debaud et S. Guilhot,
“Design-for-Diagnosis Architecture of Power Switches”, IEEE Symposium
on Design and Diagnostics of Electronic Circuits and Systems, pp.
43-48, Belgrade, Serbie, 22-24 Avril 2015.
A.
Asokan, A. Bosio, A. Virazel, L. Dilillo, P. Girard et S.
Pravossoudovitch, “An ATPG Flow to Generate Crosstalk-Aware Path Delay
Pattern”, IEEE Computer Society Annual Symposium on VLSI, pp. 515-520,
Montpellier, France, 8-10 Juillet 2015.
I. Wali, A. Virazel, A. Bosio, L. Dilillo, P. Girard et M. Sonza
Reorda, “Design Space Exploration and Optimization of a Hybrid
Fault-Tolerant Architecture”, IEEE International On-Line Testing
Symposium, pp. 89-94, Halkidiki, Grèce, 6-8 Juillet 2015.
A. Bosio, L. Dilillo, P. Girard, A. Virazel et L. Zordan, “An Effective
BIST Architecture for Power-Gating Mechanisms in Low-Power SRAMs”, IEEE
International Symposium on Quality Electronic Design, Santa Clara, USA,
14-16 Mars 2016.
A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi et M. Sonza
Reorda, “An Effective Approach for Functional Test Programs
Compaction”, IEEE Symposium on Design and Diagnostics of Electronic
Circuits and Systems, Košice, Slovaquie, 20-22 Avril 2016. DOI:
10.1109/DDECS.2016.7482466.
A. Nocua, A. Virazel, A. Bosio, P. Girard et C. Chevalier, “A Hybrid
Power Modeling Approach to Enhance High-Level Power Models”, IEEE
Symposium on Design and Diagnostics of Electronic Circuits and Systems,
Košice, Slovaquie, 20-22 Avril 2016. DOI: 10.1109/DDECS.2016.7482453.
I. Wali, B. Deveautour, A. Virazel, A. Bosio, P. Girard et M. Sonza
Reorda, “A Low-cost Selective Hybrid Fault Tolerant Architecture”, IEEE
European Test Symposium, Amsterdam, Pays-Bas, 24-27 Mai 2016. DOI:
10.1109/ETS.2016.7519296.
A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi et M. Sonza
Reorda, “Improving the Functional Test Delay Fault Coverage: A
Microprocessor Case Study”, IEEE Computer Society Annual Symposium on
VLSI, Pittsburgh, USA, 11-13 Juillet 2016. DOI: 10.1109/ISVLSI.2016.42.
I. Wali, M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio,
“Towards Approximation during Test of Integrated Circuits”, IEEE
Symposium on Design and Diagnostics of Electronic Circuits and Systems,
DOI: 10.1109/DDECS.2017.7934574, Dresde, Allemagne, 19-21 Avril 2017.
M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Towards
Digital Circuit Approximation by exploiting Fault Simulation”, IEEE
East-West Design & Test Symposium, Novi Sad, Serbie, 29 Sept.-2
Oct., 2017.
.P. Ho, E. Faehn, A. Virazel, A. Bosio, P. Girard et P. Loth, “ An
Advanced Diagnosis Flow for Embedded SRAMs”, 43th International
Symposium for Testing and Failure Analysis, Pasadena, USA, 5-9 Novembre
2017.
M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Testing
Approximate Digital Circuits: Challenges and Opportunities”, IEEE
Latin-American Test Symposium, Sao Paulo, Brésil, 12-16 Mars 2018.
M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio,
“On the Comparison of Different ATPG approaches for Approximate
Integrated Circuits”, proposé à IEEE Symposium on Design and
Diagnostics of Electronic Circuits and Systems, Hongrie, Allemagne,
25-27 Avril 2018.
M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio,
“Mean-Error Metrics Aware Testing of Approximate Integrated Circuits:
Challenges and Opportunities”, IEEE International Symposium on Defect
and Fault Tolerance in VLSI and Nanotechnology Systems, Chicago, USA, 8
– 10 Octobre 2018.
S. Mhamdi, A. Virazel, P. Girard, A. Bosio, E. Auvray, E. Fhaen and A.
Ladhar, “Towards Improvement of Mission Mode Failure Diagnosis for
System-on-Chip”, IEEE International On-Line Testing Symposium, Rhodes,
Grèce, 2 – 4 Juillet 2019.
A. Yan, Z. Wu, L. Lu, Z. Chen, J. Song, P. Girard et X. Wen, “Novel
Radiation Hardened Latch Design with Cost-Effectiveness for
Safety-Critical Terrestrial Applications”, IEEE Asian Test Symposium,
Calcutta, Inde, 10-13 Décembre 2019.
A. Yan, Z. Wu, J. Zhou, Y. Hu, Y. Chen, X. Wen et P. Girard, “Design of
a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for
Highly Reliable Terrestrial Applications”, IEEE Asian Test Symposium,
Calcutta, Inde, 10-13 Décembre 2019.
A. Yan, Y. Ling, Z. Xu, J. Cui, K. Yang, P. Girard et X. Wen,
“Dual-Interlocked-Storage-Cells-Based Double-Node-Upset
Self-Recoverable Flip-Flop Design for Aerospace Applications”, proposé
à IEEE VLSI Test Symposium, San Diego, USA, 5-8 Avril 2020.
J. Chen, K. Liu, X. Guo, P. Girard, et Y. Cheng, “A Dynamic Overwriting
Voltage Adjustment for STT-RAM L1 Cache”, propose à IEEE International
Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, 25-26
Mars 2020.
P. Girard, C. Landrault et S. Pravossoudovitch,
“Delay-Fault Diagnosis Based on Critical Path Tracing”, IEEE European
Workshop on Design For Testability, Bruges, Belgique, 2-4 juin 1992.
P. Girard, C. Landrault, S. Pravossoudovitch et
B. Rodriguez, “Diagnostic of Delay Faults in Non-Scan Sequential
Circuits”, North Atlantic Test Workshop - European part, pp. 58-62,
Cargese, Corse, France, 7-8 Juillet 1995.
P. Girard, C. Landrault, S. Pravossoudovitch et
B. Rodriguez, “Diagnostic Test Pattern Generation for Delay Faults
Using Genetic Algorithms”, IEEE European Test Workshop, pp. 249-253,
Montpellier, France, 12-14 Juin 1996.
P. Girard, C. Landrault, V. Moreda et S.
Pravossoudovitch “BIST and “Scan BIST” Structures for Delay Faults”,
IEEE European Test Workshop, pp. 110-111, Cagliari, Italie, 28-30 Mai
1997.
C. Fagot, P. Girard et C. Landrault, “A Novel
Approach for Logic BIST Based on Machine Learning”, IEEE International
On-Line Testing Workshop, pp. 170-174, Crète, Grèce, 7-9 Juillet 1997.
P. Girard, C. Landrault, V. Moreda, S.
Pravossoudovitch et A. Virazel, “A New Scan-BIST Structure to Test
Delay Faults in Sequential Circuits”, IEEE European Test Workshop, pp.
44-48, Sitges, Espagne, 27-29 Mai 1998.
S. Manich, A. Gabarro, J. Figueras, P. Girard,
L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira et M.
Santos, “Low Power BIST by Filtering Non-Detecting Vectors”, IEEE
European Test Workshop, pp. 165-170, Constance, Allemagne, 25-28 Mai
1999.
C. Fagot, O. Gascuel, P. Girard et C.
Landrault, “On Calculating Efficient LFSR Seeds for Built-In Self
Test”, IEEE European Test Workshop, pp. 7-14, Constance, Allemagne,
25-28 Mai 1999.
A. Virazel, R. David, P. Girard, C. Landrault
et S. Pravossoudovitch, “Delay Fault Testing: Choosing Between Random
SIC and Random MIC Test Sequences”, IEEE European Test Workshop, pp.
9-14, Carcais, Portugal, 23-26 Mai 2000.
A. Virazel, R. David, P. Girard, C. Landrault
et S. Pravossoudovitch, “Comparison Between Random and Pseudo-Random
Generation for BIST of Delay and Bridging Faults”, IEEE International
On-Line Testing Workshop, pp. 121-126, Mallorca, Espagne, 3-5 Juillet
2000.
R. David, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel,, “On Hardware Generation of Random
Single Input Change Test Sequences”, IEEE European Test Workshop, pp.
299-305, Stockholm, Suède, 30 Mai-1 Juin 2001.
Y. Bonhomme, P. Girard, L. Guiller, C.
Landrault et S. Pravossoudovitch, “A Gated Clock Scheme for Low Power
Scan-Based BIST”, IEEE International On-Line Testing Workshop, pp.
87-89, Taormina, Italie, 9-11 Juillet 2001.
Y. Bonhomme, P. Girard, C. Landrault et S.
Pravossoudovitch, “Efficient Scan Design for Low Power Test”, SAME:
Sophia Antipolis forum on Microelectronics, pp. 58-61, Sophia
Antipolis, France, 14-15 Novembre 2001.
Y. Bonhomme, P. Girard, C. Landrault et S.
Pravossoudovitch, “Test Power: A Big Issue in Large SOC Designs”, IEEE
International Workshop on Electronic Design, Test & Applications,
pp. 447-449, Christchurch, Nouvelle-Zélande, 29-31 Janvier 2002.
Y. Bonhomme, P. Girard, C. Landrault et S.
Pravossoudovitch,, “Scan Cell Ordering for Low Power Scan Testing”,
IEEE European Test Workshop, Informal Digest, pp. 405-410, Corfu,
Grèce, 26-29 Mai 2002.
P. Girard, O. Héron, S. Pravossoudovitch et M.
Renovell, “Timing Defect Analysis in Look-Up Tables of SRAM-Based
FPGAS”, IEEE Latin American Test Workshop, pp. 26-31, Natal, Brésil,
16-19 Février 2003.
Y. Bonhomme, P. Girard, L. Guiller, C.
Landrault et S. Pravossoudovitch, “Efficient Scan Chain Design for
Power Minimization During Scan Testing Under Routing Constraint”, IEEE
European Test Workshop, Informal Digest, pp. 251-256, Maastricht,
Pays-Bas, 25-28 Mai 2003.
P. Girard, O. Héron, S. Pravossoudovitch et M.
Renovell, “Requirements for Delay Testing of Look-Up Tables in
SRAM-Based FPGAS”, IEEE European Test Workshop, Formal Proceedings, pp.
147-152, Maastricht, Pays-Bas, 25-28 Mai 2003.
S. Borri, M. Hage Hassan, P. Girard, S.
Pravossoudovitch et A. Virazel, “Defect-Oriented Dynamic Fault Models
for Embedded-SRAMs”, IEEE European Test Workshop, Formal Proceedings,
pp. 23-28, Maastricht, Pays-Bas, 25-28 Mai 2003.
Y. Bonhomme, P. Girard, L. Guiller, C.
Landrault, S. Pravossoudovitch et A. Virazel, “Design of
Routing-Constrained Low Power Scan Chains”, IEEE International Workshop
on Electronic Design, Test & Applications, pp. 287-292, Perth,
Australie, 28-30 Janvier 2004.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et S. Borri, “March Tests Improvement for Address Decoder Open
and Resistive Open Fault Detection”, IEEE Latin American Test Workshop,
pp. 31-36, Cartagena, Colombie, 8-10 Mars 2004.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et M. Bastian Hage-Hassan, “Efficient Test of Dynamic Read
Destructive Faults in SRAM Memories”, IEEE Latin American Test
Workshop, pp. 40-45, Salvador Bahia, Brésil, 30 Mars – 2 Avril 2005.
N. Badereddine, P. Girard, S.
Pravossoudovitch, C. Landrault et A. Virazel, “Peak Power Consumption
during Scan Testing: Issue, Analysis and Heuristic Solution”, IEEE
Workshop on Design and Diagnostics of Electronic Circuits and Systems,
pp. 151-159, Sopron, Hongrie, 13-16 Avril 2005.
Y. Bonhomme, T. Yoneda, H. Fujiwara et P.
Girard, “Test Application Time Reduction with a Dynamically
Reconfigurable Scan Tree Architecture”, IEEE Workshop on Design and
Diagnostics of Electronic Circuits and Systems, pp. 19-26, Sopron,
Hongrie, 13-16 Avril 2005.
N. Badereddine, P. Girard, A. Virazel, S.
Pravossoudovitch et C. Landrault, “Controlling Peak Power Consumption
during Scan Testing: Power-aware DfT and Test Set Perspectives”, IEEE
International Workshop on Power And Timing Modeling, Optimization and
Simulation, proceedings published by Springer, pp. 540-549, Louvain,
Belgique, 21-23 Septembre 2005.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et M. Bastian, “March Pre: an Efficient Test for Resistive-Open
Defects in the SRAM Pre-charge Circuit”, IEEE Workshop on Design and
Diagnostics of Electronic Circuits and Systems, pp. 256-261, Prague,
République Tchèque, Avril 2006.
L. Dilillo, B.M. Al-Hashimi, P. Rosinger et P.
Girard, “Leakage Read Fault in Nanoscale SRAM: Analysis, Test and
Diagnosis”, IEEE International Design and Test Workshop, pp. 110-115,
Dubai, Emirats Arabes Unis, 19-20 Novembre 2006.
A. Bosio, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel et A. Rousset, “A Mixed Approach for
Unified Logic Diagnosis”, IEEE Workshop on Design and Diagnostics of
Electronic Circuits and Systems, pp. 239-242, Cracovie, Pologne, Avril
2007.
A. Bosio, P. Girard, S. Pravossoudovitch et P.
Bernardi, “SoC Symbolic Simulation: a case study on delay fault
testing”, IEEE Workshop on Design and Diagnostics of Electronic
Circuits and Systems, pp. 1-6, Bratislava, Slovaquie, Avril 2008.
L. Dilillo, A. Bosio, P. Rech, P. Girard, F. Wrobel et F. Saigné,
“Robust Data Collection and Transfer Framework for a Distributed SRAM
Based Neutron Sensor”, IEEE International Workshop on Advances in
Sensors and Interfaces, pp. 176-180, Brindisi, Italie, 28-29 Juin 2011.
G.
Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A.
Todri, A. Virazel, J. Mekki, M. Brugger, J.R. Vaillé, F. Wrobel et F.
Saigné, “Characterization of an SRAM Based Particle Detector for
Mixed-Field Radiation Environments”, IEEE International Workshop on
Advances in Sensors and Interfaces, pp. 239-242, Bari, Italie, 13-14
Juin 2013.
A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et P.
Bernardi, “A Comprehensive Evaluation of Functional Programs for
Power-Aware Test”, IEEE North Atlantic Test Workshop, pp. 69-72,
Wakefield, USA, 14-16 Mai 2014.
S. Mhamdi, P. Girard, A. Virazel, A. Bosio, E. Fhaen et A. Ladhar,
“Cell-Aware Diagnosis of Automotive Customer Returns Based on
Supervised Learning”, IEEE International Workshop on Automotive
Reliability & Test, Washington, USA, 14-15 novembre 2019.
P. Girard, C. Landrault et
S. Pravossoudovitch, “Delay Fault Diagnosis in Digital Circuits”, ATSEC
Open Workshop (ESPRIT III Basic Research), Turin, Italie, 27-29
Septembre 1993.
P. Girard, C. Landrault et
S. Pravossoudovitch, “Diagnostic and Simulation for Delay Faults in
Digital Circuits”, ATSEC Open Workshop (ESPRIT III Basic Research),
Enschede, Pays-Bas, 6-7 Septembre 1994.
P. Girard, C. Landrault et
S. Pravossoudovitch, “Diagnostic and Simulation of Delay Faults in
Combinational and Sequential Circuits”, ARCHIMEDES / ATSEC Open
Workshop (ESPRIT III Basic Research), Sankt Augustin, Allemagne, 28-29
Septembre 1995.
P. Girard, L. Guiller, C.
Landrault et S. Pravossoudovitch, “Low Power/Energy BIST Design by
Partitioning VLSI Circuits”, SAME: Sophia Antipolis forum on
Microelectronics, Sophia Antipolis, France, 21-22 October 1999.
N. Badereddine, P. Girard,
S. Pravossoudovitch, C. Landrault, A. Virazel et H.J. Wunderlich,
“Structural-Based Power-Aware Assignment of Don’t Cares for Peak Power
Reduction during Scan Testing”, IEEE European Test Symposium,
Southampton, Grande-Bretagne, 21-25 Mai 2006.
P. Girard, S.
Pravossoudovitch, A. Virazel et M. Bastian, “Failure Mechanisms due to
Process Variations in Nanoscale SRAM Core-cells”, IEEE European Test
Symposium, Southampton, Grande-Bretagne, 21-25 Mai 2006.
A. Rousset, P. Girard, S.
Pravossoudovitch, C. Landrault, et A. Virazel, “ Unified Diagnostic
Method Targeting Several Fault Models”, IFIP VLSI-SOC Conference, PhD
Forum, Nice, France, 16-18 Octobre 2006.
R. Alves Fonseca, A. Bosio,
L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel et N.
Badereddine, “Analysis of Resistive-Bridging Defects in SRAM Core-Cell:
Impact within the Core-Cell and in the Memory Array”, IEEE European
Test Symposium, Seville, Espagne, 24-28 Mai 2009.
Y. Benabboud, A. Bosio, L.
Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, L. Bouzaida et I.
Izaute “A Logic Diagnosis Approach for Sequential Circuits”, IEEE
European Test Symposium, PhD Forum, Seville, Espagne, 24-28 Mai 2009.
J. Vial, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch et A. Virazel, “SoC Yield Improvement for Future
Nanoscale Technologies”, IEEE European Test Symposium, PhD Forum,
Seville, Espagne, 24-28 Mai 2009.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Virazel et X. Wen, “Trade-off between Power
Dissipation and Delay Fault Coverage for LOS and LOC Testing Schemes”,
2nd International Workshop on the Impact of Low Power on Test and
Reliability (LPonTR’09), Seville, Espagne, 24-28 Mai 2009.
R. Fonseca, L. Dilillo, A. Bosio, P. Girard,
S. Pravossoudovitch, A. Virazel et N. Badereddine, “Setting Test
Conditions for Detecting Faults Induced by Random Dopant Fluctuation in
SRAM Core-Cells”, 1st European workshop on CMOS Variability (VARI’10),
Montpellier, France, 26-27 Mai 2010.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen et N.
Ahmed, “Power Reduction Through X-filling of Transition Fault Test
Vectors for LOS Testing”, 3rd International Workshop on the Impact of
Low Power on Test and Reliability (LPonTR’10), Prague, Czech Republic,
27-28 Mai 2010.
K. Miyase, F. Wu, L. Dilillo, A. Bosio, P.
Girard, W. Wen et S. Kajihara, “X-Identification of Transition Delay
Fault Tests for Launch-off Shift Scheme”, IEEE Workshop on
RTL and High Level Testing, Shanghai, Chine, Decembre 2010.
R. Alves Fonseca, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Virazel et N. Badereddine, “Variability Analysis of an SRAM Test
Chip”, IEEE European Test Symposium, Trondheim, Norvège, 23-27 Mai 2011.
L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovith et A. Virazel,
“Robust Structure for Data Collection and Transfer in a Distributed
SRAM Based Neutron Test Bench”, Workshop on Dependability Issues in
Deep-submicron Technologies, Trondheim, Norvège, 26-27 Mai 2011.
H. Salmani, W. Zhao, M. Tehranipoor, S. Chakravarty, P. Girard, X. Wen,
“Layout-Aware Pattern Evaluation and Analysis for Power-Safe
Application of TDF Patterns”, IEEE International Workshop on the Impact
of Low Power on Test and Reliability (LPonTR’11), Trondheim, Norvège,
26-27 Mai 2011.
A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch et A.
Virazel, “Simultaneous Power and Thermal Integrity Analysis for 3D
Integrated Systems”, IEEE International Workshop on the Impact of Low
Power on Test and Reliability (LPonTR’11), Trondheim, Norvège, 26-27
Mai 2011.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A.
Virazel, M. Tehranipoor, K. Miyase, X. Wen et N. Ahmed, “Mapping Test
Power to Functional Power through Smart X-Filling for LOS Scheme”, IEEE
International Workshop on the Impact of Low Power on Test and
Reliability (LPonTR’11), Trondheim, Norvège, 26-27 Mai 2011.
A. Todri, A. Bosio, L. Dilillo, P. Girard et A. Virazel,
“Electro-Thermal Analysis of 3D Power Delivery Networks”, ACM Design
Automation Conference, Work-In-Progress Session, San Fransisco, USA,
3-7 Juin 2012.
Z. Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et E.
Auvray, “Improving Defect Localization Accuracy by Means of
Effect-Cause Intra-Cell Diagnosis at Transistor Level”, IEEE
International Workshop on Silicon Debug and Diagnosis, Anaheim, USA,
8-9 Novembre 2012.
D. Adil Patel, R. Wilson, F. Gardic, S. Naudet, P. Brahic, A. Virazel
et P. Girard, “Simulation & Silicon Verification of Adaptive
Voltage Scaling for Real Applications”, SNUG (Synopsys Users Group)
Conference, Grenoble, France, 18 Juin 2015.
A. Bosio, P. Debaud, P. Girard, S. Guilhot, M. Valka et A. Virazel,
“Under-limits Voltage Scaling: The benefit of Approximate Computing”,
2nd Workshop On Approximate Computing (WAPCO), Prague, République
Tchèque, 18-20 Janvier 2016.
I. Wali, A. Virazel, P. Girard, A. Bosio et M. Barbareschi, “A Case
study on the Approximate Test of Integrated Circuits”, Workshop on
Approximate Computing (CA), Pittsburgh, USA, 6 Octobre 2016.
I. Wali, M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio,
“Can we Approximate the Test of Integrated Circuits?”, 3rd Workshop On
Approximate Computing (WAPCO), Stockholm, Suède, 25 Janvier 2017.
T.P. Ho, E. Faehn, A. Virazel, A. Bosio, P. Girard et P. Loth, “An
Advanced Diagnosis Flow Using CustomSim for SRAMs”, SNUG (Synopsys
Users Group) Conference, Grenoble, France, 22 Juin 2017.
M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Testing
Integrated Circuits for Approximate Computing Applications”, 4th
Workshop On Approximate Computing (WAPCO), Manchester, Angleterre, 22
Janvier 2018.
B. Deveautour, A. Virazel, P. Girard et A. Bosio, “On Using Approximate
Computing to Build an Error Detection Scheme”, 3rd Workshop on
Approximate Computing (AxC’18), Breme, Allemagne, 31 mai – 1 juin 2018.
M. Traiola, A. Virazel et P. Girard, “On the Testing of Approximate
Integrated Circuits for Embedded applications considering Average-Error
Metrics”, 3rd Workshop on Approximate Computing (AxC’18), Breme,
Allemagne, 31 mai – 1 juin 2018.
P. Girard, C. Landrault et S. Pravossoudovitch,
“Diagnostic de Pannes Temporelles dans les Circuits Digitaux”, Journée
AFCET : Sureté de fonctionnement des systèmes informatiques, Paris,
France, 8 Février 1994.
P. Girard, C. Landrault, S. Pravossoudovitch et
D. Severac, “Re-dimensionnement de portes des circuits CMOS pour une
réduction de la consommation de puissance”, Colloque CAO de circuits
intégrés et systèmes, Grenoble (Villard de Lans), 15-17 Janvier 1997.
P. Girard, C. Landrault, V. Moreda et S.
Pravossoudovitch, “Générateur de Vecteurs de Test Intégré pour Pannes
Temporelles”, Colloque CAO de circuits intégrés et systèmes, Grenoble
(Villard de Lans), 15-17 Janvier 1997.
P. Girard, C. Landrault, S. Pravossoudovitch et
A. Virazel, “Analyse des Capacités de Test de Générateurs Intégrés
Produisant des Vecteurs Adjacents”, Colloque CAO de circuits intégrés
et systèmes, Aix en Provence, 10-12 Mai 1999.
P. Girard, L. Guiller, C. Landrault et S.
Pravossoudovitch, “Stratégie de Réduction de la Consommation d'Energie
lors du Test des Circuits Intégrés”, Colloque CAO de circuits intégrés
et systèmes, Aix en Provence, 10-12 Mai 1999.
P. Girard, O. Heron, S. Pravossoudovitch et M.
Renovell, “Pannes Temporelles dans les FPGA”, Colloque CAO de circuits
intégrés et systèmes, Paris, 15-17 Mai 2002.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel, S. Borri et M. Hage-Hassan, “Test March pour la Détection des
Fautes Dynamiques dans les Décodeurs de Mémoires SRAM”,7ième
Journées Nationales du Réseau Doctoral en Microélectronique, Marseille,
4-6 Mai 2004.
N. Badereddine, P. Girard, S. Pravossoudovitch,
A. Virazel et C. Landrault, “Analyse et Réduction de la Puissance de
Pic durant le Test Série”, 8ième Journées Nationales du Réseau Doctoral
en Microélectronique, Paris, 10-12 Mai 2005.
L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel, et M. Hage-Hassan, “Incidence des Fautes Résistifs dans les
Circuits de Precharge des Mémoires SRAM”, 8ième Journées Nationales du
Réseau Doctoral en Microélectronique, Paris, 10-12 Mai 2005.
N. Badereddine, P. Girard, S.
Pravossoudovitch, C. Landrault, A. Virazel et H.J. Wunderlich,
“Technique Structurelle d’Affectation des Bits Non Spécifiés en Vue
d’une Réduction de la Puissance de Pic Pendant le Test Série”, 9ième
Journées Nationales du Réseau Doctoral en Microélectronique, Rennes,
10-12 Mai 2006.
A. Rousset, P. Girard, S. Pravossoudovitch, C.
Landrault, et A. Virazel, “Méthode Unifiée de Diagnostic Ciblant
l’Ensemble des Modèles de Fautes”, 9ième Journées Nationales du Réseau
Doctoral en Microélectronique, Rennes, 10-12 Mai 2006.
A. Rousset, P. Girard, S. Pravossoudovitch, C.
Landrault, et A. Virazel, “Méthode Unifiée de Diagnostic Ciblant
l’Ensemble des Modèles de Fautes”, Conférence MajecSTIC - MAnifestation
des Jeunes Chercheurs STIC, Lorient, 22-24 Novembre 2006.
O. Ginez, J.M. Daga, P. Girard, C. Landrault,
S. Pravossoudovitch et A. Virazel, “Embedded Flash Testing”, Colloque
National du GDR SoC-SiP, Paris, 13-15 Juin 2007.
J. Vial, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “Test et Testabilité de Structures
Numériques Tolérantes aux Fautes”, Colloque National du GDR SoC-SiP,
Paris, 13-15 Juin 2007.
A. Rousset, A. Bosio, P. Girard, C. Landrault,
S. Pravossoudovitch et A. Virazel, “Méthode de Diagnostic Unifiée pour
Circuits Intégrés Numériques”, Colloque National du GDR SoC-SiP, Paris,
13-15 Juin 2007.
A. Ney, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel et M. Bastian, “ Resistive-Open Defect
Influences in SRAM I/O Circuitry”, Colloque National du GDR SoC-SiP,
Paris, 13-15 Juin 2007.
J. Vial, A. Bosio, P. Girard, C. Landrault, S.
Pravossoudovitch et A. Virazel, “Tolérer Plus pour Fabriquer Plus”,
Colloque National du GDR SoC-SiP, Paris, 4-6 Juin 2008.
Y. Benabboud, A. Bosio, P. Girard, S.
Pravossoudovitch, L. Bouzaida et I. Izaute, “Case Study on Logic
Diagnosis for Industrial Circuits”, Colloque National du GDR SoC-SiP,
Paris, 4-6 Juin 2008.
A. Ney, P. Girard, C. Landrault, S.
Pravossoudovitch, A. Virazel et M. Bastian, “A History-Based Technique
for Fault Diagnosis in SRAM Memories”, Colloque National du GDR
SoC-SiP, Paris, 4-6 Juin 2008.
J. Vial, C. Landrault, A. Bosio, P. Girard, S.
Pravossoudovitch et A. Virazel, “ Utilisation de Structures Tolérantes
aux Fautes pour Augmenter le Rendement”, 11ième Journées Nationales du
Réseau Doctoral en Microélectronique, Mai 2008.
R. Alves Fonseca, L. Dilillo, A. Bosio, P.
Girard, S. Pravossoudovitch, A. Virazel et N. Badereddine, “SRAM
Core-cell Quality Metrics”, Colloque National du GDR SoC-SiP, Paris,
10-12 Juin 2009.
P.D. Mauroux, A. Virazel, A. Bosio, L.
Dilillo, P. Girard et S. Pravossoudovitch, “Test des Mémoires FLASH
NAND”, Colloque National du GDR SoC-SiP, Paris, 10-12 Juin 2009.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Virazel et X. Wen, “ Trade-off Between Power
Dissipation and Delay Fault Coverage For LOS and LOC Testing Schemes”,
Colloque National du GDR SoC-SiP, Paris, 10-12 Juin 2009.
D. Mauroux, A. Virazel, A. Bosio, L. Dilillo,
P. Girard, S. Pravossoudovitch, B. Godard, G. Festes et L. Vachez,
“Analyse et modélisation des défauts résistifs affectant les mémoires
Flash”, Colloque National du GDR SoC-SiP, Cergy, 9-11 Juin 2010.
F. Wu, L. Dilillo, A. Bosio, P. Girard, S.
Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen et N.
Ahmed, “Test Relaxation and X-filling to Reduce Peak Power During
At-Speed LOS Testing”, Colloque National du GDR SoC-SiP, Cergy, 9-11
Juin 2010.
D. A. Tran, A. Virazel, P. Girard, S.
Pravossoudovitch, H-J Wunderlich, A. Bosio et L. Dilillo, “Tolérance
aux Fautes et Rendement de Fabrication”, Colloque National du GDR
SoC-SiP, Cergy, 9-11 Juin 2010.
D.A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch et H.J. Wunderlich, “Robustness Improvement of Digital
Circuits : A New Hybrid Fault Tolerant Architecture”, 14ième Journées
Nationales du Réseau Doctoral en Microélectronique, Paris, 23-25 Mai
2011.
L.B. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et N. Badereddine, “Optimized March Test Flow for Detecting
Memory Faults in SRAM Devices Under Bit Line Coupling”, 14ième Journées
Nationales du Réseau Doctoral en Microélectronique, Paris, 23-25 Mai
2011.
L.B. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Virazel et N. Bedereddine, “Optimized March Test Flow for Detecting
Memory Faults in SRAM Devices Under Bit Line Coupling”, Colloque
National du GDR SoC-SiP, Lyon, 15-17 Juin 2011.
D.H. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S.
Pravossoudovitch et H.J. Wunderlich, “A Hybrid Fault Tolerant
Architecture for Robustness Improvement of Digital Circuits”, Colloque
National du GDR SoC-SiP, Lyon, 15-17 Juin 2011.
J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard et S.
Pravossoudovitch, “Test and Reliability of Magnetic Random Access
Memories”, Colloque National du GDR SoC-SiP, Lyon, 15-17 Juin 2011.
L.B. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A.
Todri, A. Virazel et N. Bedereddine, “Failure Analysis and Test
Solutions for Low-Power SRAMs”, Journées Electroniques Club EEA / GDR
SoC-SiP / GDR SEEDS / CNFM, “Technologies émergentes et Green Soc-Sip”,
Montpellier, 27-28 Octobre 2011.
M. De Carvalho, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel,
P. Bernardi et M. Sonza Reorda, “A Functional Power Evaluation Flow for
Defining Test Power Limits during At-Speed Delay Testing”, Journées
Electroniques Club EEA / GDR SoC-SiP / GDR SEEDS / CNFM, “Technologies
émergentes et Green Soc-Sip”, Montpellier, 27-28 Octobre 2011.
Z. Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et E.
Auvray, “Effective Defect Localization Through an Effect-Cause based
Intra-Cell Diagnosis”, Colloque National du GDR SoC-SiP, Paris, 13-15
Juin 2012.
J. Azevedo, A. Bosio, L. Dilillo, P. Girard, A. Todri et A. Virazel,
“Impacts of Resistive-Open Defects in the Word-Line Selection of
TAS-MRAMs”, Colloque National du GDR SoC-SiP, Paris, 13-15 Juin 2012.
C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard et A. Virazel,
“Through-Silicon-Via Resistive-Open Defect Analysis”, Colloque National
du GDR SoC-SiP, Paris, 13-15 Juin 2012.
M. Valka, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et P.
Debaud, “Adaptive Voltage Scaling via Effective On-Chip Timing
Uncertainty Measurements”, Colloque National du GDR SoC-SiP, Paris,
13-15 Juin 2012.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri et A.
Virazel, “Dynamic Mode Testing of SRAMS under Neutron Radiation”,
Colloque National du GDR SoC-SiP, Paris, 13-15 Juin 2012.
J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard et A. Todri,
“Performance Evaluation of Capacitive defects on TAS-MRAMs”, Colloque
National du GDR SoC-SiP, Lyon, 10-12 Juin 2013.
G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch,
A. Todri et A. Virazel, “Investigating Multiple-Cell-Upsets on a 90mn
SRAM”, Colloque National du GDR SoC-SiP, Lyon, 10-12 Juin 2013.
Z. Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel et E.
Auvray, “Fault-Effect Propagation Based Intra-cell Scan Chain
Diagnosis”, Colloque National du GDR SoC-SiP, Lyon, 10-12 Juin 2013.
A. Touati, A. Bosio, L. Dilillo, P. Girard et A. Virazel, “A
Comprehensive Evaluation of Functional Programs for Power-Aware Test”,
Colloque National du GDR SoC-SiP, Paris, 11-13 Juin 2014.
A. Asokan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch et A.
Virazel, “Crosstalk and Supply Noise - Aware Pattern Generation for
Delay Testing”, Colloque National du GDR SoC-SiP, Paris, 11-13 Juin
2014.
I. Wali, A. Virazel, A. Bosio, L. Dilillo et P. Girard, “A
Fault-tolerant Architecture for Pipelined Microprocessor Cores”,
Colloque National du GDR SoC-SiP, Paris, 11-13 Juin 2014.
D.A. Patel, S. Naudet, L. Echene, A. Virazel, A. Bosio et P. Girard,
“Design and Implementation of Novel Test Strategies for High Quality
Test”, 18ième Journées Nationales du Réseau Doctoral en
Microélectronique, Bordeaux, 5-7 Mai 2015.
A. Nocua, A. Virazel, A. Bosio, L. Dilillo et P. Girard, “Effective
Transistor-Level Characterization for Accurate Gate-Level Power
Estimation”, 18ième Journées Nationales du Réseau Doctoral en
Microélectronique, Bordeaux, 5-7 Mai 2015.
I. Wali, A. Virazel, A. Bosio, L. Dilillo et P. Girard, “A Hybrid
Fault-Tolerant Architecture for Non-Linear Pipelines”, 18ième Journées
Nationales du Réseau Doctoral en Microélectronique, Bordeaux, 5-7 Mai
2015.
A. Asokan, A. Bosio, A. Virazel, L. Dilillo, P. Girard et S.
Pravossoudovitch, “Layout-Aware ATPG for Path Delay Fault”, 18ième
Journées Nationales du Réseau Doctoral en Microélectronique, Bordeaux,
5-7 Mai 2015.
D. Patel, S. Naudet, A. Virazel, A. Bosio et P. Girard, “Innovative
Test Techniques for Advanced Technology Nodes”, 19ième Journées
Nationales du Réseau Doctoral en Microélectronique, Toulouse, 11-13 Mai
2016.
A. Touati, A. Bosio, P. Girard et A. Virazel, “Exploring the Impact of
Functional Test Programs Re-Used for At-Speed Testing”, 19ième Journées
Nationales du Réseau Doctoral en Microélectronique, Toulouse, 11-13 Mai
2016.
A. Nocua Cifuentes, A. Virazel, A. Bosio et P. Girard, “A Hybrid Power
Modeling Approach to Improve High-Level Power Characterization”, 19ième
Journées Nationales du Réseau Doctoral en Microélectronique, Toulouse,
11-13 Mai 2016.
D. Patel, S. Naudet, A. Virazel, A. Bosio et P. Girard, “Test and
Characterization Methodologies for FDSOI”, Colloque National du GDR
SoC-SiP, Nantes, 8-10 Juin 2016.
A. Touati, A. Bosio, P. Girard et A. Virazel, “Exploring the Impact of
Functional Test Programs Re-Used for At-Speed Testing”, Colloque
National du GDR SoC-SiP, Nantes, 8-10 Juin 2016.
A. Nocua Cifuentes, A. Virazel, A. Bosio et P. Girard, “Cross-Level
Power Estimation to Improve High-Level Power Characterization”,
Colloque National du GDR SoC-SiP, Nantes, 8-10 Juin 2016.
T.P. Ho, E. Faehn, A. Virazel, A. Bosio et P. Girard, “An Advanced
Diagnosis Flow for SRAMs”, Colloque National du GDR SoC-SiP, Bordeaux,
14-16 Juin 2017.
M. Traiola, A. Bosio, P. Girard et A. Virazel, “A Case Study on the
Approximate Test of Integrated Circuits”, Colloque National du GDR
SoC-SiP, Bordeaux, 14-16 Juin 2017.
T.P. Ho, E. Faehn, A. Virazel, A. Bosio et P. Girard, “An Automated
Intra-Cell Diagnosis Flow for Industrial SRAMs”, Colloque National du
GDR SOC2, Paris, 13-15 Juin 2018.
B. Deveautour, A. Virazel, A. Bosio et P. Girard, On using Approximate
Computing in Duplication Schemes”, Colloque National du GDR SOC2,
Paris, 13-15 Juin 2018.
M. Traiola, A. Bosio, P. Girard et A. Virazel, “Automatic Test Pattern
Generation for Approximate Integrated Circuits”, Colloque National du
GDR SOC2, Paris, 13-15 Juin 2018.
Safa Mhamdi, Alberto Bosio, Arnaud Virazel et P. Girard,
“Systems-on-Chip Diagnosis for Automotive Applications”, Colloque
National du GDR SOC2, Paris, 13-15 Juin 2018.
M. Traiola, A. Virazel, P. Girard et A. Bosio, “Test Techniques for
Approximate Integrated Circuits”, Colloque National du GDR SOC2,
Montpellier, 19-21 Juin 2019.
S. Mhamdi, A. Virazel, P. Girard, A. Bosio, E. Auvray, E. Faehn, A.
Ladhar, “A Learning-Guided Intra-Cell Diagnosis Flow for
System-on-Chip”, Colloque National du GDR SOC2, Montpellier, 19-21 Juin
2019.
B. Deveautour, A. Virazel et P. Girard, “On using Approximate Computing
in Arithmetic Circuit Duplication Schemes”, Colloque National du GDR
SOC2, Montpellier, 19-21 Juin 2019.
P. Girard, “Diagnostic and Simulation of Delay
Faults in Digital Circuits”, Invité par la société Lucent Technologies
(Bell Labs), Murray Hill, USA, Mai 1996.
P. Girard, “Testing Delay Faults in Scan-Based
Designs”, Invité par la société Intel, Santa Clara, USA, Mars 2000.
P. Girard, “Considering Power Consumption
during Scan Testing and BIST”, Invité par la société Synopsys, Mountain
View, USA, Avril 2001.
P. Girard, “Delay Fault Testing in Logic ICs”,
Invité par la société Infineon, Sophia Antipolis, France, Janvier 2002.
P. Girard, “Low Power BIST of VLSI Circuits”,
Invité par la société Philips, Eindhoven, Pays-Bas, Septembre 2002.
P. Girard, “Test de Fautes de Délai dans les
Circuits Intégrés Numériques”, Réunion Action Spécifique CNRS
“TestSOC-MRF”, Montpellier, France, 5 Mars 2004.
P. Girard, “European Projects: What Type of
Instruments for What Type of Research?”, 1st Reconfigurable
Communication-centric SoCs Workshop, Panel on European Projects,
Montpellier, 27-29 Juin 2005.
P. Girard, “Diagnostic de Fautes Electriques
dans les Circuits Logiques”, Invité par la société ST Microelectronics,
Crolles, France, avril 2006.
P. Girard, “Test Faible Consommation des
Circuits Numériques”, Invité par la société ATMEL, Nantes, France, Mars
2007.
P. Girard, Tutoriel intitulé “Power-Aware
Testing and Test Strategies for Low Power Devices” dispensé dans le
cadre de la conference IEEE/ACM Design Automation and Test in Europe
(DATE), à Munich, Allemagne, 10 Mars 2008.
P. Girard, Tutoriel intitulé “Power-Aware
Testing and Test Strategies for Low Power Devices” dispensé dans le
cadre de la conference IEEE International Conference on Design &
Technology of Integrated Systems (DTIS), à Touzeur, Tunisie, 24 Mars
2008.
P. Girard, Keynote intitulé “Power : The New
Dimension of Test” donné dans le cadre du congrès IEEE Workshop on RTL
and High Level Testing (WRTLT), à Sapporo, Japon, 28 Novembre 2008.
P. Girard, “Power : The New Dimension of
Test”, Invité par la société Hitachi, Tokyo, Japon, 29 Novembre 2008.
P. Girard, Tutoriel intitulé “Power-Aware
Testing and Test Strategies for Low Power Devices” dispensé dans le
cadre de la conference IEEE International Test Conference (ITC), à
Austin, Texas, USA, 1er Novembre 2009.
P. Girard, Tutoriel intitulé “Power-Aware
Testing and Test Strategies for Low Power Devices” dispensé dans le
cadre de la conference IEEE Asian Test Symposium (ATS), à Taichung,
Taiwan, 23 Novembre 2009.
P. Girard, “Test Strategies for Low Power
Devices”, Invité par la société Faraday Technology Corporation,
Hsin-Chu, Taiwan, 26 Novembre 2009.
P. Girard, Tutoriel intitulé “Power-Aware
Testing and Test Strategies for Low Power Devices” dispensé dans le
cadre de la conference IEEE Latin American Test Workshop (LATW), à
Punta del Este, Uruguay, 28 Mars 2010.
P. Girard, “Test Faible Consommation
d’Energie”, école thématique CNRS ECOFAC, Plestin-les-Grèves, France, 2
Avril 2010.
P. Girard, “Test Strategies for Low Power
Devices”, Invité par la société ST-Ericsson, Grenoble, 28 Avril 2010.
P. Girard, Tutoriel intitulé “Power-Aware
Testing and Test Strategies for Low Power Devices” dispensé dans le
cadre de la IEEE International NEWCAS Conference, à Montreal, Canada,
20 Juin 2010.
P. Girard, Tutoriel intitulé “Power-Aware
Testing and Test Strategies for Low Power Devices” dispensé dans le
cadre de la conference IEEE International Midwest Symposium on Circuits
and Systems (MWSCAS), à Seattle, USA, 1er Août 2010.
P. Girard, Tutoriel intitulé “Power-Aware Testing and Test Strategies
for Low Power Devices” dispensé dans le cadre de la conference IEEE
International Conference on Microelectronics (ICM), Le Caire, Egypte,
19 Décembre 2010.
P. Girard, “Un Etat de l’art sur le Diagnostic Logique”, Invité par la
société ST Microelectronics, Grenoble, France, Janvier 2011.
P. Girard, “Test Strategies for Digital Low Power Devices”, Invité par
la société Intel Mobile Communications, Sophia Antipolis, France,
Janvier 2011.
P. Girard, Tutoriel intitulé “Power-Aware Testing and Test Strategies
for Low Power Devices” dispensé dans le cadre de la conference IEEE/ACM
Design Automation and Test in Europe (DATE), à Grenoble, France, 14
Mars 2011.
P. Girard, Tutoriel intitulé “Advanced Test Methods for SRAMs” dispensé
dans le cadre de la conference IEEE Latin American Test Workshop
(LATW), à Porto de Galinhas, Brésil, le 30 Mars 2011.
P. Girard, “Test Strategies for Low Power Devices”, Invité par la
société LSI Logic, Milpitas, USA, Mai 2011.
P. Girard, Tutoriel intitulé “Power-Aware Testing and Test Strategies
for Low Power Devices” dispensé dans le cadre du congrès IEEE
International Test Conference (ITC), à Anaheim, Californie, USA, 19
Septembre 2011.
P. Girard, Tutoriel intitulé “Power-Aware Testing and Test Strategies
for Low Power Devices” dispensé dans le cadre du congrès IEEE
International Symposium on Quality of Electronic Design (ISQED), à
Santa Clara, Californie, USA, 20 Mars 2012.
P. Girard, Tutoriel intitulé “Advanced Test Methods for SRAMs” dispensé
dans le cadre du congrès IEEE VLSI Test Symposium (VTS), à Hawai, USA,
le 25 Avril 2012.
P. Girard, Tutoriel intitulé “Power-Aware Testing and Test Strategies
for Low Power Devices” dispensé dans le cadre du congrès IEEE
International Test Conference (ITC), à Anaheim, Californie, USA, 4
Novembre 2012.
P. Girard, Tutoriel intitulé “Power-Aware Testing and Test Strategies
for Low Power Devices” dispensé dans le cadre du congrès IEEE Asian
Test Symposium (ATS), à Niigata, Japon, 19 Novembre 2012.
P. Girard, “Test Strategies for Low Power Devices”, Invité par les
sociétés DOCEA Power et DeFacTo Technologies, Grenoble, France, Mars
2014.
P. Girard, Tutoriel intitulé “Power-Aware Testing in the Era of IoT”
dispensé dans le cadre du congrès IEEE Asian Test Symposium (ATS), à
Taipei, Taiwan, le 27 Novembre 2017.
P. Girard, “Power-Aware Testing in the Era of IoT”, Invité par la société MediaTeck, Hsinchu, Taiwan, 30 novembre 2017.
P. Girard, Tutoriel intitulé “Power-Aware Testing in the Era of IoT”
dispensé dans le cadre du congrès IEEE International Symposium on
Quality Electronic Design (ISQED), à Santa Clara, USA, le 13 Mars 2018.
P. Girard, Tutoriel intitulé “Power-Aware Testing in the Era of IoT ”
dispensé dans le cadre du congrès IEEE Latin American Test Symposium
(LATS), à Sao Paulo, Brésil, 16 Mars 2018.
P. Girard, Tutoriel intitulé “Power-Aware Testing in the Era of IoT ”
dispensé dans le cadre du congrès IEEE International Symposium on
Circuits & Systems (ISCAS), à Florence, Italie, 29 Mai 2018.
P. Girard, Tutoriel intitulé “Power-Aware Testing in the Era of IoT”
dispensé dans le cadre du congrès IEEE Asian Test Symposium (ATS), à
Hefei, Chine, le 15 Octobre 2018.
P. Girard, “Power-Aware Testing in the Era of IoT”, Invité par la société ChipMotion, Hefei, Chine, 16 Octobre 2018.
P. Girard, Tutoriel intitulé “Developments and Practices for Testing
MRAM Memories” dispensé dans le cadre du congrès IEEE International
Symposium on Quality Electronic Design (ISQED), à Santa Clara, USA, le
7 Mars 2019.
P. Girard, Tutoriel intitulé “Power-Aware Testing in the Era of IoT”
dispensé dans le cadre du congrès IEEE International Test Conference
(ITC), à Washington, USA, 11 Novembre 2019.
P. Girard, Tutoriel intitulé “Developments and Practices for Testing
MRAM Memories” dispensé dans le cadre du congrès IEEE International
Conference on Microelectronics (ICM), au Caire, Egypte, le 16 Décembre
2019.
D. Dumas, P. Girard, C. Landrault et S.
Pravossoudovitch, “Determination of delay fault detectability
conditions”, Rapport final tâche WP2-5, Contrat ESPRIT III Basic
Research “ATSEC”, Janvier 1994.
D. Dumas, P. Girard, C. Landrault et S.
Pravossoudovitch, “Evaluation of delay fault diagnosis possibilities by
critical path tracing algorithms”, Rapport final tâche WP2-6, Contrat
ESPRIT III Basic Research “ATSEC”, Janvier 1994.
D. Dumas, P. Girard, C. Landrault et S.
Pravossoudovitch, “Software Prototype for Delay Fault Diagnosis in
Combinational Circuits”, Rapport final tâche WP2-7, Contrat ESPRIT III
Basic Research “ATSEC”, Janvier 1994.
P. Cavallera, P. Girard, C. Landrault, S.
Pravossoudovitch et B. Rodriguez, “Proposition of a Sequential Delay
Fault Diagnosis Method and Algorithm”, Rapport final tâche WP 2-7,
Contrat ESPRIT III Basic Research, “ATSEC”, Janvier 1995.
P. Cavallera, P. Girard, C. Landrault, S.
Pravossoudovitch et B. Rodriguez, “Proposition of a Sequential Delay
Fault Diagnosis Method and Algorithm”, Rapport final tâche WP 2-8,
Contrat ESPRIT III Basic Research “ATSEC”, Janvier 1995.
P. Cavallera, P. Girard, C. Landrault, S.
Pravossoudovitch et B. Rodriguez, “DFSIM: A Delay Fault Simulator for
Sequential Circuits”, Rapport final tâche WP 3-9, Contrat ESPRIT III
Basic Research “ATSEC”, Octobre 1995.
P. Cavallera, P. Girard, C. Landrault, S.
Pravossoudovitch et B. Rodriguez, “Description of the Delay Fault
Diagnostic Tool for Sequential Circuits”, Rapport final tâche WP 3-10,
Contrat ESPRIT III Basic Research ”ATSEC”, Octobre 1995.
D. Auvergne, F. Azais, N. Azemard, Y. Bertrand,
C. Dufaza, P. Girard, S. Pravossoudovitch et M. Renovell, Rapport
intermédiaire, tâche WP4.1, Contrat EEC-JESSI-EUREKA Project MEDEA
AT406, December 1997.
D. Auvergne, F. Azais, N. Azemard, Y. Bertrand,
C. Dufaza, P. Girard, S. Pravossoudovitch et M. Renovell, Rapport
intermédiaire, tâche WP4.1, Contrat EEC-JESSI-EUREKA Project MEDEA AT
406, Juin 1998.
D. Auvergne, F. Azais, N. Azemard, Y.
Bertrand, C. Dufaza, P. Girard, S. Pravossoudovitch et M. Renovell,
Rapport Intermédiaire, tâche WP4.1, Contrat EEC-JESSI-EUREKA Project
MEDEA AT406, Décembre 1998.
D. Auvergne, F. Azais, N. Azemard, Y.
Bertrand, C. Dufaza, P. Girard, S. Pravossoudovitch et M. Renovell,
Rapport final, tâches WP1.2 et WP4.1, Contrat EEC-JESSI-EUREKA Project
MEDEA AT406, 6 Janvier 2000.
D. Auvergne, S. Pravossoudovitch, F. Azais, N.
Azemard, Y. Bertrand, C. Dufaza, P. Girard et M. Renovell, Rapport
final, Version 1.1, Contrat EEC-JESSI-EUREKA Project MEDEA AT406, 8
Janvier 2001.
P. Girard, M. Renovell, S. Bernard, M.L.
Flottes, C. Landrault, S. Pravossoudovitch, et B. Rouzeyre, Rapport
technique de fin d’année, Contrat CEE ASSOCIATE A503 “Advanced
Solutions for Innovative SOC Testing in Europe”, Programme MEDEA+, 25
Janvier 2002.
P. Girard, M. Renovell, S. Bernard, M.L.
Flottes, C. Landrault, S. Pravossoudovitch, et B. Rouzeyre, Rapport
technique intermédiaire, Contrat CEE ASSOCIATE A503 “Advanced Solutions
for Innovative SOC Testing in Europe”, Programme MEDEA+, 19 Juillet
2002.
P. Girard, M. Renovell, S. Bernard, M.L.
Flottes, C. Landrault, S. Pravossoudovitch, et B. Rouzeyre, Rapport
technique de fin d’année, Contrat CEE ASSOCIATE A503 “Advanced
Solutions for Innovative SOC Testing in Europe”, Programme MEDEA+,
Janvier 2003.
P. Girard, N. Azemard et D. Auvergne, Premier
rapport de management du projet (PMR1), Contrat CEE MARLOW “A Central
Market Place for Dissemination of Low Power Microelectronics Design
Knowledge”, Réseau Thématique, Programme IST-2001-37115, Deliverable
R5.1, Avril 2003.
P. Girard, M. Renovell, S. Bernard, M.L.
Flottes, C. Landrault, S. Pravossoudovitch, et B. Rouzeyre, Rapport
technique intermédiaire, Contrat CEE ASSOCIATE A503 “Advanced Solutions
for Innovative SOC Testing in Europe”, Programme MEDEA+, Juillet 2003.
N. Azemard, P. Girard et D. Auvergne, Premier
rapport d’avancement du projet (PPR1), Contrat CEE MARLOW “A Central
Market Place for Dissemination of Low Power Microelectronics Design
Knowledge”, Réseau Thématique, Programme IST-2001-37115, Deliverable
D5.2, Octobre 2003.
P. Girard, M. Renovell, S. Bernard, M.L.
Flottes, S. Pravossoudovitch, et B. Rouzeyre, Rapport technique de fin
d’année, Contrat CEE ASSOCIATE A503 “Advanced Solutions for Innovative
SOC Testing in Europe”, Programme MEDEA+, Janvier 2004.
P. Girard et N. Azemard, Second rapport de
management du projet (PMR2), Contrat CEE MARLOW “A Central Market Place
for Dissemination of Low Power Microelectronics Design Knowledge”,
Réseau Thématique, Programme IST-2001-37115, Deliverable R5.3, Avril
2004.
P. Girard, M. Renovell, S. Bernard, M.L.
Flottes, S. Pravossoudovitch, et B. Rouzeyre, Rapport technique final,
Contrat CEE ASSOCIATE A503 “Advanced Solutions for Innovative SOC
Testing in Europe”, Programme MEDEA+, Juillet 2004.
P. Girard et N. Azemard, Second rapport
d’avancement du projet (PPR2), Contrat CEE MARLOW “A Central Market
Place for Dissemination of Low Power Microelectronics Design
Knowledge”, Réseau Thématique, Programme IST-2001-37115, Deliverable
D5.4, Août 2004.
P. Girard et N. Azemard, Troisième rapport de
management du projet (PMR3), Contrat CEE MARLOW “A Central Market Place
for Dissemination of Low Power Microelectronics Design Knowledge”,
Réseau Thématique, Programme IST-2001-37115, Deliverable R5.5, Mai 2005.
P. Girard, S. Bernard, M.L. Flottes, C.
Landrault, S. Pravossoudovitch, M. Renovell, B. Rouzeyre et A. Virazel,
Rapport technique intermédiaire, Contrat NanoTEST 2A702, Programme CEE
MEDEA+, Juin 2005.
P. Girard, S. Bernard, M.L. Flottes, C.
Landrault, S. Pravossoudovitch, M. Renovell, B. Rouzeyre et A. Virazel,
Rapport technique de fin d’année, Contrat NanoTEST 2A702, Programme CEE
MEDEA+, Janvier 2006.
P. Girard, S. Bernard, M.L. Flottes, C.
Landrault, S. Pravossoudovitch, M. Renovell, B. Rouzeyre et A. Virazel,
Rapport technique intermédiaire, Contrat NanoTEST 2A702, Programme CEE
MEDEA+, Juillet 2006.
P. Girard, S. Bernard, A. Bosio, M.L. Flottes,
S. Pravossoudovitch, M. Renovell, B. Rouzeyre et A. Virazel, Rapport
technique de fin d’année, Contrat NanoTEST 2A702, Programme CEE MEDEA+,
Janvier 2007.
P. Girard, S. Bernard, A. Bosio, M.L. Flottes,
S. Pravossoudovitch, M. Renovell, B. Rouzeyre et A. Virazel, Rapport
technique intermédiaire, Contrat NanoTEST 2A702, Programme CEE MEDEA+,
Juillet 2007.
P. Girard, S. Bernard, A. Bosio, M.L. Flottes,
S. Pravossoudovitch, M. Renovell, B. Rouzeyre et A. Virazel, Rapport
technique de fin d’année, Contrat NanoTEST 2A702, Programme CEE MEDEA+,
Janvier 2008.
P. Girard, S. Bernard, A. Bosio, M.L. Flottes,
S. Pravossoudovitch, M. Renovell, B. Rouzeyre et A. Virazel, Rapport
technique intermédiaire, Contrat NanoTEST 2A702, Programme CEE MEDEA+,
Juillet 2008.
P. Girard, S. Bernard, A. Bosio, L. Dilillo,
M.L. Flottes, S. Pravossoudovitch, M. Renovell, B. Rouzeyre et A.
Virazel, Rapport technique de fin de contrat, Contrat NanoTEST 2A702,
Programme CEE MEDEA+, Janvier 2009.
P. Girard, S. Bernard, A. Bosio, L. Dilillo,
M.L. Flottes, M. Renovell, B. Rouzeyre et A. Virazel, Rapport technique
intermédiaire, Contrat TOETS, Programme CEE CATRENE, Juillet 2009.
P. Girard, S. Bernard, F. Azais, A. Bosio, L.
Dilillo, G. Di Natale, M.L. Flottes, M. Renovell, B. Rouzeyre et A.
Virazel, Rapport technique de fin d’année, Contrat TOETS CT 302,
Programme CEE CATRENE, Janvier 2010.
P. Girard, S. Bernard, F. Azais, A. Bosio, L.
Dilillo, G. Di Natale, M.L. Flottes, M. Renovell, B. Rouzeyre et A.
Virazel, Rapport intermédiaire, Contrat TOETS CT 302, Programme CEE
CATRENE, Juillet 2010.
P. Girard, S. Bernard, F. Azais, A. Bosio, L. Dilillo, G. Di Natale,
M.L. Flottes, M. Renovell, B. Rouzeyre et A. Virazel, Rapport technique
de fin d’année, Contrat TOETS CT 302, Programme CEE CATRENE, Janvier
2011.
P. Girard, S. Bernard, F. Azais, A. Bosio, L. Dilillo, G. Di Natale,
M.L. Flottes, M. Renovell, B. Rouzeyre et A. Virazel, Rapport technique
intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE, Juillet
2011.
P. Girard, S. Bernard, F. Azais, A. Bosio, L. Dilillo, G. Di Natale,
M.L. Flottes, M. Renovell, B. Rouzeyre et A. Virazel, Rapport technique
de fin d’année, Contrat TOETS CT 302, Programme CEE CATRENE, Janvier
2012.
P. Girard, S. Bernard, F. Azais, A. Bosio, L. Dilillo, G. Di Natale,
M.L. Flottes, M. Renovell, B. Rouzeyre et A. Virazel, Rapport de fin de
contrat, Contrat TOETS CT 302, Programme CEE CATRENE, Juin 2012.
P. Girard, S. Bernard, F. Azais, A. Bosio, M. Comte, L. Dilillo, V.
Kerzerho, L. Latorre, M. Renovell, A. Todri et A. Virazel, Rapport
technique intermédiaire, Contrat « ELESIS » n° 296112, Programme CEE
ENIAC, Janvier 2013.
P. Girard, B. Rouzeyre, A. Todri, G. Di Natale, M.L. Flottes, et A.
Virazel, Rapport technique intermédiaire, Contrat CT312 MASTER_3D,
Programme CEE CATRENE, Juillet 2013.
P. Girard, S. Bernard, F. Azais, A. Bosio, M. Comte, L. Dilillo, V.
Kerzerho, L. Latorre, M. Renovell, A. Todri et A. Virazel, Rapport
technique de fin d’année, Contrat « ELESIS » n° 296112, Programme CEE
ENIAC, Juillet 2013.
P. Girard, B. Rouzeyre, A. Todri, G. Di Natale, M.L. Flottes, et A.
Virazel, Rapport technique de fin d’année, Contrat CT312 MASTER_3D,
Programme CEE CATRENE, Décembre 2013.
P. Girard, S. Bernard, F. Azais, A. Bosio, M. Comte, L. Dilillo, V.
Kerzerho, L. Latorre, M. Renovell, A. Todri et A. Virazel, Rapport
technique intermédiaire, Contrat « ELESIS » n° 296112, Programme CEE
ENIAC, Janvier 2014.
P. Girard, B. Rouzeyre, G. Di Natale, M.L. Flottes, et A. Virazel,
Rapport technique intermédiaire, Contrat CT312 MASTER_3D, Programme CEE
CATRENE, Juillet 2014.
P. Girard, S. Bernard, F. Azais, A. Bosio, M. Comte, L. Dilillo, V.
Kerzerho, L. Latorre, M. Renovell et A. Virazel, Rapport technique de
fin d’année, Contrat « ELESIS » n° 296112, Programme CEE ENIAC, Juillet
2014.
P. Girard, B. Rouzeyre, G. Di Natale, M.L. Flottes, et A. Virazel,
Rapport technique de fin d’année, Contrat CT312 MASTER_3D, Programme
CEE CATRENE, Janvier 2015.
P. Girard, B. Rouzeyre, G. Di Natale, M.L. Flottes et A. Virazel,
Rapport technique intermédiaire, Contrat CT312 MASTER_3D, Programme CEE
CATRENE, Juillet 2015.
P. Girard, S. Bernard, F. Azais, A. Bosio, M. Comte, V. Kerzerho, L.
Latorre, M. Renovell et A. Virazel, Rapport technique de fin de projet,
Contrat « ELESIS » n° 296112, Programme CEE ENIAC, Octobre 2015.
P. Girard, B. Rouzeyre, G. Di Natale, M.L. Flottes et A. Virazel,
Rapport technique de fin de projet, Contrat CT312 MASTER_3D, Programme
CEE CATRENE, Janvier 2016.
S. Kaiser, P. Girard, C. Aktouf, C. Chevalier et L. Fesquet, Rapport
technique de fin de projet, Contrat FUI « HiCool », Novembre 2016.
A. Virazel, F. Azais, A. Bosio, G. Di Natale, M.L. Flottes, P. Girard,
et B. Rouzeyre, Rapport technique de fin d’année, Contrat HADES,
Programme CEE PENTA, Juillet 2018.
P. Girard, A. Virazel, A. Bosio, E. Fhaen, A. Ladhar, and H.
Stratigopoulos, Rapport intermédiaire, Contrat EDITSoC, Programme ANR
AAP-2017, Juillet 2019.
A. Virazel, F. Azais, M.L. Flottes, P. Girard, et B. Rouzeyre, Rapport
technique de fin d’année, Contrat HADES, Programme CEE PENTA, Juillet
2019.
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