Patrick Girard  
CNRS Research Director
 
    Research Interests
 
 

My research interests include the various aspects of digital testing and memory testing, with special emphasis on DfT, BIST, diagnosis, delay testing and power-aware testing. Reliability and fault tolerance, power modeling and estimation, as well as design and test of 3D ICs are also part of my (new) research activities. A detailed list of past and current topics investigated as part of my research activities is given below.


Delay Testing and Performance Verification

  • Delay Fault Simulation in Digital Circuits

  • BIST of Delay Faults in Digital Circuits

  • BIST of Delay Faults in FPGAs

  • Signal Integrity -Aware Pattern Generation for Delay Testing and Speed Binning (ongoing)

  • At-Speed Design-for-Test Techniques (ongoing)

BIST and Learning

  • BIST of Digital Circuits by Learning Techniques

Logic Diagnosis

  • Electrical Fault Diagnosis in Logic Cores

  • Diagnosis-Oriented ATPG

  • Diagnosis for Yield Improvement in SoCs (ongoing)

Memory Testing

  • Test and Reliability of Embedded SRAM Memories (ongoing)

  • Test of Low Power SRAM Memories (ongoing)

  • Test and Reliability of Embedded FLASH Memories

  • Test and Reliability of Magnetic RAM (MRAM) Memories (ongoing)

Power-aware Testing and Test Strategies for Low Power Devices

  • Low-Power BIST

  • Power-Aware At-speed Scan Testing

  • Test Strategies for Low-Power Digital Circuits (ongoing)

Power Modeling and Estimation

  • Power Estimation for CPU Cores (ongoing)

  • Circuit and Architectural-Level Power Modeling and Estimation (ongoing)

Reliability and Fault Tolerance

  • Design and Test of Fault-Tolerant Digital Structures (ongoing)

  • Radiation-Induced Effects on Electronic Systems and ICs (ongoing)

Design and Test of 3D ICs

  • Power and Thermal Analysis for 3D Integration (ongoing)

  • Addressing Power and Thermal Issues during Test of 3D ICs (ongoing)