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My
research interests include the various aspects of
digital circuit
and memory testing, with special emphasis on DfT, BIST, diagnosis,
delay testing and power-aware testing. Reliability and fault tolerance of digital ICs,
power modeling and estimation, design and test of 3D ICs, as well as
test and reliability of approximate circuits are (or have been) also
part of my research
activities. Future research activities will
concentrate on DFT for smart image sensors, AI for test and diagnosis
of circuits and systems, and robustness of bio-inspired circuits. A
detailed list
of past and current topics investigated as part of my research
activities is given below.
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Delay Fault Simulation in Digital Circuits
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BIST of Delay Faults in Digital Circuits
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BIST of Delay Faults in FPGAs
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Signal Integrity -Aware Pattern Generation for Delay Testing and Speed Binning
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At-Speed Design-for-Test Techniques for Test Chip Validation
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BIST of Digital Circuits by Learning Techniques
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Learning-Guided Cell-Aware Diagnosis of Automotive Customer Returns (ongoing)
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Characterization of Defective Cell Libraries for Test and Diagnosis (ongoing)
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Test and Reliability of Embedded SRAM Memories
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Test of Low
Power SRAM Memories
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Diagnosis of SRAM Memories (ongoing)
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Test and Reliability of Embedded FLASH Memories
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Test and Reliability of Magnetic RAM (MRAM) Memories
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