| Michel Renovell |
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| FPGA |
Patent on FPGA testing, In Progress. |
| ADConverters |
International Patent on BIST for A to D Converters,
Septembre 99. |
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| 1. M. Renovell |
“Some Aspects of the Test Generation Problem
for an Application-Oriented Test of SRAM-Based FPGAs”,
Invited Paper for the Journal of Circuits, Systems and
Computers, pp. 143-158, vol. 12, n° 2, April 2003,
Word Scientific Publishing Company |
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| 1. M. Renovell |
“From Dependable Computing Systems to Computing
for Integrated Dependable Systems”, Invited Panel,
Fault Tolerant Computing Symposium, FTCS-28, pp. 296-301,
June 23-25, Munich, Germany, 1998. |
| 2. M. Renovell |
“SRAM-Based FPGAs: A Structural Test Approach”,
Invited Paper for IEEE XI Brazilian Symposium on Integrated
Circuit Design SBCCI98, pp. 67-72, Rio de Janeiro, Brazil,
Oct. 98. |
| 3. M. Renovell |
“Testing embedded SRAM-Based FPGAs”, Invited
Paper for IEEE International Conference on Microelectronics,
Aug., Ottawa, Canada, 1999. |
| 4. M. Renovell |
“A specific test methodology for symmetric SRAM-based
FPGAs”, Invited Paper for 10th International Conference
on Field-Programmable Logic and Applications, pp. 300-311,
Villach, Austria, August 27-30, 2000. |
| 5. M. Renovell |
“Different Experiments in Test Generation for
XILINX FPGAs”, Invited Paper for IEEE International
Test Conference ITC’00, pp. 854-862, Atlantic
City, NJ, USA, Oct. 3-5, 2000. |
| 6. M. Renovell |
“Revisiting the Classical Fault Models through
a Detailed Analysis of Realistic Defects”, Invited
Paper for IEEE International Symposium on Quality of
Electronic Design, pp. 359-364, San Jose, USA, 2001. |
| 7. M. Renovell |
“Testing Challenges for Modern FPGAs”,
Invited Paper for the 4th IEEE International Conference
on Electronic Circuits and Systems ECS’03, pp.
1-9, Bratislava, Slovaquia, Sept. 11-12, 2003. |
| 8. M. Renovell |
“Structural Testing of Modern Reconfigurable
Chips”, Invited Paper for the International East-West
Design and Test Conference EWDTC’03, Yalta, Ukrain,
Sept. 18-21, 2003. |
| 9. M. Renovell |
“Principe et Problématique pour le test
des System-On-Chip”, Invited Paper for the International
Conférence sur les Signaux, Circuits et Systèmes
SCS’04, pp. 1-3, Monastir, Tunisie, Mars 18-21,
2004. |
| 10. M. Renovell |
“Realistic Fault Models for Defects in Electronic
Circuits”, Invited Paper for the International
Baltic Electronic Conference BEC’04, pp. 33-37,
Tallin, Estonia, Octobert 4-6, 2004. |
| 11. M. Renovell |
“Fundamentals of System Testing : Challenges
for System-On-Chips”, Invited Paper for the International
Conference on Microelectronics ICM’04, pp. to
appear, Tunis, Tunisia, December 6-8, 2004. |
| 12. M. Renovell |
“Modelization and Detection of Realistic Defects
in CMOS Technology”, Invited Paper for the International
East-West Design and Test Conference EWDTC’05,
Odessa, Ukrain, Sept. 15-19, 2005. |
| 13. M. Renovell |
“Testing for Realistic Defects”, Invited
Paper for the International Conference on Computer Science
and Information Technology CSIT’05, Yerevan, Armenia,
Sept. 19-22, 2005. |
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| 1. F. Azais |
S. Bernard, Y. Bertrand, M. Renovell, “On-Chip
Generator of a Saw-Tooth Test Stimulus for ADC BIST”,
Selected papers from the 11th International Conference
on Very Large Scale Integration of Systems-on-Chip,
Kluwer Academic Publishers, ISBN: 1-4020-7148-5, pp.
425-436, 2002. |
| 1. F. Azais |
P. Nouet, M. Renovell, “Mixed-Signal Test Standards
”, One Chapter in the book ‘Test and Design
for Testability in Mixed Signal Integrated Circuits’,
october 2003, Kluwer Academic Publishers. |
| 3. M. Renovell |
En collaboration avec Azais, S. Bernard, Y. Bertrand,
M.L. Flottes, P. Girard, C. Landrault, B. Rouzeyre,
S. Pravossoudovitch, “Test de Circuits et Systèmes
Intégrés”, auteur d’un chapitre,
Hermes Science publications, ISBN 2-7462-0864-4, 2004. |
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| 1. M. Renovell |
G. Cambon, D. Auvergne, "FSPICE: A tool for fault
modeling in MOS circuits", Integration the VLSI
journal 3, pp. 245-255, 1985. |
| 2. M. Renovell |
G. Cambon, "Topology dependence of floating gate
faults in MOS integrated circuits", IEE Electronics
Letters, vol. 22, no 3, pp. 152-153, Jan. 1986. |
| 3. M. Renovell |
G. Cambon, “Electrical analysis and modeling
of Floating-Gate Fault", IEEE Transactions on CAD
of ICs and Sys, Vol. 11, no 11, Nov. 1992, pp. 1450-1458 |
| 4. M. Renovell |
P. Huc, Y. Bertrand, “Realistic fault model
for External Shorts in MOS Technologies", IEE Electronics
Letters, Vol. 29, no 9, pp. 813-814, April 1993. |
| 5. M. Renovell |
J. Figueras, “Current Testing in Dynamic CMOS
Circuits", Jour. of Electr. Testing : Theory and
Application (JETTA), Kluwer Academic Publisher, Vol.
6, no. 1, pp. 127-131, Feb. 1995. |
| 6. S. Lavabre |
Y. Bertrand, M. Renovell, C. Landrault, “Testability
Improvements of Sequential Circuits by Emulation of
Test Configurations", Journal of Solid State Devices
and Circuits, Vol. 4, n°1, Jan. 1996, pp. 32-38. |
| 7. M. Renovell |
F. Azais, Y. Bertrand, “On-Chip Signature Analyzer
for Analogue Circuit Testing", IEE Electronics
Letters, vol. 32, no 24, pp. 2185-2186, September 1996. |
| 8. M. Renovell |
J.M. Portal, J. Figueras, Y. Zorian, “Testing
the Interconnect Structure of RAM-Based FPGA",
IEEE Design & Test, Vol. 15, n°1, pp.45-50,
January-March 1998. |
| 9. M. Renovell |
J.M. Portal, J. Figueras, Y. Zorian, “SRAM-based
FPGA: Testing the Embedded RAM Modules“, Journal
of Electr. Testing: Theory and Application (JETTA),
Kluwer Academic Publisher, pp. 159-167, Vol. 14, n°1/2,
Jan./Fev. 99. |
| 10. M. Renovell |
F. Azais, Y. Bertrand, “Detection of Defects
Using Fault Model Oriented Test Sequences“, Journal
of Electr. Testing: Theory and Application (JETTA),
Kluwer Academic Publisher, pp. 13-22, Vol. 14, n°1/2,
Jan./Fev. 99. |
| 11. M. Renovell |
F. Azais, J-C Bodin, Y. Bertrand, “Combining
Functional and Structural Approaches for Switched-Current
Circuit Testing“, Journal of Electr. Testing:
Theory and Application (JETTA), Kluwer Academic Publisher,
2000. |
| 12. M. Renovell |
J.M. Portal, J. Figueras, Y. Zorian, “Testing
the Local Interconnect Resources of SRAM-based FPGAs“,
Journal of Electr. Testing: Theory and Application (JETTA),
Kluwer Academic Publisher, 2000. |
| 13. M. Renovell |
J.M. Portal, J. Figueras, Y. Zorian, “An Approach
to Minimize the Test Configurations for the Logic Cells
of the XILINX XC4000 FPGA Family“, Journal of
Electr. Testing: Theory and Application (JETTA), Kluwer
Academic Publisher, 2000. |
| 14. F. Azais |
M. Renovell, Y. Bertrand, A. Ivanov, S. Tabatabaei,
“PLL Testing: A Unified Digital Test Approach“,
IEEE Design & Test, 2000. |
| 15. M. Renovell |
F. Azais, Y. Bertrand, “Analyzing Some Cases
of Test Escapes“, IEEE Design & Test, 2000. |
| 16. A. Ivanov |
S. Rafiq, M. Renovell, F. Azais, Y. Bertrand, “
On the detectability of CMOS floating gates transistor
faults“, IEEE Transactions on CAD, Vol. 20, n°
1, January 2001, pp. 116-128. |
| 17. F. Azais |
S. Bernard, Y. Bertrand, M. Renovell, “A low-cost
BIST architecture for linear histogram testing of ADCs“,
Journal of Electronic Testing (JETTA), Kluwer Academic
Publisher, Vol. 17, n° 2, April 2001, pp. 139-147. |
| 18. F. Azais |
S. Bernard, Y. Bertrand, M. Renovell, “Optimizing
sinusoidal histogram test for low cost ADC BIST“,
Journal of Electronic Testing (JETTA), Kluwer Academic
Publisher, Vol. 17, n° 3/4, June/August 2001, pp.
255-266. |
| 19. M. Renovell |
J.M. Portal, P. Faure, J. Figueras, Y. Zorian, “A
discussion on test pattern generation for FPGA - Implementated
circuits “, Journal of Electronic Testing (JETTA),
Kluwer Academic Publisher, Vol. 17, n° 3/4, June/August
2001, pp. 283-290. |
| 20. F. Azais |
S. Bernard, Y. Bertrand, M. Renovell, “Analog
Built-In Saw-Tooth Generator for ADC Histogram Test“,
Microelectronics Journal (MEJO), Elsevier Sciences,
Vol. 33, Issue 10, pp. 781-789, Oct. 2002. |
| 21. F. Azais |
S. Bernard, Y. Bertrand, M. Comte, M. Renovell, “A-to-D
Converters Static Errors Detection from Dynamic Parameters
Measurement“, Microelectronics Journal (MEJO),
Elsevier Science, vol. 34, n°10, pp.945-953, 2003. |
| 22. F. Azais |
Y. Bertrand, M. Renovell, A. Ivanov, S. Tabatabataei,
“An all Digital DFT Scheme for testing catastrophic
faults in PLL“, IEEE Design & Test of Computer,
Vol. 20, Issue 1, pp. 60-67, Jan-Feb. 2003. |
| 23. F . Azais |
S. Bernard, M. Comte, Y. Bertrand, M. Renovell and
M. Lubazewski, “Estimating Static Parameters of
A-to-D Converters from Spectral Analysis ”, Accepted
to appear in Journal of Electronic Testing (JETTA),
Kluwer Academic Publisher, 2003. |
| 24. S. Bernard |
F. Azais, Y. Bertrand, M. Renovell, “On-chip
Generation of Ramp and Triangle –Wave Stimuli
for ADC BIST”, Journal of Electronic Testing (JETTA),
Kluwer Academic Publisher, vol. 19, n°4, pp. 469-479,
August 2003. |
| 25. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Modelling
the Random Parameters Effects in a Non-Split Model of
Gate Oxide Short”, Journal of Electronic Testing
(JETTA), Kluwer Academic Publisher, Vol. 19, n°4,
August 2003, pp. 377-386. |
| 26. I. Polian |
P. Engelke, M. Renovell, and B. Becker, “Modeling
Feedback Bridging Faults with non-zero Resistance”,
Accepted to appear in Journal of Electronic Testing
(JETTA), Kluwer Academic Publisher, 2004. |
| 27. S. Bernard |
M. Comte, F. Azais, Y. Bertrand, M. Renovell, “Efficiency
of Spectral-based ADC Test Flows to Detect Static Errors”,
Journal of Electronic Testing (JETTA), Kluwer Academic
Publisher, vol. 20, n°3, pp. 257-267, June 2004. |
| 28. F. Azais |
S. Bernard, M. Comte, Y. Bertrand, M. Renovell, M.
Lubaszewski, “Correlation between Static and Dynamic
Parameters of A-to-D Converters in the viewof a Unique
Test Procedure”, Journal of Electronic Testing
(JETTA), Kluwer Academic Publisher, vol. 20, n°4,
pp. 375-387, August 2004. |
| 29. A. Gonzales |
M. Lubaszewski, L. Carro and M. Renovell, “A
New FPGA for DSP Applications Integrating BIST Capabilities”,
Journal of Electronic Testing (JETTA), Kluwer Academic
Publisher, vol. 20, n°4, pp. 423-431, August 2004. |
| 30. R. Bouchakour |
J.M. Portal, J.M. Galliere, F. Azais, Y. Bertrand,
, M. Renovell, “A Compact DC Model of Gate Oxide
Short Defect”, Microelectronic Engineering, Vol.
72, 1-4, pp. 140-148, 2004. |
| 31. F. Azais |
S. Bernard, M. Comte, Y. Bertrand, M. Renovell, “Efficiency
of Optimized Dynamic Test Flows for ADCs: Sensitivity
to Specifications”, Journal of Electronic Testing:
Theory and Applications (JETTA), Kluwer Academic Publisher,
vol. 21, n°3, pp. 291-298, December 2004. |
| 32. F. Azais |
M. Lubaszewski, P. Nouet, M. Renovell, “A Strategy
for Optimal Point Insertion In Analog Cascaded Filters”,
Journal of Electronic Testing (JETTA), Kluwer Academic
Publisher, vol. 21, n°1, pp. 9-16, 2005. |
| 33. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Delay
Testing Viability of MOS Transistors with Gate Oxide
Shorts”, Journal of Computer Science and Technology,
Vol. 20, n°2, pp. 195-200, 2005. |
| 34. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “Delay
Fault Testing of Look-Up Tables in SRAM-Based FPGAs”,
Journal of Electronic Testing (JETTA), Kluwer Academic
Publisher, vol. 21, n°1, pp. 43-55, 2005. |
| 35.T.R. Balen |
A. Andrade, F. Azais, M. Lubaszewski, M. Renovell,
“Applying the Oscillation Test Strategy to FPAA’s
Configurable Analog Blocks", Journal of Electronic
Testing (JETTA), Kluwer Academic Publisher, vol. 21,
n°2, pp. 135-146, 2005. |
| 36. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “An
Efficient BIST Architecture for Delay Faults in the
Logic Cells of Symmetrical SRAM-Based FPGAs”,
Journal of Electronic Testing (JETTA), Kluwer Academic
Publisher, vol. 22, n°2, pp. 161-172, April 2006. |
| |
|
| 1. M. Renovell |
G. Cambon, D. Auvergne, "Modeling and electrical
simulation of faults in MOS integrated circuits",
Intern. Conf.on CAD, pp. 89-92, Paris, Jun.1985. |
| 2. M. Renovell |
P. Faure, G. Cambon, "Mask dependent models of
faults in MOS integrated circuits", IC Technology
Conf., Limerick, Eire, pp. 125-134, September 1986. |
| 3. M. Renovell |
P. Faure, G. Cambon, "Modélisation logique
des grilles flottantes dans les technologies MOS",
3rd Intern. Conf. QEC, pp. 29-34, Bordeaux, March 1987. |
| 4. A. Elleuch |
M. Renovell, J. Lassalle, G. Cambon, "Méthodologie
et outil d'extraction automatique des sites de pannes",
Intern. Conf. on Microele, Alger, Nov. 1988. |
| 5. A. Elleuch |
M. Renovell, J. Lassale, G. Cambon, "Transistor
à grille flottante : Modélisation logique
de pannes dépendantes de la topologie",
International Conference on Microelectronics 88, Alger,
novembre 1988. |
| 6. M. Renovell |
S. Rayon, Y. Bertrand, G. Cambon, "Testability
Design for PLA-Implemented FSM", 1st European Test
Conf. (ETC), pp. 246-251, Paris, Ap. 1989. |
| 7. M. Renovell |
A. Elleuch, J. Lassale, G. Cambon, "Automatic
Extraction and Modelisation of Layout Dependent Faults",
12th Fault-Tolerant Systems and Diagnosis Conference,
Prague, Tchécoslovaquie, pp. 96-100, Septembre
1989. |
| 8. M. Renovell |
G. Cambon, A. Elleuch, J. Lassale, "Computer
Aided Location and Model Analysis of Faults in MOS Integrated
Circuits", ISSSE'89 International Symposium on
Signals Systems and Electronics, Erlangen RFA, pp. 609-612,
Sept. 89. |
| 9. M. Renovell |
S. Rayon, Y. Bertrand, G. Cambon, "Short Fault
in Dynamic CMOS PLA", 13th Fault Tolerant Syst.
and Diagnosis Conf., Varna, Bulgarie, June 1990. |
| 10. M. Renovell |
M. Ildevert, Y. Bertrand, “Autonomously testable
dynamic CMOS PLAs", Europ. Test Conf. ETC'91, Munich,
RFA, April 10-12, 1991, p. 519. |
| 11. M. Renovell |
M. Ildevert, Y. Bertrand, “DCPLA : A new BIST
design for dynamic CMOS PLAs", International Test
Conf., Nashville, TN, USA, Oct. 28-31, 1991. |
| 12. M. Renovell |
M. Ildevert, Y. Bertrand, “A low overhead BIST
scheme for dynamic CMOS PLAs", Int. Conf. on VLSI
Design, India, jan. 1992, pp. 352-355. |
| 13. C. Counil |
M. Renovell, G. Cambon, “Self-Test for F.I.R.filters",VLSI
Signal Processing V, Edited by K. Yao, R. Jain, W. Przytula,
IEEE 1992, pp. 51-60. |
| 14. C. Counil |
M. Renovell, G. Cambon, “BIST for mixed signal
analog/digital circuits", Int. Symp. on Signals,
Syst and Elect., Paris, 1-3 September 1992, pp. 958-961. |
| 15. Y. Bertrand |
F. Bancel, M. Renovell, “A DFT Technique to
improve ATPG efficiency for seq. cir.", Int.Conf.
on VLSI Des., Bombay, India, Jan. 1993, pp. 51-54. |
| 16. Y. Bertrand |
F. Bancel, M. Renovell, “A new DFT Tech. to
reduce test duration for seq. circ.", Eur. Test
Conf., Rotterdam, Netherland, Ap. 21-23, 1993, pp. 489. |
| 17. Y. Bertrand |
F. Bancel, M. Renovell, “Multiconfiguration
Tech to reduce test duration for seq. cir.", Int.
Test Conf., Nashville, USA, October 1993, pp. 989-997. |
| 18. M. Renovell |
P. Huc, Y. Bertrand, “Fault Modelisation of
External Shorts in CMOS Circuits“, Asian Test
Symposium, Nov.17-18, Pekin, China, 1993, pp. 237-242. |
| 19. M. Renovell |
P. Huc, Y. Bertrand, “CMOS Bridging Fault Modeling",
IEEE 12th VLSI Test Symposium, April, New Jersey, USA,
1994, pp. 392-397. |
| 20. M. Renovell |
P. Huc, Y. Bertrand, “The configuration ratio:
a model for simulating CMOS intra-gate bridge with variable
logic thresholds“, 1st European Dependable Computing
Conference EDCC, Oct., Berlin, Germany, 1994, pp. 165-177. |
| 21. M. Renovell |
P. Huc, Y. Bertrand, “A Unified Model for Inter-gate
and Intra-gate CMOS Bridging Fault : The Configuration
Ratio", 3rd Asian Test Symposium, November, Nara,
Japan, 1994, pp. 170-174. |
| 22. M. Renovell |
P. Huc, Y. Bertrand, “The Concept of Resistance
Interval: A New Parametric Model for Realistic Resistive
Bridging Fault", IEEE 13th VLSI Test Symposium,
April 30-May 3, New Jersey, USA, 1995, pp. 184-189. |
| 23. S. Lavabre |
Y. Bertrand, M. Renovell, C. Landrault, “Testability
Improvements of Sequential Circuits by Emulation of
Test Configurations", X SBMICRO’95, 10th
Congress of the Brazilian Microelectronics Society,
Canela, RS-Brazil, July 31 August 4, 1995, pp. 281-289. |
| 24. S. Lavabre |
Y. Bertrand, M. Renovell, C. Landrault, “Test
Configurations to Enhance Testability of Sequential
Circuits ", ATS’95, 4th Asian Test Symposium,
pp. 160-168, Nov. 23-24, Bangalore, India, 1995. |
| 25. M. Renovell |
P. Huc, Y. Bertrand, “Serial Transistor Network
Modeling for Bridging Fault Simulation", ATS’95,
4th Asian Test Symposium, pp. 100-106, Nov. 23-24, Bangalore,
India, 1995. |
| 26. M. Renovell |
F. Azais, Y. Bertrand, “A Design-For-Test Technique
for Multi-Stage Analog Circuits", ATS’95,
4th Asian Test Symposium, pp. 113-119, Nov. 23-24, Bangalore,
India, 1995. |
| 27. M. Renovell |
P. Huc, Y. Bertrand, “Bridging Fault Coverage
Improvement by Power Supply Control", IEEE 14th
VLSI Test Symposium, April 28-May 1, New Jersey, USA,
1996, pp. 338-343. |
| 28. M. Renovell |
F. Azais, Y. Bertrand, “ The Multi-Configuration
: A DFT Technique for Analog Circuits", IEEE 14th
VLSI Test Symposium, April 28-May 1, New Jersey, USA,
1996, pp. 54-59. |
| 29. F. Azais |
M. Renovell, Y. Bertrand, “A Switched-Capacitor
Filter with DFT Facilities", Design of Integrated
Circuits and Systems, pp. 130-135, Nov. 20 - 22, Barcelone,
Espagne, 1996. |
| 30. M. Renovell |
P. Huc, Y. Bertrand, “The logic Threshold Based
Voting : A Mode for Local Feedback Bridging Fault",
2nd European Dependable Computing Conference EDCC, pp.
205-213, October 2-4, Taormina, Italy, 1996. |
| 31. M. Renovell |
F. Azais, Y. Bertrand, “On-Chip Analog Output
Response Compaction", IEEE European Design and
Test Conference, pp. 568-572, March 18-20, Paris, France,
1997. |
| 32. M. Renovell |
J. Figueras, Y. Zorian, “Test of RAM-Based FPGA:
Methodology and Application to the Interconnect",
IEEE 15th VLSI Test Symposium, pp. 230-237, April 28-30,
Monterey, CA, USA, 1997. |
| 33. M. Renovell |
M. Lubaszewski, S. Mir, F. Azais, Y. Bertrand, “A
Multi-Mode Signature Analyzer for Analog and Mixed Circuits“
, IX IFIP International Conference on VLSI, pp. 65-76,
August 27-29, Gramado, Brazil, 1997. |
| 34. M. Renovell |
Y. Bertrand, F. Azais, “Test Strategy Sensitivity
to Floating Gate Fault Parameter", IEEE International
Conference on Innovative System In Silicon ISIS97, pp.
186-195, Oct. 8-10, Austin, Texas, USA, 1997. |
| 35. M. Renovell |
Y. Bertrand, “Test Strategy Sensitivity to Defect
Parameter", IEEE International Test Conference
ITC97, pp. 607-616, Nov. 3-5, Washington, USA, 1997. |
| 36. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “Test
Pattern and Test Generation Methodology for the Logic
of RAM-Based FPGA”, IEEE Asian Test Symposium
ATS97, pp. 254-259, Akita, Japan, Nov. 1997. |
| 37. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “A Specific
Test Pattern Generation Methodology for RAM-Based FPGA
Logic Modules”, XII Design of Circuits and Integrated
Systems Conference, pp. 213-218, Sevilla, Spain, Nov.
1997. |
| 38. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “Testing
the Configurable Logic of RAM-based FPGA”, IEEE
Int. Conf. on Design, Automation and Test in Europe
DATE98, pp. 82-88, Feb. 23-26, Paris, France, 1998. |
| 39. M. Renovell |
F. Azais, Y. Bertrand, “Optimized Implementations
of the Multi-Configuration DFT Technique for Analog
and Mixed Signal Circuits", IEEE Int. Conf. on
Design, Automation and Test in Europe, pp. 815-821,
Feb. 23-26, Paris, France, 1998. |
| 40. M. Renovell |
F. Azais, J.C. Bodin, Y. Bertrand, “Design For
Testability for Switch Current Circuits", IEEE
16th VLSI Test Symposium, pp. 370-375, April 26-30,
Monterey, CA, USA, 1998. |
| 41. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “SRAM-based
FPGA: A Fault Model for the Configurable Logic Modules”,
Field Programmable logic and Applications Conference
FPL98, Lectures Notes in Computer Science 1482, pp.
139-148, Tallin, Estonia, Oct. 1998. |
| 42. M. Lubaszewski |
M. Renovell, S. Mir, F. Azais, Y. Bertrand, “A
Built-In Multi-Mode Stimuli Generator for Analog and
Mixed-Signal Testing“ , IEEE XI Brazilian Symposium
on Integrated Circuit Design, pp. 175-178, Rio de Janeiro,
Brazil, Oct. 98. |
| 43. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “SRAM-based
FPGA: Testing the LUT/RAM Modules”, IEEE International
Test Conference ITC98, pp. 1102-1111, Washington, DC,
USA, Oct. 18-23, 1998. |
| 44. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “SRAM-based
FPGAs: A Fault Model for the Multiplexer-Based Logic
Modules”, XIII Design of Circuits and Integrated
Systems Conference DCIS98, pp. 182-187, Nov. 17-20,
Madrid, Spain, 1998. |
| 45. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “SRAM-based
FPGA: Testing the Logic-Interconnect/Logic Interface”,
IEEE 7th Asian Test Symposium ATS98, pp. 266-271, Dec.
2-4, Singapore, 1998. |
| 46. S. Rafiq |
A. Ivanov, S. Tabatabaei, M. Renovell, “Testing
for Floating Gate Defects in CMOS Circuits”, IEEE
7th Asian Test Symposium ATS98, pp. 228-236, Dec. 2-4,
Singapore, 1998. |
| 47. M. Renovell |
F. Azais, J.C. Bodin, Y. Bertrand, “BISTing
Switched-Current Circuits", IEEE 7th Asian Test
Symposium ATS98, pp. 372-377, December 2-4, Singapore,
1998. |
| 48. F. Azais |
A. Ivanov, M. Renovell and Y. Bertrand, “A Methodology
and Design for Effective Testing of Voltage-Controlled
Oscillators (VCOs)", IEEE 7th Asian Test Symposium
ATS98, pp. 383-387, Dec. 2-4, Singapore, 1998. |
| 49. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “Testing
the Configurable Interconnect/Logic Interface of SRAM-Based
FPGA’s ”, IEEE Int. Conf. on Design, Autom.
and Test in Europe DATE99, pp. 618-622, March 10-12,
Munich, Germany, 99. |
| 50. M. Renovell |
F. Azais, Y. Bertrand, A. Ivanov, “Optimal Conditions
for Static Detection of Floating Gate Faults",
IEEE International Test Conference ITC99, pp. 477-486,
Atlantic City, NJ, USA, Sept. 27-30, 1999. |
| 51. M. Renovell |
F. Azais, Y. Bertrand, “Test Escapes : Analysis
of Short Defects”, IEEE XII Brazilian Symposium
on Integrated Circuit Design SBCCI99, pp. 160-163, Natal,
Rio Grande do Norte, Brazil, Sept. 29-Oct. 2, 1999. |
| 52. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “SRAM-Based
FPGAs: Logic Cell Test Configuration Minimization ”,
XIV Design of Circuits and Integrated Systems Conference
DCIS99, pp. 307-312, Nov. 16-19, Palma de Mallorca,
Spain, 99. |
| 53. M. Renovell |
F. Azais, J.C. Bodin, Y. Bertrand, “A New Test
Scheme for Switched-Current Circuits", XIV Design
of Circuits and Integrated Systems Conference DCIS99,
pp. 95-100, Nov. 16-19, Palma de Mallorca, Spain, 1999. |
| 54. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “Minimizing
the Number of Test Configurations for different FPGA
Families”, IEEE 8th Asian Test Symposium ATS99,
pp. 363-368, Nov. 16-18, Shanghai, China, 1999. |
| 55. E. Cota |
M. Renovell, M. Lubaszewski, L. Carro, F. Azais, Y.
Bertrand, “Reuse of Existing Ressources for analog
BIST of a switch capacitor filter", IEEE Int. Conf.
on Design, Automation and Test in Europe DATE2000, pp.
226-230, March 27-30, Paris, France, 2000. |
| 56. M. Renovell |
F. Azais, S. Bernard, Y. Bertrand, “Hardware
Ressource Minimization for an Histogram-Based ADC BIST",18th
IEEE VLSI Test Symposium, pp. 247-252, May 2-4, Montreal,
Canada, 2000. |
| 57. M. Renovell |
J.M. Portal, P. Faure, J. Figueras and Y. Zorian,
“ Some experiments in test pattern generation
for FPGA-implemented combinational circuits”,
IEEE XII Brazilian Symposium on Integrated Circuit Design
SBCCI’00, pp. 3-8, Manaus, Brazil, September 18-24,
2000. |
| 58. M. Renovell |
J.M. Portal, P. Faure, J. Figueras and Y. Zorian,
“Test generation optimization for a FPGA application-oriented
test procedure”, XV Design of Circuits and Integrated
Systems Conference DCIS’00, pp. 330-336, Nov.
21-24, Montpellier, France, 2000. |
| 59. F. Azais |
S. Bernard, Y. Bertrand, M. Renovell, “ Sinusoidal
histogram-based BIST for ADC testing", XV Design
of Circuits and Integrated Systems Conference DCIS’00,
pp. 96-101, Nov. 21-24, Montpellier, France, 2000. |
| 60. L. Carro |
L. Carro, E. Cota, M. Lubaszewski, Y. Bertrand, F.
Azais, M. Renovell, “ TI-BIST : A temperature
independant analog BIST for switched-capacitor filters",
IEEE 9th Asian Test Symposium ATS’00, pp. 77-83,
Dec. 4-6, Taipei, Taiwan, 2000. |
| 61. M. Renovell |
J.M. Portal, P. Faure, J. Figueras and Y. Zorian,
“TOF: A tool for test pattern generation optimization
of an FPGA application-oriented test”, IEEE 9th
Asian Test Symposium ATS’00, pp. 323-328, Dec.
4-6, Taipei, Taiwan, 2000. |
| 62. F. Azais |
S. Bernard, Y. Bertrand, M. Renovell, “On-chip
generation of high-quality ramp stimulus with minimal
silicon area”, LATW'01 : 2nd IEEE Latin American
Test Workshop, Cancun, Mexico, February, 11-14, 2001,
pp. 112-117. |
| 63. F. Azais |
S. Bernard, Y. Bertrand, M. Renovell, “Implementation
of a Linear Histogram BIST for ADCs”, Design Automation
and Test in Europe DATE2001, pp. 590-595, Mar. 13-16,
Munich, Germany, 2001. |
| 64. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Analysing
the Characteristics of MOS Transistors in the Presence
of Gate Oxide Shorts”, IEEE Design and Diagnostics
of Electronic Circuits and Systems Workshop DDECS01,
pp. 155-161, Apr. 18-20, Gyor, Hungary, 2001. |
| 65. F. Azais |
S. Bernard, Y. Bertrand, X. Michel, M. Renovell, “A
Low Cost Adaptative Ramp Generator for Analog BIST Applications”,
IEEE VLSI Test Symposium, pp. 266-271, Apr. 29- May
3, Marina del Rey, California, USA, 2001. |
| 66. S. Bernard |
F. Azais, Y. Bertrand, M. Renovell, “ Analog
BIST generator for ADC testing”, DFT'01: IEEE
International Symposium on Defect and Fault Tolerance
in VLSI Systems, San Francisco, USA, October 24-26,
2001, pp. 338-346 |
| 67. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Boolean
and Current Detection of MOS Transistor with Gate Oxide
Short”, IEEE International Test Conference ITC’01,
pp. 1039-1048, Oct. 29-31, Baltimore, USA, 2001. |
| 68. M. Renovell |
P. Faure, J.M. Portal, J. Figueras, Y. Zorian, “IS-FPGA:
A New Symmetric FPGA Architecture with Implicit Scan”,
IEEE International Test Conference ITC’01, pp.
924-931, Oct. 29-31, Baltimore, USA, 2001. |
| 69. F. Azais |
S. Bernard, Y. Bertrand, M. Renovell, “On Chip
generator of a Saw-Tooth Test Stimulus for ADC BIST”,
VLSI-soc'01 : 11th IFIP International Conference on
Very Large Scale Integration, Montpellier, France, December
3-5, pp 347-352, 2001. |
| 70. M. Renovell |
F. Azais, Y. Bertrand, “A Design-For-Test Technique
for Multi-Stage Analog Circuits", Compendium of
the Best papers of ATS 1992-2001, pp. 126-132, Nov.
2001, Kyoto, Japan, 2001. |
| 71. M. Renovell |
P. Faure, P. Prinetto, Y. Zorian, “Testing the
Unidimensional Interconnect Architecture of SRAM-Based
FPGAs”, IEEE International Workshop on Electronic
Design Test and Applications, pp. 297-301, Jan. 29-31,
Christchurch, New Zealand, 2002. |
| 72. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Low Voltage
Testing of Gate Oxide Shorts in MOS Technology”,
IEEE Design and Diagnostics of Electronic Circuits and
Systems Workshop DDECS02, pp. 168-174, Apr. 17-19, Brno,
Czech Republic, 2002. |
| 73. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “A Non-Split
Model for Realistic Gate Oxide Short in CMOS Technology”,
Design of Circuits and Integrated Systems Conference
DCIS’02, pp. 197-204, Nov. 19-22, Santander, Spain,
2002. |
| 74. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “Timing
Defect Analysis in Look-Up Tables of SRAM-Based FPGAs”,
IEEE Latin American Test Workshop Formal Proceedings,
LATW’03, pp. 26-31, Feb 16-19, Porto-Alegre, Brazil,
2003. |
| 75. I. Polian |
P. Engelke, M. Renovell, and B. Becker, “Modeling
Feedback Bridging Faults with non-zero Resistance”,
IEEE European Test Workshop Formal Proceedings, ETW’03,
pp. -, May 25-28, Maastritch, Netherland, 2003. |
| 76. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “Requirements
for Delay Testing of Look-Up Tables in SRAM-Based FPGAs”,
IEEE European Test Workshop Formal Proceedings, ETW’03,
pp. 147-152, May 25-28, Maastritch, Netherland, 2003. |
| 77. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “Defect
Analysis for Delay-Fault BIST in FPGAs”, IEEE
International On-Line Testing Symposium, pp. 124-128,
Jul. 7-9, Kos, Greece, 2003. |
| 78. S. Bernard |
M. Comte, F. Azais, Y. Bertrand, M. Renovell, “A
New Methodology for ADC Test Flow Optimization",
IEEE International Test Conference ITC’03, pp.
201-209, Oct. 29-02, Charlotte, USA, 2003. |
| 79. P. Engelke |
I. Polian, M. Renovell, and B. Becker, “Simulating
Resistive Bridging and Stuck-at Faults”, IEEE
International Test Conference ITC’03, pp. 1051-1059,
Oct. 29-02, Charlotte, USA, 2003. |
| 80. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Delay
Testing of MOS Transistors with Gate Oxide Shorts”,
IEEE 12th Asian Test Symposium ATS’03, pp. XX-XX,
Nov. 17-19, Xian, China, 2003. |
| 81. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “High
Quality TPG for Delay Faults in Look-Up Tables of FPGAs”,
IEEE International Workshop on Electrical Design Test
and Applications, pp. -, Jan. 28-30, Perth, Australia,
2004. |
| 82. P. Engelke |
I. Polian, M. Renovell, B. Seshadri, and B. Becker,
“The pros and cons of Very-Low-Voltage Testing
: an Analysis Based on Resistive Bridging Faults”,
IEEE VLSI Test Symposium, pp. 171-178, Napa Valley,
California, USA, April 25-29, 2004. |
| 83. T.R. Balen |
A. Andrade, F. Azais, M. Lubaszewski, M. Renovell,
“An Approach to the Built-In-Self-Test of Field
Programmable Analog Arrays”, IEEE VLSI Test Symposium,
VTS’04, pp. 383-388, Napa Valley, California,
USA, April 25-29, 2004. |
| 84. M.B. Tahoori |
Mc. Cluskey, M. Renovell, P. Faure, “A Multi-Configuration
Strategy for an Application-Dependent Testing of FPGAs”,
IEEE VLSI Test Symposium, VTS’04, pp. 154-159,
Napa Valley, California, USA, April 25-29, 2004. |
| 85. P. Engelke |
I. Polian, M. Renovell, B. Seshadri, and B. Becker,
“Automatic Test Pattern Generation of Resistive
Bridging Faults”, IEEE European Test Symposium,
ETS’04, pp. -, May 24-26, Ajaccio, France, 2004. |
| 86. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “Manufacturing-Oriented
Testing of Delay Faults in the Logic Architecture of
Symmetrical FPGAs”, IEEE European Test Symposium,
ETS’04, pp. 117-122, May 24-26, Ajaccio, France,
2004. |
| 87. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “BIST
of Delay Faults in the Logic Architecture of Symmetrical
FPGAs”, IEEE International On-Line Testing Symposium,
pp. 187-192, Jul. 12-14, Madeira Island, Portugal, 2004. |
| 88. D. Hely |
M.L. Flottes, F. Bancel, B. Rouzeyre, N. Bérard,
M. Renovell, “Scan Design and Secure Chip”,
IEEE International On-Line Testing Symposium, pp. 219-224,
Jul. 12-14, Madeira Island, Portugal, 2004 |
| 89.T.R. Balen |
A. Andrade, F. Azais, M. Lubaszewski, M. Renovell,
“Testing the Configurable Analog Blocks of Field
Programmable Analog Arrays", International Test
Conference, pp. 893-902, 2004 |
| 90. A. Zenteno |
V.H. Champac, M. Renovell, F. Azais, “Analysis
and Attenuation Proposal in Ground Bounce”, IEEE
13th Asian Test Symposium ATS’04, pp. 460-463,
Taiwan, 2004. |
| 91. M. Renovell |
S. Tanguy, “A Set of Test Configurations for
the Global Routing of Hierarchical SRAM-Based FPGAs”,
IEEE Design and Diagnostics of Electronic Circuits and
Systems Workshop DDECS05, pp. 47-54, Apr. 13-16, Sopron,
Hungary, 2005. |
| 92. M. Comte |
S. Ohtake, H. Fujiwara, M. Renovell, “Electrical
Behavior of Gate-Oxide-Short in Domino Logic",
IEEE Design and Diagnostics of Electronic Circuits and
Systems Workshop DDECS05, pp. 210-215, Apr. 13-16, Sopron,
Hungary, 2005. |
| 93. I. Polian |
S. Kundu, J.M. Galliere, P. Engelke, M. Renovell,
and B. Becker, “Resistive Bridge Fault Model Evolution
from Conventional to Ultra Deep Sub-Micron Technologies”,
IEEE VLSI Test Symposium, VTS’05, pp. 343-348,
Palm Springs, California, USA, 2005. |
| 94. G. Pereira |
A. Andrade, T.R. Balen, M. Lubaszewski, F. Azais,
M. Renovell, “ Testing the Interconnect Networks
and I/O Ressources of Field Programmable Analog Arrays",
IEEE VLSI Test Symposium, VTS’05, pp. 389-400,
Palm Springs, California, USA, 2005. |
| |
|
| 1. G. Cambon |
Guiraudou, Landrault, Tabusse, Renovell, "Fault
modeling in MOS Technology", 3rd European Design
For Test Workshop, Timmendorfer, Germany, June 1985. |
| 2. M. Renovell |
G. Cambon, "BIST for Finite state machine implemented
in dynamic CMOS technology", BIST workshop IEEE
Test Technology, Charleston USA, March 1988. |
| 3. M. Renovell |
"Design for Testability for Finite State Machine",
ESPRIT CAVE workshop (CEE), Sintra, Portugal, May 1988. |
| 4. Y. Bertrand |
M. Renovell, S. Rayon, G. Cambon, "Bridging Fault
Modell. and DFT in Dynamic CMOS PLA", 7th European
DFT Workshop, Ségovia, June 18-21, 1990. |
| 5. M. Renovell |
M. Ildevert, Y. Bertrand, "A New Built-In Self
Test Dynamic CMOS PLA Design", 16th ESPRIT CAVE
Workshop, Gent, Belgium, 2-5 december, 1990. |
| 6. Y. Bertrand |
M. Ildevert, M. Renovell, “A design for Dynamic
CMOS PLA with Autonomous Test Facilities", 14th
IEEE Workshop on DFT, Vail, U.S.A., April 16-19, 1991. |
| 7. M. Renovell |
P. Huc, Y. Bertrand, “Bridging Fault Modelling
in CMOS Technology", 1st ARCHIMEDES Workshop on
Analysis-Realistic Testability Evaluation, Lisboa, Portugal,
February, 1993. |
| 8. M. Renovell |
P. Huc, Y. Bertrand, “A Fault Model for Feedback
and Non-Feddback Bridging Fault in CMOS and BiCMOS Technology",
2nd ARCHIMEDES Workshop on Analysis-Realistic Testability
Evaluation, Hannover, Germany, June, 93. |
| 9. M. Renovell |
J. Figueras, “Current Test Viability in Dyn
CMOS Circ", Int. Workshop on Defect and Fault Tol.
in VLSI Systems, October 27-29, Venice, Italy, 1993. |
| 10. M. Renovell |
F. Azais, Y. Bertrand, “A DFT Technique to Fully
Access Embedded Modules in Analog Circuits Under Test",
International Mixed Signal Testing Workshop, June 20-22,
Grenoble, FRANCE, 1995. |
| 11. S. Lavabre |
M. Renovell, Y. Bertrand, “Modulable Configurations
to Enhance the Testability of Sequential Circuits",
MCEA’95, Mediterranean Conference on Electronics
and Automatic Control, Septembre, Grenoble, FRANCE,
1995, pp. 499-503. |
| 12. M. Renovell |
F. Azais, Y. Bertrand, “Analog Signature Analyzer
for Analog Circuits BIST Implementations", IEEE
International Mixed Signal Testing Workshop, May 15-18,
Quebec City, Canada, 1996, pp. 233-238. |
| 13. M. Renovell |
J. Figueras, Y. Zorian,“Testing the Interconnect
Structures of Unconfigurated FPGA", IEEE European
Test Workshop, pp. 125-129, June 12-14, Montpellier,
France, 1996. |
| 14. M. Renovell |
F. Azais, Y. Bertrand, “Analog DFT Technique
Implementation : A Case Study", IEEE European Test
Workshop, pp. 282-288, June 12-14, Montpellier, France,
1996. |
| 15. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “Testing
Unconfigured FPGA Logic Modules”, IEEE European
Test Workshop, Cagliari, Italy, May 28-30 1997. |
| 16. F. Azais |
J-C Bodin, M. Renovell, Y. Bertrand, “DC Test
Efficiency for Switch-Current Memory Cells", IEEE
European Test Workshop, ETW97, May 28-30, Cagliari,
Italy, 1997. |
| 17. F. Azais |
M. Renovell, Y. Bertrand, “Testability Improvement
Evaluation in Analog Multi-Configuration DFT Technique",
IEEE International Mixed Signal Testing Workshop, IMSTW97,
pp. 106-112, June 3-6, Seattle, Washington, USA, 1997. |
| 18. M. Lubaszewski |
M. Renovell, S. Mir, F. Azais, Y. Bertrand, “A
Multi-Mode Stimuli Generator for Analog and Mixed-Signal
Built-In Self-Test“ , IEEE International Mixed
Signal Testing Workshop, IMSTW98, pp. 100-106, June
8-11, The Hague, The Netherlands, 1998. |
| 19. M. Renovell |
F. Azais, J.C. Bodin, Y. Bertrand, “A Generic
BIST Scheme for Switched-Current Building Blocks",
IEEE International Mixed Signal Testing Workshop, IMSTW98,
pp. 113-122, June 8-11, The Hague, The Netherlands,
1998. |
| 20. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “SRAM-based
FPGA: Testing the RAM mode of the LUT/RAM Modules”,
IEEE European Test Workshop, pp. 5-9, Barcelona, Spain,
May 1998. |
| 21. M. Renovell |
F. Azais, Y. Bertrand, “Analysing Relationship
between Defect and Fault Model", IEEE European
Test Workshop, pp. 151-155, Barcelona, Spain, May 1998.
|
| 22. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “Test
Configuration Minimization for the Logic Cells of SRAM-Based
FPGAs”, IEEE European Test Workshop ETW99, pp.
146-151, May 25-28, Constance, Germany, 1999. |
| 23. M. Renovell |
F. Azais, J-C Bodin, Y. Bertrand, “Functional
and Structural Testing of Switched-Current Circuit“,
IEEE European Test Workshop ETW99, pp. 22-27, May 25-28,
Constance, Germany, 1999. |
| 24. M. Renovell |
F. Azais, Y. Bertrand, “Limitations of Classical
Fault Models", IEEE 10th European Workshop on Dependable
Computing, pp. 97-101, May 6-7, Vienna, Austria, 1999. |
| 25. J-C Bodin |
M. Renovell, F. Azais, Y. Bertrand, “Technique
de DFT pour Circuits à Courants Commutés“,
Colloque CAO de Circuits Intégrés et Systèmes,
Aix-en-Provence, pp. 14-17, 10-12 Mai, France, 1999. |
| 26. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “Test
des Circuits Configurables à Base de SRAM : La
Composante d’Interconnexion Globale”, Colloque
CAO de Circuits Intégrés et Systèmes,
Aix, pp. 84-87, 10-12 Mai, France, 99. |
| 27. M. Renovell |
F. Azais, J.C. Bodin, Y. Bertrand, “Mixed Test
Strategy for Switched-Current Circuits", IEEE International
Mixed Signal Testing Workshop, IMSTW99, pp. 177-193,
June 15-18, Vancouver, Canada, 1999. |
| 28. F. Azais |
M. Renovell, Y. Bertrand, A. Ivanov, S. Tabatabaei,
“A Unified Digital Test Technique for PLLs : Catastrophic
Fault Covered“, IEEE International Mixed Signal
Testing Workshop, pp. 269-292, June 15-18, Vancouver,
Canada, 99. |
| 29. M. Renovell |
F. Azais, J.C. Bodin, Y. Bertrand, “Testing
Switched-Current Memory Cells Using DC Stimuli",
3rd International Workshop on Design of Mixed-Mode Integrated
Circuits and Systems, Puerto-Vallarta, Mexico, July
1999. |
| 30. M. Renovell |
J.M. Portal, J. Figueras and Y. Zorian, “Test
Configuration Generation for FPGA Logic Cells ”,
IEEE 1st Latin-American Test Workshop LATW2000, pp.
202-208, March. 13-15, Rio de Janeiro, Brazil, 2000. |
| 31. S. Bernard |
F. Azais, Y. Bertrand, M. Renovell, “ Minimizing
the Hardware Overhead of a Histogram-Based BIST Scheme
for Analog-to-Digital Converters", IEEE 1st Latin-American
Test Workshop LATW2000, pp. 118-122, March. 13-15, Rio
de Janeiro, Brazil, 2000. |
| 32. L. Carro |
M. Renovell, E. Cota, M. Lubaszewski, Y. Bertrand,
F. Azais, “On the temperature Dependencies of
analog BIST”, IEEE 1st Latin-American Test Workshop
LATW2000, pp. 88-93, March. 13-15, Rio de Janeiro, Brazil,
2000. |
| 33. M. Renovell |
J.M. Portal, J. Figueras, Y. Zorian, “Minimal
sets of test configurations for the logic cells of XILINX,
ALTERA and LUCENT FPGAs ”, IEEE 3rd Workshop on
Design and Diagnostics of Electronic Circuits and Systems
DDECS00, pp. 4-11, Smolenice, Slovakia, Apr. 5-7, 2000. |
| 34. F . Azais |
S. Bernard, Y. Bertrand, M. Renovell, “Towards
an ADC BIST scheme using the Histogram Test Technique
”, IEEE European Test Workshop ETW’00, pp.
129-134, May 23-26, Cascais, Portugal, 2000. |
| 35. F. Zimmermann |
A. Susim, M. Renovell, “A Microprocesseur with
Analog Capabilities ”, IEEE International Mixed
Signal Testing Workshop, IMSTW’00, pp. 214-218,
June 21-23, Montpellier, France, 2000. |
| 36. S. Bernard |
F. Azais, Y. Bertrand, M. Renovell, “Linear
Histogram Test of ADCs – A BIST Implementation”,
”, IEEE International Mixed Signal Testing Workshop,
IMSTW’00, pp. 40-45, June 21-23, Montpellier,
France, 2000. |
| 37. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Electrical
Analysis of Gate Oxide Short in MOS Technologies”,
IEEE International Latin-American Test Workshop LATW’01,
pp. 266-272, Feb. 11-14, Cancun, Mexico. |
| 38. F. Azais |
S. Bernard, Y. Bertrand, X. Michel, M. Renovell,
“On-Chip Generation of High-Quality Ramp Stimulus
with Minimal Silicon Area”, IEEE International
Latin-American Test Workshop LATW’01, pp. 112-117,
Feb. 11-14, Cancun, Mexico. |
| 39. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “A Complete
Analysis of the Voltage Behavior of MOS Transistor with
Gate Oxide Short”, IEEE International Workshop
on Defect Based Testing DBT’01, pp. 5-10, April
29, Los Angeles, California, USA. |
| 40. S. Bernard |
F. Azais, Y. Bertrand, X. Michel, M. Renovell, “Efficient
on-chip Generator for Linear Histogram BIST of ADCs”,
IEEE International Mixed Signal Testing Workshop, IMSTW’01,
pp. 89-96, June 2001, Atlanta, USA. |
| 41. F . Azais |
S. Bernard, M. Comte, Y. Bertrand, M. Renovell and
M. Lubazewski, “Estimating Static Parameters of
A-to-D Converters from Spectral Analysis ”, IEEE
Latin American Test Workshop, pp. 174-179, Feb. 10-13,
2002, Montevideo, Urugay. |
| 42. A. Gonsales |
M. Lubazewski, L. Carro, M. Renovell, “A New
FPGA for DSP Applications Integrating BIST Capabilities”,
IEEE Latin American Test Workshop, pp. 76-81, Feb. 10-13,
2002, Montevideo, Urugay. |
| 43. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Non-Linear
and Non-Split Transistor MOS Model for Gate Oxide Short”,
IEEE International Workshop on Defect Based Testing
DBT’02, pp. 11-16, April 28, 2002, Monterey, USA.
|
| 44. S. Bernard |
F. Azais, Y. Bertrand, M. Renovell, “,A High
Accuracy Triangle-Wave Signal Generator for On-Chip
ADC Testing”, IEEE European Test Workshop ETW’02,
ISBN 0-7695-1715-3, pp. 89-94, May 2002, Corfu, Greece. |
| 45. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “Modelling
Gate Oxide Short Defects in CMOS Minimum Transistors”,
IEEE European Test Workshop ETW’02, ISBN 0-7695-1715-3,
pp. 15-20, May 26-29, 2002, Corfu, Greece. |
| 46. F . Azais |
S. Bernard, Y. Bertrand, M. Comte, M. Renovell, “Evaluation
of Static Parameters via Frequency Domain", IEEE
International Mixed-Signal Testing Workshop, pp. 165-169,
June 2002, Montreux, Switherland. |
| 47. F . Azais |
P. Nouet, M. Renovell, J.V. Calvano, M. Lubaszewski,
“Designing Testable Analog Filters with Optimal
DFT Insertion", IEEE International Mixed-Signal
Testing Workshop, pp. 201-203, June 2002, Montreux,
Switherland. |
| 48. M . Comte |
F. Azais, S. Bernard, Y. Bertrand, M. Renovell, “On
the Evaluation of ADC Static Parameters through Dynamic
Testing", International Conference on Advanced
A/D and D/A Conversion Techniques and their Applications
& European Workshop on ADC Modelling and Testing,
pp. 95-98, 2002. |
| 49. U. Kac |
F. Novak, F. Azais, P. Nouet, M. Renovell, “Implementation
of an Experimental IEEE 1149.4 Mixed-Signal Test Chip",
IEEE Board Test Workshop BTW’02, pp. 42, October
2002, Baltimore, USA. |
| 50. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, “GOSMOS
: A Gate Oxide Short Defect embedded in a MOS Compact
Model”, IEEE Latin American Test Workshop, pp.
6-11, Feb. 16-19, Natal, Brazil, 2003. |
| 51. M. Comte |
F. Azais, S. Bernard, Y. Bertrand, M. Renovell, “On
the Efficiency of Measuring ADC Dynamic Parameters to
Detect ADC Static Errors", IEEE Latin American
Test Workshop, pp. 174-179, Feb. 16-19, Natal, Brazil,
2003 |
| 52. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “Timing
Defect Analysis in Look-Up Tables of SRAM-Based FPGAs”,
IEEE Latin American Test Workshop, pp. 26-31, Feb. 16-19,
Natal, Brazil, 2003 |
| 53. M. Renovell |
J.M. Galliere, F. Azais, Y. Bertrand, J.M. Portal,
R. Bouchakour, “An Embedded Gate Oxide Short Model
for Efficient Electrical Simulation”, 9th IBERCHIP
Workshop, March 26-28, La Habana, Cuba, 2003. |
| 54. M. Comte |
S. Bernard, F. Azais, Y. Bertrand, M. Renovell, “A
New Methodology for ADC Test Flow Optimization",
IEEE European Test Workshop ETW’03, pp. , May
25-28, 2003, Maastricht, Netherland. |
| 55. P. Girard |
O. Heron, S. Pravossoudovitch, M. Renovell, “Requirements
for Delay Testing of Look-Up Tables in SRAM-Based FPGAs”,
IEEE European Test Workshop ETW’03, pp. 147-152,
May 25-28 , 2003, Maastricht, Netherland. |
| 56. I. Polian |
P. Engelke, M. Renovell, B. Becker, “Modelling
Feedback Bridging Faults with Non-Zero Resistance”,
IEEE European Test Workshop ETW’03, pp. 91-96,
May 25-28 , 2003, Maastricht, Netherland. |
| 57. S. Bernard |
F. Azais, Y. Bertrand, M. Renovell, “An Automatic
Tool Generation of ADC BIST Architecture", Proc.
IEEEE International Mixed-Signal Testing Workshop, June
2003, Sevilla, Spain. |
| 58. M. Comte |
F. Azais, S ; Bernard, Y. Bertrand, M. Renovell,
“Analysis of the Specification Influence on the
Efficiency of an Optimized Test Flow for ADCs",
Proc. IEEEE International Mixed-Signal Testing Workshop,
June 2003, Sevilla, Spain. |
| 59. R. Bouchakour |
J.M. Portal, J.M. Galliere, F. Azais, Y. Bertrand,
, M. Renovell, “A Compact DC Model of Gate Oxide
Short Defect”, Insulating Films on Semiconductors,
June 18-20, Barcelona, Spain, 2003. |
| 60. S. Bernard |
F. Azais, M. Comte, Y. Bertrand, M. Renovell, “Automatic
Generation of LH-BIST Architecture for ADC Testing",
IEEE Workshop on ADC Modelling and Testing 2003 (IWADC'03),
pp. 71-76, Sept. 2003. |
| 61. P. Engelke |
I. Polian, M. Renovell, and B. Becker, “Simulating
Resistive Bridging and Stuck-at Faults”, IEEE
International Workshop on Current and Defect-Based Testing,
pp. 49-56, Napa Valley, California, USA, May 2003. |
| 62. S. Bernardini |
P. Masson, J.M. Portal, J.M. Gallière, M.
Renovell, “Impact of Gate Oxide reduction Failure
on Analog Applications : Example of the Current Mirror”,
IEEE 5th Latin American Test Workshop, pp. 12-17, March
8-10, Cartagena, Colombia, 2004 |
| 63. P. Engelke |
I. Polian, M. Renovell, B. Seshadri, and B. Becker,
“The pros and cons of Very-Low-Voltage Testing
: an Analysis Based on Resistive Bridging Faults”,
GI/ITG Workshop Testmethoden und Zuverlassigkeit von
Schaltungen und Systemen, pp. 149-153, Dresden, Germany,
Feb 2004. |
| 64. A. Andrade |
G. Vieira, T.R. Balen, M. Lubaszewski, F. Azais,
M. Renovell, “ Testing Global Interconnects of
Field Programmable Analog Arrays", 10th IEEE International
Mixed Signal testing Workshop, 2004. |
| 65. M. Renovell |
“Principe et Problématique pour le Test
des System-On-Chip”, Signaux Circuits et Systèmes
2004, SCS’04, pp. 1-3, Tunisie, 2004. |
| 66. P. Engelke |
I. Polian, M. Renovell, and B. Becker, “Automatic
Test Pattern Generation for Resistive Bridging Faults”,
IEEE International Workshop on Current and Defect-Based
Testing, pp. 89-94, Napa Valley, California, USA, May
2004. |
| 67. M. Renovell |
S. Tanguy, “A Set of Test Configurations for
the Global Routing of Hierarchical FPGAs”, Iberchip
Workshop 2005, pp. 277-280, Bahia, Brazil, 2005. |
| 68. A. Regnier |
J.M. Portal, R. Bouchakour, M. Renovell, “Modeling
Halo Implant Failures in MOS Sub-Micron Technology”,
IEEE 6th Latin American Test Workshop, pp. 29-33, March,
Bahia, Brazil, 2005. |
| 69. A. Zenteno |
V.H. Champac, M. Renovell, F. Azais, “Analysis
and Attenuation Proposal in Ground Bounce”, IEEE
6th Latin American Test Workshop, pp. 34-39, March,
Bahia, Brazil, 2005. |
| 89.T.R. Balen |
T.A. Jost, J.V. Calvano, M. Lubaszewski, M. Renovell,
“ The Transient Response Analysis Method applied
to the Test of Field Programmable Analog Arrays",
IEEE 6th Latin American Test Workshop, pp. 252-257,
March, Bahia, Brazil, 2005. |
| 90. S. Bernard |
M. Comte, F. Azais, Y. Bertrand, M. Renovell, “Fast
and Fully Efficient Test Flow for ADCs", Proc.
IEEEE International Mixed-Signal Testing Workshop, pp.
244-249, June 2005, Canne, France. |
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