**Conference Papers**

[C97] B. Uhlig, A. Dhavamani, N. Nagy, K. Lilienthal, R. Liske, R. Ramos, J. Dijon, H. Okuno, D. Kalita, J. Lee, V. Georgiev, A. Asenov, S. Amoroso, L. Wang, F. Konemann, B. Gotsmann, G. Goncalves, B. Chen, J. Liang, R.R. Pandey, R. Chen, **A. Todri-Sanial**, “Challenges and Progress on Carbon Nanotube Integration for BEOL Interconnects (Invited),” in IEEE International Interconnect Technology Conference (IITC), June 2018.

[C96] L. Zhang, W. Kang, H. Cai, P. Ouyang, L. Torres, Y. Zhang, **A. Todri-Sanial** and W. Zhao, “A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM", IEEE International Symposium on VLSI (ISVLSI), 2018, pp. 275-280. doi: 10.1109/ISVLSI.2018.00058.

[C95] D. Liu. Y. Cheng, Y. Wang, B. Wu, B. Zhang, **A. Todri-Sanial**, W. Zhao, “Chameleon: A Thermally Adaptive Error Correction Code Design for STT-MRAM LLCs,” in IEEE Design Automation Conference (DAC), Work-in-Progress Session, 2018 (link).

[C94] B. Uhlig, J. Liang, J. Lee, R. Ramos, A. Dhavamani, N. Nagy, J. Dijon, H. Okuno. D. Kalita, V. Georgiev, A. Asenov, S. Amoroso, L. Wang, C. Millar, F. Konemann, B. Gotsmann, G. Goncalves, B. Chen, R.R. Pandey, R. Chen, **A. Todri-Sanial**, “Progress on Carbon Nanotube BEOL Interconnects,” in IEEE/ACM Design, Automation and Test in Europe Conference (DATE), March 2018, pp. 937-942. doi: 10.23919/DATE.2018.8342144.

[C93] J. Liang, R. Ramos, J. Dijon, H. Okuno, D. Kalita, D. Renaud, J. Lee, V. P. Georgiev, S. Berrada, T. Sadi, A. Asenov, B. Uhlig, K. Lilienthal, A. Dhavamani, F. Könemann, B. Gotsmann, G. Goncalves, B. Chen, K. Teo, R. R. Pandey, **A. Todri-Sanial**, "A Physics-Based Investigation of Pt-Salt Doped Carbon Nanotubes for Local Interconnects,” in IEEE International Electron Devices Meeting (IEDM), December 2017, pp. 35.5.1-35.5.4. doi: 10.1109/IEDM.2017.8268502.

[C92] N. Jeanniot, G. Pillonnet, P. Nouet, N. Azemard, **A. Todri-Sanial**, “Synchronized 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic,” in IEEE International Conference on Reboot Computing (ICRC), November 2017, pp.1-6, doi: 10.1109/ICRC.2017.8123661.

[C91] J. Liang, J. Lee, S. Berrada, V. Georgiev, A. Asenov, N. Azemard-Crestani, **A. Todri-Sanial**, "Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application,” in IEEE Nanotechnology Materials and Devices Conference (NMDC), October 2017, pp. 66-67. doi: 10.1109/NMDC.2017.8350506.

[C90] J. Liang, **A. Todri-Sanial**, “Power and Performance Analysis of Doped SW/DW CNT for On-Chip Interconnect Application”, in GRAPHENE 2017 International Conference.

[C89] J. Lee, T. Sadi, J. Liang, V. P. Georgiev, **A. Todri-Sanial**, and A. Asenov, “A hierarchical model for CNT and Cu-CNT composite interconnects: from density functional theory to circuit-level simulations,” in IEEE International Workshop on Computational Nanotechnology (IWCN) 2017.

[C88] J. Lee, S. Berrada, J.Liang, T. Sadi, V. Georgiev, **A. Todri-Sanial**, D. Kalita, R. Ramos, H.Okuno, J. Dijon, A. Asenov, “The impact of vacancy defects on CNT interconnects: From statistical atomistic study to circuit simulations,” in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, 2017, pp. 157-160. doi: 10.23919/SISPAD.2017.8085288.

[C87] J. Lee, J. Liang, S. M. Amoroso, T. Sadi, L. Wang, P. Asenov, A. Pender, D. Reid, V.P. Georgiev, C. Millar, **A. Todri-Sanial**, A. Asenov, "Atoms-to-circuits simulation investigation of CNT interconnects for next generation CMOS technology," in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, 2017, pp. 153-156. doi: 10.23919/SISPAD.2017.8085287.

[C86] A. Magnani, M. de Magistris, S. Heidari, **A. Todri-Sanial** and A. Maffucci, "Electrical performance of carbon-based power distribution networks with thermal effects," in IEEE Workshop on Signal and Power Integrity (SPI), Baveno, 2017, pp. 1-4. doi: 10.1109/SaPIW.2017.7944044.

[C85] J. Liang, L. Zhang, N. Azemard-Crestani, P. Nouet and **A. Todri-Sanial**, "Physical description and analysis of doped carbon nanotube interconnects," in IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Bremen, 2016, pp. 250-255. doi: 10.1109/PATMOS.2016.7833695

[C84] N. Jeanniot, **A. Todri-Sanial**, P. Nouet, G. Pillonnet and H. Fanet, "Investigation of the power-clock network impact on adiabatic logic," in IEEE Workshop on Signal and Power Integrity (SPI), Turin, 2016, pp. 1-4.
doi: 10.1109/SaPIW.2016.7496270

[C83] A. Magnani, M. de Magistris, A. Maffucci and **A. Todri-Sanial**, "A clustering technique for fast electrothermal analysis of on-chip power distribution networks," in IEEE Workshop on Signal and Power Integrity (SPI), Turin, 2016, pp. 1-4, doi: 10.1109/SaPIW.2016.7496292.

[C82] **A. Todri-Sanial**, "Investigation of electrical and thermal properties of carbon nanotube interconnects," in IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Bremen, 2016, pp. 25-32.
doi: 10.1109/PATMOS.2016.7833421

[C81] **A. Todri-Sanial**, A. Magnani, M. de Magistris and A. Maffucci, "Present and future prospects of carbon nanotube interconnects for energy efficient integrated circuits," in International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), Montpellier, 2016, pp. 1-5, doi: 10.1109/EuroSimE.2016.7463379.

[C80] L. Zhang, Y. Cheng, W. Kang, Y. Zhang, W. Zhao, L. Torres, **A. Todri-Sanial**, "Reliability and performance evaluation for STT-MRAM under temperature variation," in International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), Montpellier, 2016, pp. 1-4, doi: 10.1109/EuroSimE.2016.7463380.

[C79] L. Zhang, Y. Cheng, W. Kang, Y. Zhang, W. Zhao, L. Torres, **A. Todri-Sanial**, "Quantitative evaluation of reliability and performance for STT-MRAM," in IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 1150-1153, doi: 10.1109/ISCAS.2016.7527449.

[C78] C. Metzler, **A. Todri-Sanial**, P. Girard, “Small Delay Defect Investigation in Critical Path Delay with Multiple TSVs,” EMicro-NE, Oct 2015, Campina Grande, Brazil. X Escola de Microeletrônica do Nordeste, 2015.

[C77] Ch. Effiong, V. Lapotre, A. Gamatie, **A. Todri-Sanial**, G. Sassatelli, “On the performance exploration of 3D NoCs with resistive-open TSVs,” in IEEE International Symposium on VLSI (ISVLSI), 2015, pp. 579-584.
doi: 10.1109/ISVLSI.2015.49.

[C76] G. Mouslih, **A. Todri-Sanial**, P. Nouet, “On analysis of on-chip DC-DC converters for power delivery networks,” IEEE International Symposium on VLSI (ISVLSI), pp. 557-560, 2015, doi: 10.1109/ISVLSI.2015.96.

[C75] X. Zhang, Y. Cheng, Y, Zhang, W. Zhao, **A. Todri-Sanial**, “Write back energy optimization for STT-RAM based cache using data pattern characterization,” IEEE Design Automation Conference (DAC), WIP session, 2015.

[C74] D. Zhang, Y, Cheng, Y. Qu, Y. Zhang, W. Zhao, **A. Todri-Sanial**, “Low Power and High Speed Neuromorphic Network Construction Using Stochastic Synapse-like Spintronics Devices,” IEEE International Symposium on Circuits and Systems (ISCAS), 2015.

[C73] R. Kheirallah, J.M Galliere, **A. Todri-Sanial**, N. Azemard, G. Ducharme, "Statistical energy study for 28nm FDSOI devices," International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), pp.1-4, 2015. doi: 10.1109/EuroSimE.2015.7103149.

[C72] L. Yang, Y. Cheng, Y. Wang, H. Yu, W. Zhao, **A. Todri-Sanial**, "A body-biasing of readout circuit for STT-RAM with improved thermal reliability," IEEE International Symposium on Circuits and Systems (ISCAS), pp.1530-1533, 2015. doi: 10.1109/ISCAS.2015.7168937.

[C71] A. Magnani, M. de Magistris, A. Maffucci, **A. Todri-Sanial**, “A node clustering reduction scheme for power grids electrothermal analysis”, IEEE Signal Power Integrity Workshop (SPI), pp.1-4, 2015, doi: 10.1109/SaPIW.2015.7237399.

[C70] A. Magnani, M. de Magistris, A. Maffucci, **A. Todri-Sanial**, “Carbon-based power delivery networks for nanoscale ics: Electrothermal performance analysis”, IEEE International Conference on Nanotechnology (NANO), pp. 416-419. 2015, doi: 10.1109/NANO.2015.7388625. **Nanoscale Horizons Award**

[C69] B. Wu, Y. Cheng, Y. Wang, **A. Todri-Sanial**, G. Sun, L. Torres, W, Zhao, “An Architecture-level cache simulation framework supporting most advanced PMA STT-MRAM,” IEEE/ACM International Symposium on nanoscale architectures (NANOARCH), 2015, pp. 7-12, doi: 10.1109/NANOARCH.2015.7180576.

[C68] **A. Todri-Sanial**, “Carbon nanotube interconnects for energy-efficient integrated circuits,” IEEE International Conference on Trends in Nanotechnology (TNT), pp.1-1, 2015.

[C67] Y. Cheng, **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard, A. Virazel, "Power Supply Noise-Aware Workload Assignment for Homogeneous 3D MPSoCs with Thermal Consideration," ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp.544-549, 2014.

[C66] C. Metzler, **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “TSV Aware Timing Analysis and Diagnosis in Paths with Multiple TSVs,” IEEE VLSI Test Symposium (VTS), pp.1-6, 2014.

[C65] **A. Todri-Sanial**, “Thermal Characterization of Through-Silicon Vias,” IEEE International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EurosimE), pp.1-6, 2014.

[C64] M. Valka, A. Bosio, L. Dilillo, **A. Todri**, A. Virazel, P. Girard, Ph. Debaud, S. Guilhot, “Test and Diagnosis of Power Switches,” IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.213-218, 2014.

[C63] I. Wali, A. Virazel, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, “Protecting Combinational Logic in Pipelined Microprocessors,” IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 223-225, 2014.

[C62] A. Asokan, **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, “Path Delay Test in the Presence of Multi-Aggressor Crosstalk, Power Supply Noise and Ground Bounce,“ IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.207-212, 2014.

[C61] C. Metzler, **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “Timing-aware ATPG for Critical Paths with Multiple TSVs,” IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.116-121, 2014.

[C60] A. Bosio, L. Dilillo, P. Girard, **A. Todri-Sanial**, A. Virazel, S. Bernabovi, P. Bernardi, “An Intra-Cell Defect Grading Tool,” IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 298-301, 2014.

[C59] **A. Todri-Sanial**, "Investigation of horizontally aligned carbon nanotubes for efficient power delivery in 3D ICs," IEEE 18th Workshop on Signal and Power Integrity (SPI), pp.1-4, 2014.

[C58] A. Touati, A. Bosio, L. Dilillo, P. Girard, **A. Todri-Sanial**, A. Virazel, P. Bernardi, "A Comprehensive Evaluation of Functional Programs for Power-Aware Test," IEEE 23rd North Atlantic Test Workshop (NATW), pp.69-72, 2014.

[C57] A. Asokan, **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A.Virazel, "A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.226-231, 2014.

[C56] M. Valka, A. Bosio, L. Dilillo, **A. Todri**, A. Virazel, P. Girard, P. Debaud, S. Guilhot, "iBoX — Jitter based Power Supply Noise sensor," IEEE European Test Symposium (ETS), pp.1-2, 2014.

[C55] A. Kologeski, F. Lima Kastensmidt, V. Lapotre, A. Gamatie, **A. Todri-Sanial**, G. Sassatelli, “Performance Exploration of Partially Connected 3D NoCs under Manufacturing Variability,” IEEE International NEWCAS Conference, pp.1-6, 2014.

[C54] X. Zhang, Y. Cheng, W. Zhao, Y. Zhang, **A. Todri-Sanial**, “Exploring Potentials of Perpendicular Magnetic Anisotropy STT-MRAM for Cache Design”, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp.1-6, 2014.

[C53] L. B. Zordan, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, N. Badereddine, “Test Solution for Data Retention Faults in Low-Power SRAMs”, ACM/IEEE Design, Automation and Test in Europe (DATE), 2013.

[C52] L. B. Zordan, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, N. Badereddine, “A Built-in Scheme for Testing and Repairing Voltage Regulators of Low-Power SRAMs”, IEEE VLSI Test Symposium (VTS), 2013.

[C51] Zh. Sun, A. Bosio, L. Dilillo, P. Girard, **A. Todri-Sanial**, A. Virazel, E. Auvray, “Effect-Cause Intra-Cell Diagnosis at Transistor Level,” IEEE International Symposium on Quality Electronics Design (ISQED), 2013.

[C50] I. Vatajelu, A. Bosio, L. Dilillo, P. Girard, **A. Todri-Sanial**, A. Virazel, N. Badereddine, "Analysing the effect of Concurrent Variability in the Core Cells and Sense Amplifiers on SRAM Read and Access Failures," Design and Technology of Integrated Systems (DTIS), 2013.

[C49] C. Metzler, **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Vivet, M. Belleville, "Computing Detection Probability of Delay Defects in Signal Line TSVs," IEEE European Test Symposium (ETS), 2013.

[C48] I. Vatajelu, A. Bosio, L. Dilillo, P. Girard, **A. Todri-Sanial**, A. Virazel, N. Badereddine, "Analysing Resistive-Open Defects in SRAM Core-Cell under the Effect of Process Variability," IEEE European Test Symposium (ETS), 2013.

[C47] G. Tsiligiannis, E.I. Vatajelu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, **A. Todri**, A. Virazel, F. Wrobel, F. Saigne, "SRAM SER Evaluation Under Atmospheric Neutron Radiation and PVT variations," IEEE International On-Line Testing Symposium (IOLTS), 2013.

[C46] Y. Cheng, **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Vivet, M. Belleville, "Mitigate TSV Electromigration for 3D ICs - From the Architecture Perspective," IEEE International Symposium on VLSI (ISVLSI), 2013.

[C45] **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Vivet, M. Belleville, "Fast and Accurate Electro-Thermal Analysis of Three-Dimensional Power Delivery Networks," IEEE International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EurosimE), 2013.

[C44] L. Zordan, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, N. Badereddine, "On the Reuse of Read and Write Assist Circuits to Improve Test Efficiency in Low-Power SRAMs," IEEE International Test Conference (ITC), 2013.

[C43] **A. Todri-Sanial**, A. Bosio, L. Dilillo, P. Girard and A. Virazel, "Worst-Case Power Supply Noise and Temperature Distribution Analysis for 3D PDNs with Multiple Clock Domains," IEEE International New Circuits and Systems Conference (NEWCAS), 2013.

[C42] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, **A. Todri**, A. Virazel, C. Frost, F. Wrobel, F. Saigne, "Temperature Impact on the Neutron SER of a commercial 90nm SRAM," IEEE Nuclear and Space Radiation Effects Conference (NSREC), 2013.

[C41] **A. Todri-Sanial**, "Frequency Domain Power and Thermal Integrity Analysis of 3D Power Delivery Networks," IEEE Signal and Power Integrity Workshop (SPI), 2013.

[C40] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, **A. Todri**, A. Virazel, J. Mekki, M. Brugger, J-R. Vaille, F. Wrobel, F. Saigne, “Characterization of an SRAM Based Particle Detector For Mixed-Field Radiation Environments,” IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), 2013.

[C39] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, **A. Todri**, A. Virazel, “SEU Monitoring in Mixed-Field Radiation Environment of Particle Accelerators,” IEEE Conference on Radiation Effects on Components and Systems (RADECS), 2013.

[C38] E. I. Vatajelu, G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, **A. Todri-Sanial**, A. Virazel, F. Wrobel, F. Saigne, “On the Correlation between Static Noise Margin and Soft Error Rate Evaluated for a 40nm SRAM Cell,” IEEE Symposium on Defect and Fault Tolerance in VLSO and Nanotechnology Systems (DFT), 2013.

[C37] J. Azevedo, A. Virazel, Y. Cheng, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, J. Alvarez-Herault, “Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive Defects,” International Conference on Advances in Systems Testing and Validation Lifecycle (VALID), 2013.

[C36] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, **A. Todri**, A. Virazel, C. Frost, F. Wrobel, F. Saigne, “Multiple-Cell-Upsets on a Commercial 90nm SRAM in Dynamic Mode,” IEEE Conference on Radiation Effects on Components and Systems (RADECS), 2013.

[C35] I.E. Vatajelu, L. Dilillo, A. Bosio, P. Girard, **A. Todri-Sanial**, A. Virazel, N. Badereddine, “Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing,” Asian Test Symposium (ATS), 2013.

[C34] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, G. Prenat, K. Mackay, “Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures,” IEEE/ACM Design Automation and Test in Europe (DATE), pp. 532-537, 2012.

[C33] D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, M. Imhof, H.J. Wunderlich, “A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures,” IEEE VLSI Test Symposium (VTS), pp. 50-55, 2012.

[C32] L. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, **A. Todri**, A. Virazel, N. Badereddine, “Defect Analysis in Power Mode Control Logic of Low-Power SRAMs,” IEEE European Test Symposium (ETS), pp. 179-179, 2012.

[C31] C. Metzler, **A. Todri**, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “Resistive-Open Defect Analysis for Through-Silicon-Vias,” IEEE European Test Symposium (ETS), pp. 183-183, 2012.

[C30] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, G. Prenat, J. Alvarez-Herault, K. Mackay, “Coupling-Based Resistive-Open Defects in TAS-MRAM Architectures,” IEEE European Test Symposium (ETS), pp. 180-180, 2012.

[C29] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, **A. Todri**, A. Virazel, A. Touboul, F. Wrobel, F. Saigne, “Evaluation of Test Algorithm Stress Effects on SRAMs under Neutron Radiation,” IEEE International On-Line Testing Symposium (IOLTS), pg. 121-122, 2012.

[C28] **A. Todri**, A. Bosio, L. Dilillo, P. Girard, A. Virazel, S. Kundu, “Electro-Thermal Analysis of 3D Power Delivery Networks,” IEEE Work-In-Progress Session, Design Automation Conference (DAC), 2012.

[C27] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, **A. Todri**, A. Virazel, F. Wrobel, F. Saigne, “A Novel Framework for Evaluating the SRAM Core-Cell Sensitivity to Neutrons,” accepted in IEEE Conference on Radiation Effects on Components and Systems (RADECS), 2012.

[C26] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, **A. Todri**, A. Virazel, A. Touboul, F. Wrobel, F. Saigne, “Dynamic Mode Test of a Commercial 4Mb Toggle MRAM under Neutron Radiation,” accepted in IEEE Conference on Radiation Effects on Components and Systems (RADECS), 2012.

[C25] Zh. Sun, A. Bosio, E. Auvray, P. Girard, L. Dilillo, **A. Todri**, A. Virazel, “Fault Localization Improvement Through an Intra-Cell Diagnosis Approach,” accepted in IEEE International Symposium for Testing and Failure Analysis (ISTFA), 2012.

[C24] C. Metzler, **A. Todri**, A. Bosio, P. Girard, A. Virazel, “Resistive-Open Defect Analysis for Through-Silicon-Vias,” accepted in IEEE Conference on Design of Circuits and Integrated Systems (DCIS), 2012.

[C23] L. Zordan, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, N. Badereddine, “Low-Power SRAMs Power Mode Control Logic: Failure Analysis and Test Solutions,” IEEE International Test Conference (ITC), pp.1-10, 2012.

[C22] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, G. Prenat, J. Alvarez-Herault, K. Mackay, “Impact of Resistive-Bridge Defects in TAS-MRAM Architectures,” submitted to IEEE Asian Test Symposium (ATS), pp. 125-130, 2012.

[C21] M. Valka, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, P. Debaud, S. Guilhot, “Power Supply Noise Sensor based on Timing Uncertainty Measurements,” submitted to IEEE Asian Test Symposium (ATS), pp. 161-166, 2012.

[C20] A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, "Why and How Controlling Power Consumption During Test: A Survey", IEEE Asian Test Symposium (ATS), pp. 221-226, 2012.

[C19] Z. Sun, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, E. Auvray, “Improving Defect Localization Accuracy by means of Effect-Cause Intra-Cell Diagnosis at Transistor Level”, IEEE International Workshop on Silicon Debug and Diagnosis (SDD), 2012.

[C18] **A. Todri**, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, “A Study of Path Delay Variations in the Presence of Uncorrelated Power and Ground Noise,” IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 189-194, 2011.

[C17] **A. Todri**, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, “Power Supply Noise and Ground Bounce Aware Pattern Generation for Delay Testing,” IEEE International New Circuits and Systems (NEWCAS) Conference, pp. 73-76, 2011.

[C16] L. Zordan, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, N. Badereddine, “Failure Analysis and Test Solutions for Low-Power SRAMs,” IEEE Asian Test Symposium (ATS), pp.459-460, 2011.

[C15] A. Bosio, L. Dilillo, P. Girard, **A. Todri**, A. Virazel, K. Miyase, X. Wen, “Power-Aware Test Pattern Generation for At-Speed LOS Testing,” IEEE Asian Test Symposium (ATS), pp. 506-510, 2011.

[C14] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, **A. Todri**, G. Prenat, K. McKay, “Analysis of Resistive-Open Defects in Thermally-Assisted MRAM Array,” IEEE International Test Conference (ITC), 2011.

[C13] **A. Todri**, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, “Simultaneous Power and Thermal Integrity Analysis for 3D Integrated Systems,” IEEE International Workshop on the Impact of Low Power on Test and Reliability (LPonTR), 2011.

[C12] Andreani, A. Andreazza, A. Annovi, M. Beretta, V. Bevacqua, M. Bogdan, E. Bossini, A. Boveia, F. Canelli, Y. Cheng, M. Citterio, F. Crescioli, M. Dell'Orso, G. Drake, M. Dunford, J. F. Genat, P. Giannetti, F. Giorgi, J. Hoff, A. Kapliy, M. Kasten, Y. K. Kim, N. Kimura, A. Lanza, V. Liberali, T. Liu, A. McCarn, C. Melachrinos, C. Meroni, A. Negri, M. Neubauer, M. Piendibene, J. Proudfoot, G. Punzi, M. Riva, F. Sabatini, I. Sacco, L. Sartori, M. Shochet, A. Stabile, F. Tang, **A. Todri**, R. Tripiccione, J. Tuggle, V. Vercesi, M. Villa, R. A. Vitullo, G. Volpi, J. Wu, K. Yorita and J. Zhang, “The Fast Tracker Real Time Processor and Its Impact on Muon Isolation, Tau & b-Jet Online Selections at ATLAS,” IEEE/NPSS Real-Time Conference, ATL-DAQ-PROC-2010-014, 2010.

[C11] Andreani, A. Andreazza, A. Annovi, M. Beretta, V. Bevacqua, M. Bogdan, E. Bossini, A. Boveia, F. Canelli, Y. Cheng, M. Citterio, F. Crescioli, M. Dell'Orso, G. Drake, M. Dunford, J. F. Genat, P. Giannetti, F. Giorgi, J. Hoff, A. Kapliy, M. Kasten, Y. K. Kim, N. Kimura, A. Lanza, V. Liberali, T. Liu, A. McCarn, C. Melachrinos, C. Meroni, A. Negri, M. Neubauer, M. Piendibene, J. Proudfoot, G. Punzi, M. Riva, F. Sabatini, I. Sacco, L. Sartori, M. Shochet, A. Stabile, F. Tang, **A. Todri**, R. Tripiccione, J. Tuggle, V. Vercesi, M. Villa, R. A. Vitullo, G. Volpi, J. Wu, K. Yorita and J. Zhang, “Enhancement of the ATLAS Trigger System with a Hardware Tracker Finder FTK,” Topical Workshop on Electronics for Particle Physics, CD-ROM, 2010.

[C10] **A. Todri**, M. Turqueti, R. Rivera, S. Kwan, L. Perera, “Performance Studies of CMS Pixel Tracker Using DC-DC Conversion Powering Scheme,” IEEE Nuclear Science Symposium and Medical Imaging Conference, pp. 1038 -1041, 2010.

[C9] **A. Todri**, L. Perera, R. Rivera, and S. Kwan, “Reliability and Performance Studies of DC-DC Conversion Powering Scheme for the CMS Pixel Tracker at SLHC,” Topical Workshop on Electronics for Particle Physics, 2010.

[C8] **A. Todri**, M. Marek-Sadowska, F. Maire, Ch. Matheron, “A Study of Decoupling Capacitor Effectiveness in Power and Ground Grid Networks,” IEEE International Symposium on Quality of Electronic Design, pp. 653-658, 2009.

[C7] **A. Todri**, M. Marek-Sadowska, “Electromigration Study of Power Gated Grids,” ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 315-318, 2009.

[C6] **A. Todri**, M. Marek-Sadowska, F. Maire, Ch. Matheron, “Decoupling Capacitance Allocation for Power Supply Noise Reduction,” SRC Technology and Talent for the 21st Century, TECHCON (CD-ROM), 2009.

[C5] **A. Todri**, M. Turqueti, R, Rivera, S. Kwan, “Power Studies for the CMS Pixel Tracker,” IEEE Nuclear Science Symposium and Medical Imaging Conference, pp. 1208-1211, 2009.

[C4] **A. Todri**, M. Marek-Sadowska, “A Study of Reliability Issues in Clock Distribution Networks,” IEEE International Conference on Computer Design, pp. 101-106, 2008.

[C3] **A. Todri**, M. Marek-Sadowska, J. Kozhaya, “Power Supply Noise Aware Workload Assignment for Multi-Core Systems,” IEEE/ACM International Conference on Computer-Aided Design, pp. 330-337, 2008.

[C2]. **A. Todri**, Sh-C. Chang, M. Marek-Sadowska, “Electromigration and Voltage Drop Aware Power Grid Optimization for Power-Gated ICs,” IEEE International Symposium on Low Power Electronics and Design, pp. 391-394, 2007.

[C1] **A. Todri**, M. Marek-Sadowska, Sh-C. Chang, “Analysis and Optimization of Power-Gated ICs with Multiple Power Gating Configurations,” IEEE/ACM International Conference on Computer-Aided Design, pp. 783-790, 2007.