Poster Papers

    [P24] J. Liang, R. Ramos, J. Dijon, H. Okuno, D. Kalita, D. Renaud, J. Lee, V. Georgiev, S. Berrada, T. Sadi, A. Asenov, B. Uhlig, K. Lilienthal, A. Dhavamani, F. Koenemann, B. Gotsmann, G. Goncalves, B. Chen, K. Teo, R. Pandey and A. Todri-Sanial, "Progress on Pt-Salt Doped Carbon Nanotubes for Local Interconnects", GDR SoC-SiP 2018.

    [P23] N. Jeanniot, G. Pillonnet, A. Todri-Sanial, “4-Phase Resonant Power-Clock Supply for Adiabatic Logic,” GDR Soc-SiP 2017.

    [P22] N. Jeanniot, A. Todri-Sanial, P. Nouet, G. Pillonnet, H. Fanet, “Impact of Power-Clock Network on Adiabatic Logic,” in Colloque GDR SoC-SiP 2016.

    [P21] L. Zhang, Y. Cheng, W. Kang, Y. Zhang, W. Zhao, L. Torres, A. Todri-Sanial, “Investigation of Reliability and Performance for STT-MRAM under PVT Variations,” in Colloque GDR SoC-SiP 2016.

    [P20] N. Jeanniot, A. Todri-Sanial, P. Nouet, G. Pillonnet, H. Fanet, “Impact of Power-Clock Network on Adiabatic Logic,” in IEEE PwrSoc Workshop, 2016.

    [P19] A. Todri-Sanial, “On Carbon Nanotubes as VLSI Interconnects,” CMOS Emerging Technology Research Symposium, 2014.

    [P18] A. Todri-Sanial, “Carbon Nanotubes for Energy Efficient Integrated Circuits,” CNRS Colloque Physique Theorique et ses Interfaces, 2014.

    [P17] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri,“Performance Evaluation of Capacitive Defects on TAS-MRAM,” Colloque du GDR SoC-SiP, 2013.

    [P16] G. Tsiligiannis, L. Dilillo, A, Bosio, P. Girard, S. Pravossoudovitch, A. Todri, A. Virazel, “Investigating Multiple-Cell-Upsets on a 90nm SRAM,” Colloque GDR SoC-SiP, 2013.

    [P15] Zh. Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, “Fault-Effect Propagation Based Intra-Cell Scan Chain Diagnosis,” Colloque GDR SoC-SiP, 2013.

    [P14] J. Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G. Prenat, J. Alvarez-Herault, K. Mackay, “Impact of Resistive-Open Defects in the Word-Line Selection of TAS-MRAMs,” Colloque du GDR Soc-Sip, 2012.

    [P13] C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel, “Through Silicon Via Resistive-Open Defect,” Colloque du GDR Soc-Sip, 2012.

    [P12] G. Tsiligiannis, L. Dilillo, A. Bosio, P. Girard, A. Todri, A. Virazel, “Dynamic Mode Testing of SRAMs under Neutrons,” Colloque du GDR Soc-Sip, 2012.

    [P11] Zh. Sun, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, E. Auvray, “Effective Defect Localization Through an Effect-Cause based Intra-Cell Diagnosis,” Colloque du GDR Soc-Sip, 2012.

    [P10] M. Valka, A. Bosio, L. Dilillo, A. Todri, A. Virazel, P. Girard, P. Debaud, “Adaptive Voltage Scaling Via Effective On-Chip Timing Uncertainty Measurement,” Colloque du GDR Soc-Sip, 2012.

    [P9] A. Todri-Sanial,"Voltage Droop and Thermal Constraints Driven Optimization of 3D Power Delivery Networks," Workshop Design for 3D (D43D), 2012.

    [P8] M. Imhof, H-J Wunderlich, D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri,“Ein Pseudo-Dynamischer Komparator zur Fehlererkennung in fehlertoleranten Architekturen”, Workshop: Testmethoden und Zuverlaessigkeit von Schaltungen und Systemen, 2012.

    [P7] B. Zordan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Todri, A. Virazel, N. Bedereddine, “Failure Analysis and Test Solutions for Low-Power SRAMs,” Emerging Technologies and Green Soc-Sip, 2011.

    [P6] M. De Carvalho, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, “A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing,” Emerging Technologies and Green Soc-Sip, 2011.

    [P5] A. Todri, L. Perera, R. Rivera, and S. Kwan, "Reliability and Performance Studies of DC-DC Conversion Powering Scheme for the CMS Pixel Tracker at SLHC," Topical Workshop on Electronics for Particle Physics, 2010.

    [P4] A. Todri, L. Perera, R. Rivera, and S. Kwan, "Reliability and Performance Studies of DC-DC Conversion Powering Scheme for the CMS Pixel Tracker at SLHC," Fermilab Workshop on Detector RD, 2010.

    [P3] A. Todri, M. Marek-Sadowska, "Electromigration Study of Power Gated Grids," Proceedings in IEEE International Symposium on Low Power Electronics and Design, 2009.

    [P2] A. Todri, M. Marek-Sadowska, F. Maire, Ch. Matheron, "Decoupling Capacitance Allocation for Power Supply Noise Reduction," Technology and Talent for the 21st Century, TECHCON 2009

    [P1] A. Todri, Sh-C. Chang, M. Marek-Sadowska, "Electromigration and Voltage Drop Aware Power Grid Optimization for Power-Gated ICs," Proceedings in IEEE International Symposium on Low Power Electronics and Design 2007.