{"id":3372,"date":"2023-10-24T14:00:00","date_gmt":"2023-10-24T12:00:00","guid":{"rendered":"https:\/\/www.lirmm.fr\/adac\/?p=3372"},"modified":"2024-04-16T17:02:08","modified_gmt":"2024-04-16T15:02:08","slug":"adac-scientific-seminar-user-friendly-fpga-accelerated-computer-architecture-simulation","status":"publish","type":"post","link":"https:\/\/www.lirmm.fr\/adac\/2023\/10\/24\/adac-scientific-seminar-user-friendly-fpga-accelerated-computer-architecture-simulation\/","title":{"rendered":"ADAC Scientific Seminar: User-Friendly FPGA-Accelerated Computer Architecture Simulation"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\"><strong>Presenter:<\/strong> Soraya MOBARAKI<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Abstract:<\/strong><br>Companies and academia increasingly rely on simulation before fabrication to meet the demand for low-power and high-performance computer architecture designs due to the high manufacturing costs. However, software simulators are often too slow to run complete real-world applications, and FPGA-accelerated simulators have emerged as a more practical approach. However, FPGA-accelerated simulators are challenging to use and require hardware design expertise. In this context, we aim to make a new user-friendly, Fast, and Faithful Computer-System Architecture Simulation (F3CAS) approach to achieve FPGA-accelerated simulation. As our first use case, we want to add more cache replacement policies, evaluate them, and then move the cache replacement part to a soft processor to give flexibility to the user. F3CAS will combine FPGA acceleration with tightly coupled domain-specific programmable soft processors to provide a software-like abstraction.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Date:<\/strong>\u00a0October 24, 2023 from 2 to 4 pm (salle de s\u00e9miniaires, LIRMM*) <\/p>\n\n\n\n<pre class=\"wp-block-preformatted\"><\/pre>\n","protected":false},"excerpt":{"rendered":"<p>Presenter: Soraya MOBARAKI Abstract:Companies and academia increasingly rely on simulation before fabrication to meet the demand for low-power and high-performance computer architecture designs due to the high manufacturing costs. However, software simulators are often too slow to run complete real-world applications, and FPGA-accelerated simulators have emerged as a more practical approach. However, FPGA-accelerated simulators are [&hellip;]<\/p>\n","protected":false},"author":45,"featured_media":3353,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_eb_attr":"","_crdt_document":"","footnotes":""},"categories":[33],"tags":[],"class_list":["post-3372","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news"],"_links":{"self":[{"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/posts\/3372","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/users\/45"}],"replies":[{"embeddable":true,"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/comments?post=3372"}],"version-history":[{"count":1,"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/posts\/3372\/revisions"}],"predecessor-version":[{"id":3376,"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/posts\/3372\/revisions\/3376"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/media\/3353"}],"wp:attachment":[{"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/media?parent=3372"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/categories?post=3372"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.lirmm.fr\/adac\/wp-json\/wp\/v2\/tags?post=3372"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}