Monolithic 3D (M3D) integration presents a new dimension for interconnect innovation to extend the aggressive scaling of Moore’s law. M3D integration aims at processing transistors on top of each other sequentially. Its interest resides in providing ultra-high 3D contact density such as between device layers, close to planar contacts. The idea behind M3D integration is to exploit the current fabrication technology of 2D on-chip Tungsten contact plugs for implementing high-density 3D monolithic inter-layer vias between logic tiers. In this work, we investigate the timing and power performance of monolithic 3D circuits and explore novel design approaches for further optimizing power and clock delivery networks of such circuits. Our comprehensive work encompasses, device and interconnect-level study, circuit-level modeling and optimization, and full-chip power/clock delivery construction and optimization, and timing/power analysis for various technology nodes.