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Third IEEE International Workshop on Automotive Reliability & Test

Phoenix, Arizona, USA
November 01-02, 2018.

held in conjunction with ITC 2018

The ART workshop focuses exclusively on test and reliability of automotive and mission-critical electronics, including design, manufacturing, burn-in, system-level integration and in-field test, diagnosis and repair solutions, as well as architectures and methods for reliable and safe operations under different environmental conditions. With increasing system complexity, security, stringent runtime requirements for functional safety, and cost constraints of a mass market, the reliable operation of electronics in safety-critical domains is still a major challenge. This second edition of the ART Workshop offers a forum to present and discuss these challenges and emerging solutions among researchers and practitioners alike.

ART will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.

You are invited to participate and submit your contributions to the ART Workshop. The workshop's areas of interest include (but are not limited to) the following topics:

  • Functional safety and security in the automotive domain
  • Automotive standards and certification – ISO 26262
  • Approximate computing and Artificial Intelligence
  • Multi-layer dependability evaluation
  • Verification and validation of automotive systems
  • Fault tolerance and self-checking circuits
  • Aging effects on automotive electronics
  • Resiliency by application
  • Dependability challenges of autonomous driving and e-mobility
  • Power-up, power-down and periodic test
  • System level test
  • Reuse of test infrastructure
  • Functional and structural test generation
  • High quality volume test- minimizing DPPM
  • Life cycle test cost minimization
  • Embedded Tutorial

    ASPICE and ISO 26262 Compliant Software Development Methodologies

    Organizer: Rubin Parekhji, Texas Instruments.
    Presenters: Zoran Mladenovic and Bharat Rajaram, Texas Instruments.

    Abstract: The advent of the several disruptive trends in the automotive industry (vehicle electrification, connectivity and autonomous cars) is expected to increase the semiconductor content in automobiles by 3-5x (vs. conventional cars). As a result the cost of developing quality, reliable SW has easily become a significant portion of the NRE (non-recurring engineering) costs. Several international standards (ASPICE and ISO 26262) recommend the state-of-the-art in developing, testing and productizing quality software. These standards are very broad in their scope as they have to address the needs of all types of electronic systems in cars (from TPMS – tire pressure monitoring systems to completely driverless cars). Care OEMs and Tier 1s are demanding that semiconductor manufacturers follow these standards while developing even the most basic software components like low-level device drivers and SDKs (software development kits). It is important for semiconductor companies to study and interpret the recommendations of these standards and select methods and techniques that are congruent to the complexity of the software being developed. Otherwise it is very easy to be overwhelmed and err on the side of caution by adding on significant overhead for software development teams. In fact, most software developed by semiconductor companies are ‘out-of-context’ as there is limited knowledge regarding the final end-application that the software will be deployed in.
    In this tutorial Zoran Mladenovic and Bharat Rajaram will outline a case study in how an ASPICE, ISO 26262 and IEC 61508 compliant software development process was conceptualized and installed at Texas Instruments. This is ~2 year journey, and there are several lessons learned that have now led to a benchmark methodology for reliable, quality software development.

    Speaker Bios:

    Zoran Mladenovic is the CTO for Embedded Software and Tools, Embedded Processing, TI. He joined TI in 1999, through the acquisition of Telogy Networks, a startup in Washington DC area. Zoran spent most of his carrier working on embedded systems with primary focus on application development. After joining TI, he has participated in definition and architecture of several market specific SoCs, bringing the best of hw/sw integration in terms of functionality and power consumption. Lately, his focus has been on establishing SW product strategy and improving the software development methodology and development efficiency, including integration of Functional Safety Strategy into TI’s development processes. In addition to being CTO, he is in charge of TI’s SW Development Tools organization.

    Bharat Rajaram is the Director of Functional Safety for WW Connected MCU-C2000. Bharat has worked at Texas Instruments for ~ 23 years and in the Semiconductor Industry for 29+ years. He has held extremely diverse roles that span Semiconductor Equipment (SEMI), Process Development, Integration, Yield Enhancement, Applications Engineering, Program Management, Customer Quality/Reliability, Technology Development and Functional Safety. Bharat is a Certified Functional Safety Professional (TUV SUD license # TP16010516) and is currently responsible for defining Texas Instrument’s Functional Safety Strategy and go-to market needs.

    PANEL: Smarter test for Automotive

    Organizer: Teresa McLaurin, ARM
    Moderator: Davide Appello, STMicroelectronics

    Alan Becker, ARM
    Christophe Eychenne, Bosch
    Sandeep Goel, TSMC
    Robert Jin, NXP
    Riccardo Mariani, Intel

    Abstract: Currently we are so fearful of missing something that we may be planning to overtest in the field. For example, ECC vs online MBIST. If ECC is checking the contents of the memories constantly for correctness, do we need to be periodically doing online MBIST or is MBIST at POST enough? On the other side, how do we ensure the tests we are running are high quality (testing the most critical logic). For instance, if the goal is 90% test coverage and we achieve that on the whole module, we stop looking. But, perhaps if we dig down we might find that some blocks are achieving much less coverage. How do we determine if these contain critical logic? Instead of throwing every test at the problem or not testing to a high enough quality (they may both look the same from a high enough level), can we get smarter about the testing we are doing?
    The panelists will address solutions to these important issues, discussing also Functional Safety (FuSa) methodologies to reach the levels of safety demanded by ISO 26262.

    Panelist Bios:

    Alan Becker is a Staff CPU design engineer at ARM in Cambridge, UK. He joined ARM over 15 years ago and in the preceding 15 years he was an ASIC design engineer working on applications for defence, consumer electronics and telecommunications for multiple companies including Nortel, BAE Systems, NEC, Philips Semiconductors and GEC Plessy Telecom. Alan invented software transparent on-line MBIST and holds 4 patents related to this. He holds a master’s degree in electronics engineering from the University of Hertfordshire, UK.

    Xiankun (Robert) Jin (M’14) received the M.S. degree in electrical engineering from University of Texas at Austin on 2013. He is a Senior Principal Engineer at Mixed-Signal IP team at Automotive Microcontroller and Processors group of NXP Semiconductors located in Austin, Texas, United States. He is leading a small team working on a long-term innovation project towards automotive functional safety architecture for autonomous driving. He led the implementation of an on-chip ADC BIST solution supported by NXP/Freescale Discovery Labs starting 2014. Prior to that, he worked as analog and mixed-signal test engineer, DFT team lead and design engineer in microcontroller group of Freescale/Motorola since joining the company on 2002. His main topic of interest includes in-field test to enhance functional safety, on-chip analog BIST techniques to reduce test cost, and BIST based calibration to improve performance of analog modules.

    Sandeep Kumar Goel received the M.Tech. degree in VLSI Design Tools and Technology (VDTT) from the Indian Institute of Technology (IIT) Delhi, in 1999, and the Ph.D. degree in Electrical and Computer Engineering from the University of Twente, The Netherlands, in 2005. Dr. Sandeep Kumar Goel is an Academician and Department Manager with Taiwan Semiconductor Manufacturing Company (TSMC), USA. Prior to joining TSMC in 2010, he was in various research and management positions with LSI Corporation, Magma Design Automation, and Philips Research, The Netherlands. He has co-authored two books, six book chapters, and published over 90 papers in journals and conference/workshop proceedings. He has delivered several invited talks, tutorials, and has been panelist at several conferences including DAC, ITC and ICCAD. He holds 59 US patents and has over 40 other patents pending. His current research interests include all topics in the domain of design verification, testing, diagnosis, functional safety and defect modeling of 2D/3D SOCs. Dr. Goel was a recipient of the Most Significant Paper Award at the IEEE International Test Conference in 2010. Dr. Goel serves on various conference committees including DATE, DAC, ETS, ITC, DATA, and 3DTest. He was the General Chair of 3D Workshop at DATE 2012. He is a senior member of the IEEE.

    Christophe Eychenne is DFT architect at Bosch in France. He has worked for more than 20 years in the semiconductor industry, first as an ASIC designer at MBD.A missile system, and later as a DFT architect and team leader at NXP, ST Ericsson and STMicroelectronics. At Bosch, a major focus for Christophe is the development of test methodologies to ensure functional safety in automotive ICs. He graduated from the Polytechnic University School of Montpellier with an MS in microelectronics engineering. He lives in Sophia Antipolis in the south of France with his wife and two children and enjoys completing in 15Km and 20Km trail races.

    Riccardo Mariani is widely recognized as an expert in functional safety and integrated circuit reliability. In his current role as chief functional safety technologist at Intel Corporation, he oversees strategies and technologies for IoT applications that require functional safety, high reliability and performance, such as autonomous driving, transportation and industrial systems. Mariani spent the bulk of his career as CTO of Yogitech, an industry leader in functional safety technologies. Before co-founding the Italian company in 2000, he was technical director at Aurelia Microelettronica, where his responsibilities included leading high-reliability topics in projects with CERN in Geneva. A prolific author and respected inventor in the functional safety field, Mariani has contributed to multiple industry standards efforts throughout his career, including leading the ISO 26262-11 part specific to semiconductors. He has also won the SGS-Thomson Award and the Enrico Denoth Award for his engineering achievements. He holds a bachelor’s degree in electronic engineering and a Ph.D. in microelectronics from the University of Pisa in Italy.

    Important Dates

    • Discounted rate registration: before September 30, 2018
    • Submission deadline : September 07, 2018 Extended to September 14, 2018
    • Notification of acceptance : September 28, 2018
    • Camera-ready material : October 12, 2018

    Organizing Committee

    General Chair: Yervant Zorian – Synopsys (US)
    Vice General Chair: Davide Appello – ST Micro (IT)
    Program Chair: Paolo Bernardi – Polito (IT)
    Finance Chair: Suriya Natarajan – INTEL (US)
    Panel Chair: Teresa McLaurin – ARM (US)
    Embedded Tutorial Chair: Rubin Parekhji – TI (IN)
    Media Chair: Alberto Bosio – INL (FR)
    Publicity Chair: Marco Restifo - Polito (IT)

    Program Committee (to include)

    M. AbdelwahidMentor Graphics, US
    O. BallanXilinx, US
    N. BishnoiGlobalfoundries, IN
    G. BoschiIntel, IT
    A. CronSynopsys, US
    W. DobbelaereOn Semiconductor, B
    P. EngelkeInfineon, DE
    C. EychenneBOSCH, FR
    D. GizopoulosAthens University, GR
    S.K. GoelTSMC, US
    K. GrebNVidia, US
    A. HalesTexas Instruments, US
    P. HarrodARM, UK
    V. HuardSTMicroelectronics, FR
    W.-Y. KoeXilinx, US
    R. MarianiIntel, IT
    R. MontinoElmos, DE
    N. MukherjeeMentor Graphics, US
    M. PortolanTIMA, FR
    A. PrioreARM, UK
    P. RechUFGRS, BR
    E. SanchezPolitecnico di Torino, IT
    S. SarangiNvidia, US
    P. SarsonDialog, UK
    M. SchillinskyNXP, DE
    R. SrinivasanNVidia, US
    D. TilleInfineon, DE
    M. WahlUniversität Siegen, DE
    H.-J. WunderlichStuttgart University, DE
    H.M. von StaudtDialog, DE




    Register to ART 2018 by accessing the following url: https://www.badgeguys.com/reg/2018/itc/register.aspx/

    Early Registration Rates (before September 30, 2018) Regular Registration Rates (after September 30, 2018)
    IEEE/CS Member $240 $300
    Nonmember $300 $375
    IEEE/CS Student Member $130 $160
    Nonmember Student $240 $300