ANR JCJC F3CAS
Rethinking FPGA-Accelerated Computer Architecture Simulation for Data Storage Exploration
Modern high-performance mobile computing architectures spend more than 60% of the energy on data storage and movement. However, fundamental limitations in existing evaluation tools hinder innovation in memory systems.
The F3CAS project proposes a new paradigm to build user- Friendly, Fast and Faithful Computer-system Architecture Simulations (F3CAS) tailored to the exploration of new memory architectures.
The main goal of this project is to uniquely combine FPGA-acceleration with tightly coupled domain-specific soft-processors to encapsulate the simulator in a software-like abstraction. The F3CAS simulation paradigm will be demonstrated in the evaluation of hybrid memory systems, which include emerging non-volatile memory technologies, in high-performance computing systems.
Related Publications
- S. Mobaraki, T. Gil, L. Torres, D., Novo. “Exploring Cache Policies on FPGA-Accelerated Simulations: Tradeoffs Between Usability and Simulation Speed.” 36th International Workshop on Rapid System Prototyping (RSP), 2025.
- O. Canpolat, A. Olgun, D. Novo, O. Ergin, and O. Mutlu. “EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques.” 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2025.
- D. CastellsâRufas, D. Novo, and X. Martorell. “Punxa: A PythonâBased RISCâV System Simulator for Education.” Electronics Letters 61, no. 1 (2025).
- D. Castells-Rufas, D. Novo, and X. Martorell. “An Educational Tool to Analyze the Hardware/Software Integration in RISC-V Systems.” In 2024 39th Conference on Design of Circuits and Integrated Systems (DCIS), pp. 1-6. IEEE, 2024.
Details
- PI: David Novo (CNRS, LIRMM)
- Start date: October 1, 2022
- Project duration: 3.5 years
- ANR funding: 230,000 âŹ
- ANR JCJC project: ANR-20-CE25-0010
