| 7:30 8:30 |
REGISTRATION....... |
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| 8:30 9:00 |
OPENING
SESSION |
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| 9:00 9:45 |
SESSION
1: KEYNOTE ADDRESS |
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Paul Master
Quicksilver Technology |
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| 9:50 10:40 |
SESSION
2A: TRENDS |
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Chair:
to be defined |
| 2A.1 |
Disruptive Trends by Custom
Compute Engines
Reiner Hartenstein (Invited Presentation) |
| 2A.2 |
Multithreading for logic-centric
systems
Gordon Brebner |
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| 9:50 10:40 |
SESSION
2B: RAPID PROTOTYPING |
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Chair:
to be defined |
| 2B.1 |
Fast Prototyping with
Co-Operation of Simulation and Emulation
Siavash Bayat Sarmadi, Seyed Ghasem
Miremadi, Ghazanfar Asadi, Ali Reza Ejlai |
| 2B.2 |
How Fast is Rapid FPGA-Based
Prototyping: Lessons and Challenges From the Digital TV Design Prototyping
Project
Helena Krupnova, Veronique Meurou,
Christophe Barnichon, Carlos Serra, and Farid Morsi |
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| 9:50 10:40 |
SESSION
2C: FPGA SYNTHESIS |
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Chair:
to be defined |
| 2C.1 |
Implementing asynchronous
circuits on LUT based FPGAs
Quoc Thai Ho, Jean-Baptiste Rigaud,
Laurent Fesquet, Marc Renaudin, Robin Rolland |
| 2C.2 |
A technique for FPGA synthesis
driven by automatic source code analysis and transformations
Beniamino Di Martino, Nicola Mazzocca,
Giacinto Paolo Saggese, Antonio G.M. Strollo |
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| 10:40 11:10 |
COFFEE
BREAK & POSTER SESSION 1 |
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| 11:10 - 12:25 |
SESSION
3A: CUSTOM COMPUTING ENGINES |
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Chair:
to be defined |
| 3A.1 |
Flexible Routing Architecture
Generation for Domain-Specific Reconfigurable Subsystems
Katherine Compton, Akshay Sharma,
Shawn Phillips, Scott Hauck |
| 3A.2 |
iPACE-V1: A Portable Adaptive
Computing Engine For Real Time Applications
Jawad Khan, Manish Handa, Ranga
Vemuri |
| 3A.3 |
Field-Programmable Custom
Computing Machines
Mihai Sima, Stammatis Vassiliadis,
Sorin Cotofana, Jos T.J. van Eijndhoven, Kees Vissers |
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| 11:10 - 12:25 |
SESSION
3B: DSP APPLICATIONS (1) |
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Chair:
to be defined |
| 3B.1 |
Embedded Reconfigurable
Logic Core for DSP Applications
Katarzyna Leijten-Nowak and Jef
L. van Meerbergen |
| 3B.2 |
Efficient FPGA-based QPSK
Demodulation Loops: Application to the DVB standard
Francisco Cardells-Tormo, Javier
Valls-Coquillat, Vincenc Almenar-Terre, and Vincente Torres-Carot |
| 3B.3 |
FPGA QAM Demodulator Design
Chris Dick and Fred Harris |
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| 11:10 - 12:25 |
SESSION
3C: RECONFIGURABLE FABRICS |
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Chair:
to be defined |
| 3C.1 |
Analytical Framework for
Switch Block Design
Guy G. Lemieux, David M. Lewis |
| 3C.2 |
Modular, Fabric-specific
Synthesis for Programmable Architectures
Aneesh Koorapaty and Lawrence Pileggi |
| 3C.3 |
On Optimum Designs of
Universal Switch Blocks
Hongbing Fan, Jiping Liu, Yu-Liang
Wu, and Chak Chung Cheung |
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| 12:25 - 13:45 |
LUNCH....... |
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| 13:45 - 14:25 |
SESSION
4: INDUSTRIAL SESSION |
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Chair:
to be defined
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Progress and Challenges in FPGAs
Bernie New - Xilinx Labs, USA |
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| 14:30 - 16:10 |
SESSION
5.A: DYNAMIC RECONFIGURATION (1) |
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Chair:
to be defined |
| 5A.1 |
Improved Functional Simulation
of Dynamically Reconfigurable Logic
Ian Robertson, James Irvine, Patrick
Lysaght and David Robinson |
| 5A.2 |
Run-time Reconfiguration
to Check Temperature in Custom Computers: AN Application of Jbits Technology
S. Lopez-Buedo, P. Pernas and E.
Boemo |
| 5A.3 |
Dynamic Reconfiguration
in Mobile Systems
Gerard J.M. Smit, Paul J.M. Havinga,
Lodewijk T. Smit, Paul M. Heysters, Michel A.J. Rosien |
| 5A.4 |
Using PARBIT to implement
Partial Run-Time Reconfigurable Systems
Edson l. Horta, John W. Lockwood,
and Sergio T. Kofuji |
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| 14:30 - 16:10 |
SESSION
5.B: DSP APPLICATIONS (2) |
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Chair:
to be defined |
| 5B.1 |
Multiplier-less realization
of a Poly-phase Filter using LUT-based FPGAs
R.H. Turner, R.Woods, T. Courtney |
| 5B.2 |
Speech Recognition on
an FPGA Using Discrete and Continuous Hidden Markov Models
Stephen J. Melnikoff, Steven F.
Quigley, Martin J. Russell |
| 5B.3 |
FPGA implementation of
the wavelet packet transform for high speed communications
Antony Jamin, Petri Mähönen |
| 5B.4 |
A Method for Implementing
Bit-Serial Finite Impulse Response Digital Filters in FPGAs using Jbits
A. Carreira, T.W. Fox, L.E. Turner |
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| 14:30 - 16:10 |
SESSION
5.C: ROUTING & PLACEMENT |
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Chair:
to be defined |
| 5C.1 |
Automatic Partitioning
for Improved Placement and Routing in Complex Programmable Logic Devices
Valavan Manohararajah, Terry Borer,
Stephen D. Brown, Zvonko Vranesic |
| 5C.2 |
Rapid and Reliable Routability
Estimation for FPGAs
Parivallal Kannan, Shankar balachandran,
Dinesh Bhatia |
| 5C.3 |
Integrated Approach to
FPGA Placement
Zdenek Muzikar, Martin Danek |
| 5C.4 |
TDR: A Distributed-Memory
Parallel Routing Algorithm for FPGAs
Lucidio A. F. Cabral, Julio S.
Aude (in memorium) and Nelson Maculan |
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| 16:10 16:40 |
COFFEE
BREAK & POSTER SESSION 1 |
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| 16:40 - 18:20 |
SESSION
6.A: DYNAMIC RECONFIGURATION (2) |
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Chair:
to be defined |
| 6A.1 |
High-Level Partitioning
of Digital Systems Based on Dynamically Reconfigurable Devices
Rafal Kielbik, Juan Manuel Moreno,
Andrzej Napieralski, Grzegorz Jablonski, Tomasz Szymanski |
| 6A.2 |
High Speed Homology Search
using Run-time Reconfiguration
Yoshiki Yamaguchi, Yosuke Miyajima,
Tsutomu Maruyama, Akihiko Konagaya |
| 6A.3 |
Partially Reconfigurable
Cores for Xilinx Virtex
Matthias Dyer, Christian Plessl,
Marco Platzner |
| 6A.4 |
On-line Defragmentation
for Run-Time Partially Reconfigurable FPGAs
Manuel G. Gericota, Gustavo R.
Alves, Miguel L. Silva, José M. Ferreira |
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|
| 16:40 - 18:20 |
SESSION
6.B: POWER ESTIMATION |
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Chair:
to be defined |
| 6B.1 |
A Flexible Power Model
for FPGAs
Kara K. W. Poon, Andy Yan, and
Steven J.E. Wilton |
| 6B.2 |
A clocking technique with
power savings in Virtex-based pipelined designs
Oswaldo Cadenas and Graham Megson |
| 6B.3 |
Energy Evaluation on a
Reconfigurable Multimedia-Oriented Wireless Sensor
Maurizio Martina, Gianluca Piccinini,
Fabrizio Vacca, and Maurizio Zamboni |
| 6B.4 |
A Tool for Activity Estimating
in FPGAs
E. Todorovich, M. Gilabert, G.
Sutter, S. Lopez-Buedo, and E. Boemo |
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| 16:40 - 18:20 |
SESSION
6.C: SYNTHESIS ISSUES |
| |
Chair:
to be defined |
| 6C.1 |
FSM Decomposition for
Low Power in FPGA
Gustavo Sutter, Elias Todorvich,
Sergio Lopez- Buedo, and Eduardo Boemo |
| 6C.2 |
Hybrid Routing for FPGAs
by Integrating Boolean Satisfiability with Geometric Search
Gi-Joon Nam, Karem Skallah and
Rob Rutenbar |
| 6C.3 |
A Prolog-based Hardware
Development Environment
K. Benkrid, D. Crooks, A. Benkrid
and S. Belkacemi |
| 6C.4 |
Fly - A Modifiable Hardware
Compiler
C.H. Ho, P.H.W. Leong, K.H. Tsoi,
R. Ludewig, P.Zipf, A.G. Ortiz, M. Glesner |
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|
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| 19:30 |
INDUSTRIAL
PARTY / DINNER. |
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|
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| POSTER
SESSION P1 |
| P1.1 |
Data Dependent Circuit
for Subgraph Isomorphism Problem
Shuichi Ichikawa and Shoji Yamamoto |
| P1.2 |
Exploration of Design
Space in ECDSA
Jan Schmidt, Martin Novotný,
Maritn Jäger, Milos Becvár, Michal Jáchim |
| P1.3 |
2D and 3D Computer Graphics
Algorithms under Morphosys
Issam Damaji, Sohaib Majzoub, and
Hassan Diab |
| P1.4 |
A HIPERLAN/2 - IEEE 802.11a
Reconfigurable System-on-Chip
S. Blionas, K. Masselos, C. Dre,
F. Ieromnimon, T. Pagonis, A. Pneymatikakis, A. Tatsaki, T. Trimis, A.
Vontzalidis, D. Metafas |
| P1.5 |
SoftTOTEM: An FPGA Implementation
of the TOTEM Parallel Processor
Stephanie McBader, Luca Clementel,
Alvise Sartori, Andrea Boni, Peter Lee |
| P1.6 |
Real-time Medical Diagnosis
on a Multiple FPGA-based System
Takashi Yokota, Masamichi Nagafuchi,
Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba |
| P1.7 |
Threshold Element-Based
Symmetric Function Generators and their Functional Extension
Kazuo Aoyama and Hiroshi Sawada |
| P1.8 |
Hardware Implementation
of a Multiuser Detection Scheme Based on a Recurrent Neural Network
Wolfgang Schlecker, Achim Engelhart,
Werner G. Teich, Hans-Jörg Pfleiderer |
| P1.9 |
Building Custom FIR Filters
Using System Generator
James Hwang and Jonathan Ballagh |
| P1.10 |
SoC based Low Cost Design
of Digital Audio Broadcasting Transport Network Applications
Klaus Feske, Georg Heinrich, Berndt
Fritzsche, Mark Langer |
| P1.11 |
Dynamic Constant Coefficient
Convolvers Implemented in FPGAs
Ernest Jamro, Kazimierz Wiatr |
| P1.12 |
VIZARD II: An FPGA-based
Interactive Volume Rendering System
Urs Kanus, Gregor Wetekam, Johannes
Hirche, Michael Meißner |
| P1.13 |
RHINET / NI: A reconfigurable
network interface for cluster computing
Naoyuki Izu, Tomonori Yokoyama,
Junichiro Tsuchiya, Konosuke Watanabe, Tomohiro Kudoh and Hideharu Amano |
| P1.14 |
General Purpose Prototyping
Platform for Data-Processor Research and Development
Filip Miletic, Rene van Leuken,
Alexander de Graaf |
| P1.15 |
Optimal Generation of
DSP Processors From Behavioral Description
Adeel Abbas, Shoab Khan |
