HS-Scale: a MP-SOC Architecture for Embbeded Systems

 

Scalability of architecture, programming model and task control management will be a major challenge for MultiProcessor-System On Chip designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. The hardware architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed memories and a Globally Asynchronous / Locally Synchronous Network on Chip. S-Scale is the software support to program H-Scale. It is a multi-threaded sequential programming model with dedicated communication primitives handled at run-time by a simple Operating System we developed. This architecture target applications for embedded systems as well as for multimedia, smart sensors or robotics domains.