Emplois

PHD POSITION IN PARALLEL ROBOTICS / MECHANICAL DESIGN: HIGH RESOLUTION AND LARGE WORKSPACE MANIPULATORS

PHD POSITION IN PARALLEL ROBOTICS / MECHANICAL DESIGN: HIGH RESOLUTION AND LARGE WORKSPACE MANIPULATORS

The LIRMM at University of Montpellier is looking for graduate students interested in pursuing a PhD degree in parallel robotics with a focus on mechanical design and modeling of accuracy.
Montpellier University, France
LIRMM (Montpellier Institute of Informatics, Robotics and Microelectronics)
Posilab (Ultra Precision Positioner Laboratory, ANR LabCom)

Thesis Problematics

The practical goal is to set the position and orientation in space of an effector with high resolution on a large workspace. Such a problem can be illustrated considering the radio receiver of a spherical antenna. In such application, the spherical mirror is fixed. Thus pointing towards a star in the sky consists in moving optimally the focal point (the receiver) and adjusting the receiver’s orientation. In the current state of development, there are essentially machines with high resolution OR with large workspace. This is explained by the antagonist characteristics between these two features. The work in this thesis should help overcoming this limitation by designing a machine capable of fulfilling both requirements simultaneously. Foreseen strategy to bridge the gap is redundancy: actuation redundancy, kinematic redundancy, measurement redundancy and structural redundancy (hyperstatics). Foreseen Solution: Design of an improved Gough/Stewart platform (hexapod).

Work Context

High accuracy parallel robotics. A parallel manipulator is made of several kinematic (transmission) chains placed in a parallel manner (unlike conventional serial manipulators made of a single chain). This architecture offers several advantages such as high stiffness, for example. By high resolution, we mean below micrometer for linear resolution, and below arc-second for angular resolution.

Desired Candidate Profile/Nature of Work and Expected Skills

Mathematics for Engineers (trigonometry, vector analysis, linear algebra, root mean square optimization), mechanical modeling (multi-body kinematics), basic control (PID control). But also, implementation and evaluation of actual demonstrators.

Work Environment

The thesis will take place in the Dexter team of the Robotics division of LIRMM, especially with the experts in mechanical design and parallel robotics. These experts are well known for the innovative solutions they propose (including the famous industrial Adept Quattro robot), as well as their pragmatic approach “from concept to demonstrator”.

Note on Industrial Partnership

The PhD thesis will be held in the context of the French National Research Agency (ANR) LabCom project called Posilab. It will imply a strong industrial partnership with the company named Symétrie, located in Nîmes, which is specialized in high accuracy hexapods. At the end of the thesis an industrial grade demonstrator should be realized.

Additional notes

• Co-supervisor and contact: dr. Sébastien KRUT
• Supervisor: dr. François PIERROT
Thesis begins October 1st 2016 for 3 years.

Contact

Dr. Sébastien KRUT
CNRS Research Scientist in Robotics (French Nat. Center for Scientific Research)
with LIRMM (Montpellier Institute of Informatics, Robotics and Microelectronics)
an Academic Research Institute from Montpellier University and CNRS
161 rue Ada, 34090 MONTPELLIER, FRANCE | +33 (0)4 67 41 85 88 | sebastien.krut@lirmm.fr

How to apply?

Interested applicants should send a motivation letter, a detailed CV, current transcript and recommendation letters to sebastien.krut@lirmm.fr

PHD POSITION: Analog Measurements based on Digital Test Equipment for Low-Cost Testing of Analog/RF Integrated Circuits

PHD POSITION: Analog Measurements based on Digital Test Equipment for Low-Cost Testing of Analog/RF Integrated Circuits

The general context of this thesis is the development of low-cost methods to test analog/RF devices. Indeed, the conventional approach for testing such devices is specification-based testing, which relies on the direct measurement of the circuit performance parameters. This approach offers good test quality but at the price of extremely high testing costs, principally because it necessitates the use of dedicated testers equipped with sophisticated and expensive analog/RF resources. The purpose of this thesis is to develop test solutions for analog/RF devices that make use of inexpensive digital testers. The basic idea consists of converting the analog/RF signal into a digital bit stream. This conversion may be achieved by a simple comparator stage, that can be located on-chip or by using simple digital channel of standard test equipment. During this conversion, the information carried by the analog/RF signal (amplitude, frequency, phase…) is transformed into a timing information in the digital bit stream. The idea is then to develop dedicated post-processing algorithms in order to retrieve the analog signal characteristics, so that low-cost test becomes possible.

This approach is motivated by the fact that with technology scaling, circuits operate at lower supply voltages but with ever higher frequencies. In other words, technology scaling yields to degraded voltage resolution but improved time resolution. The objective is to exploit this trend and develop test solutions that rely on time-based data rather than on voltage measurements. The main benefit of such solutions resides in the dramatic reduction in the required test equipment since it permits to get rid of the expensive analog/RF tester resources required for the conventional method. Moreover, because digital channels are usually available in a large number on a standard ATE, it also offers the possibility to implement multi-site testing in order to further reduce the testing costs.

In the framework of this thesis, a first objective is to implement such a strategy for a Smart Home Transceiver (2.4GHz) from NXP Semiconductors intended for Internet of Things (IoT) growing market. Dedicated algorithms together with their associated test configurations will be developed to estimate different signal characteristics, targeting more specifically EVM measurements for the transmitter module. The performances that can be achieved will be first evaluated by simulation (Matlab environment) and then validated through experimental measurements performed on an industrial digital ATE. A second objective is to optimize the developed algorithms in order to permit on-chip integration in an advanced System-on-Chip (SoC). Additional benefits of on-chip integration are (i) a lower test cost with a possibly reduced ATE channel count and parallel testing capability, and (ii) the possibility of performing measurements in the application for safety enhancement.

This work will be carried out in the context of PENTA European Project “HADES” that involves several academic laboratories and industrial partners including NXP Semiconductors. Required skills mainly concern mathematics (statistics), digital signal processing and programming (Matlab). A good knowledge in the field of electronics/microelectronics is also required.

Duration/Date: 3 years starting December 2016.

Keywords:           Test, Digital signal processing, Analog/RF circuits.

Contacts :             LIRMM                                      NXP Semiconductors
Florence Azais (azais@lirmm.fr)                               François Lefèvre (francois.lefevre@nxp.com)
Laurent Latorre (latorre@lirmm.fr)

PHD POSITION: Methodology for Efficient Implementation of Indirect Testing for Analog/RF Integrated Circuits

PHD POSITION: Methodology for Efficient Implementation of Indirect Testing for Analog/RF Integrated Circuits

The general context of this thesis is the development of low-cost methods to test analog/RF devices. Indeed, the conventional practice for testing analog and RF circuits is specification-based testing, which relies on the measurement of the circuit performances and the comparison of the measured values with specification tolerance limits. While this approach can offer good test quality, it often incurs extremely high testing costs. Indeed, the measurement of analog or RF performances necessitates the use of dedicated test equipment, and because of the continuous improvement in the performances of new generation ICs, it becomes difficult or very expensive to find the instruments to measure accurately the specifications. Apart from increased ATE cost, the nature of each individually measured performance may imply a custom test setup which further increases conventional test cost, as well as time, especially when a large number of performances are to be evaluated. Moreover, as design trends tend to integrate complex and heterogeneous systems in one package, new technical difficulties are added to the heavy test costs. For instance, it becomes impossible to access all the inner components’ primary inputs and outputs in order to provide stimuli and catch test responses. Finally, in case of RF signals; a key challenge is to perform RF measurements at wafer level due to probing issues, and applying wafer-level specification-based testing at 100% is hardly possible.

In this context, there has been a number of research works over the past twenty years to try to overcome the cost and inabilities of specification-based testing for analog and RF circuits. Among the proposed solutions, the concept of “alternate test” (also called “indirect test”) has emerged as an attractive solution. The idea is to replace the conventional analog or RF performance measurements by some simple and low-cost measurements. The fundamental principle is to learn during a training phase the correlation between conventional analog/RF performances and low-cost Indirect Measurements (IMs). This correlation is then exploited during the mass production testing phase in order to deduce the circuit performances using only those low-cost indirect measurements.

Despite the substantial test cost reduction offered by this strategy and a number of interesting results reported in the literature on a various type of analog and RF circuits, its deployment in industry is limited. The efficiency of this type of methodology is actually impacted by many factors such as the definition and choice of adequate indirect parameters, the choice of the mapping between indirect measurements and device specifications, the size of the training set or the problem of test efficiency and test confidence evaluation. Current practice for the implantation of this strategy strongly relies on the expertise of design and test engineers that have to develop a tailored solution adapted to every new product. There is therefore a need for a generic methodology that can be used as a guide by design and test engineers in order to fit with industrial constraints and truly benefit from test cost reduction offered by the indirect test strategy.

In the framework of this thesis, a first objective is to develop a generic framework that integrates dedicated processing algorithms associated with the different steps of indirect test implementation, i.e. selection of indirect measurements, prediction model construction and indirect test efficiency evaluation. Based on an analysis of the different approaches used in machine-learning, the most pertinent algorithms with respect indirect testing will be selected, optimized and implemented. The generic framework will then be used to explore efficiency/cost tradeoff that can be achieved by indirect test under different scenarios. This generic framework will therefore constitute an essential element to guide the design and test engineers regarding practical aspects of alternate test implementation. A second objective of the thesis is to investigate the potentialities of indirect testing for a BIST (Buit-In Self-Test) implementation in order to equip devices with self-test capabilities that can be used in-field to enhance product safety. All developments will be demonstrated using a Smart Home Transceiver (2.4GHz) from NXP Semiconductors as test vehicle, focusing more specifically on the TX and RX blocks with the objective to estimate RF parameters (power, linearity, sensitivity…) based on internal DC measurements.

This work will be carried out in the context of PENTA European Project “HADES” that involves several academic laboratories and industrial partners including NXP Semiconductors. Required skills mainly concern mathematics (computational statistics) and programming (Matlab). A good knowledge in the field of electronics/microelectronics is also required.

Duration/Date: 3 years starting December 2016.

Keywords:           Test, Analog/RF circuits, Machine-Learning.

Contacts :             LIRMM                                      NXP Semiconductors
Florence Azais (azais@lirmm.fr)                               François Lefèvre (francois.lefevre@nxp.com)
Laurent Latorre (latorre@lirmm.fr)

Dernière mise à jour le 08/12/2016