Brief description. CONTINUUM is a project addressing the design of next generation energy-efficient high-performance embedded compute nodes. It focuses at the same time on software, architecture and emerging memory and communication technologies in order to synergistically exploit their corresponding feautures.

• LIRMM (France)
• Cortus S.A.S (France)
• Inria Rennes (France)

Brief description.Energy efficiency is already a primary concern for the design of any computer system and it is unanimously recognized that future Exascale systems will be strongly constrained by their power consumption. This is why the Mont-Blanc project, which was launched on 1st October 2011, has set itself the following objective: to design a new type of computer architecture capable of setting future global High Performance Computing (HPC) standards that will deliver Exascale performance while using 15 to 30 time less energy.

• Allinea (UK)
• ARM (UK)
• BSC (Spain)
• Bull (France)
• CEA (France)
• LRZ (Germany)
• University of Bristol (UK)
• CNRS (France)
• Genci (France)
• HLRS (Germany)
• CINECA (Italy)
• Inria (France)
• Jülich (Germany)
• ST-Microelectronics (France)

Brief description.The DreamCloud Project (Dynamic Resource Allocation in Embedded and High Performance Computing) is a European project started in September 2013, which aims to develop novel load balancing mechanisms that can be applied during runtime in a wide range of parallel and high performance computing systems, allowing for a fine-tuning of the trade-off between performance guarantees and system efficiency according to the application needs. The duration of the project is 36 months.

• Aicas GmbH (Germany)
• CNRS (France)
• HLRS (Germany)
• The Open Group (UK)
• Rheon Media Ltd (UK)
• Robert Bosch (Germany)
• University of York (UK)

Brief description. Drawing strengths from the complementary expertise of both groups in the areas of computer architecture exploration, power modeling and 3D integration, the MP@3D collaborative project aims at laying down the foundations of a novel modeling approach for 3D MPSoCs that will permit exploring benefits and innovative techniques for such systems.

• CNRS (France)
• University of Bremen (Germany)

Brief description. The "Famous" project (started on December 1st 2009, for 48 months) aims at introducing a complete methodology that considers the reconfigurability of the hardware as an essential design concept. It proposes the necessary mechanisms to fully exploit such a feature at runtime. The project covers research in system models, compile time and runtime methods, and analysis and verification techniques. These tools should provide high-quality designs with improved designer productivity, while guaranteeing consistency with the initial requirements for adaptability on the expected implementation.

Thus, "Famous" is a research project with almost an immediate industrial impact. Actually, it should make reconfigurable systems design easier and faster. The obtained tool-set is expected to be used by both company designers and academic researchers, especially for modern application systems specific design such as smart camera, image and video processing. It will rely on well-established standards in design community. In practice, modeling will start from very high abstraction levels using an extended version of the UML/Marte standard profile. Then simulation and synthesizable models will be generated by automatic model-to-model transformations, using an MDE approach. These techniques will contribute to shorten drastically time-to-market. The project is seen as a first attempt to explore novel design methodologies and target modern embedded systems architectures.

• The public research labs INRIA Lille - Nord Europe (Lille)
• LabSTICC (Lorient)
• INRIA Rhône-Alpes (Grenoble)
• LE2I University of Bourgogne (Dijon)
• The SME company Sodius SAS (Nantes)

This project was supported by the French STIC Inria-Tunisia program, which aims at promoting the design of metamodels, transformation tools and techniques for the implementation of reconfigurable systems-on-chip.