Portfolio 1

Design Continuum for Next Generation Energy‐Efficient Compute Nodes

CONTINUUM is a project addressing the design of next generation energy-efficient high-performance embedded compute nodes. It focuses at the same time on software, architecture and emerging memory and communication technologies in order to synergistically exploit their corresponding feautures.

The current page highlights the results obtained during the project.


  1. July 2018: A Special Session on CONTINUUM topics during ReCoSoC Symposium - Join us!

  2. March 28/28, 2018: Next project F2F meeting in Montpellier (Cortus)

  3. July 2017: MAGPIE now available for download!

  4. June 27, 2017: MAGPIE tutorial at ComPAS'2017 (Sophia-Antipolis): see presented materials.



  1. -- Abdoulaye Gamatié and Pierre-Yves Péneau. 'Half-Day Tutorial on MAGPIE tool', organized during Conférence d’informatique en Parallélisme, Architecture et Système - ComPAS'17, Sophia-Antipolis, France, June 2017.

Conferences and Workshops

  1. -- Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié 'Partial WCET Estimates and their Applications', Conférence d’informatique en Parallélisme, Architecture et Système - Compas'18, Toulouse, France, July 2018.

  2. -- Junio Ribeiro, Fernando Pereira, Abdoulaye Gamatié and Michael Frank 'A Compiler-Centric Infra-Structure for Whole-Board Energy Measurement on Heterogeneous Android Systems', 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip - ReCoSoC'2018, Lille, France, July 2018.

  3. -- Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, Jose Ignacio Gomez, Gouri Sankar Kar, Arnaud Furnemont, Francky Catthoor, Sophiane Senni, David Novo, Abdoulaye Gamatié and Lionel Torres 'Main Memory Organization Trade-offs with DRAM and STT-MRAM Options based on Extended gem5/NVMain Simulation Framework', Design, Automation & Test in Europe - DATE'2018, Dresden, Germany, March 2018.

  4. -- Pierre-Yves Péneau, David Novo, Florent Bruguier, Lionel Torres, Gilles Sassatelli and Abdoulaye Gamatié 'Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement Policy', International Conference on Architecture of Computing Systems - ARCS'2018, Braunschweig, Germany, April 2018.

  5. -- Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié 'Compile-Time Silent-Store Elimination for Energy Efficiency: an Analytic Evaluation for Non-Volatile Cache Memory', 10th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools - RAPIDO'18, Manchester, United Kingdom, January 2017.
    Portfolio 1
  6. -- Pierre-Yves Péneau, David Novo, Florent Bruguier, Gilles Sassatelli and Abdoulaye Gamatié 'Performance and Energy Assessment of Last-Level Cache Replacement Policies', International conference on Embedded & Distributed Systems - EDiS'2017, Oran, Algeria, December 2017.

  7. -- Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié 'How could compile-time program analysis help leveraging emerging NVM features?', International conference on Embedded & Distributed Systems - EDiS'2017, Oran, Algeria, December 2017.

  8. -- Stefano Bernabovi, Florent Bruguier, Michael Chapman, Abdoulaye Gamatié, Thierry Gil, David Kerr-Munslow, Philippe Naudin, and Gilles Sassatelli'A Low-Power Multicore Architecture at Work', Demo Night at IEEE International Workshop on Signal Processing Systems - SiPS'2017, Lorient, France, October 2017.

  9. -- Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou 'LLVM-based Silent Stores Optimization to Reduce Energy Consumption on STT-RAM Cache Memory', European LLVM Developers Meeting - EuroLLVM'2017, Saarland Informatics Campus, Saarbrücken, Germany, March 2017.

  10. -- Thibaud Delobelle, Pierre-Yves Péneau, Abdoulaye Gamatié, Florent Bruguier, Sophiane Senni, Gilles Sassatelli and Lionel Torres 'MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory Technologies', Workshop on Emerging Memory Solutions - Technology, Manufacturing, Architectures, Design and Test at Design Automation and Test in Europe - DATE'2017, Lausanne, Switzerland, March 2017.

  11. -- Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Péneau, Lionel Torres, Abdoulaye Gamatié, Pascal Benoit and Gilles Sassatelli. 'Embedded Systems to High Performance Computing using STT-MRAM', Design Automation and Test in Europe - DATE'2017, Lausanne, Switzerland, March 2017.

  12. -- Pierre-Yves Péneau, Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres and Sophiane Senni 'Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy Tradeoffs', International Workshop on Power And Timing Modeling, Optimization and Simulation - PATMOS'16, Bremen, Germany, September 2016.

  13. -- Thibaud Delobelle, Pierre-Yves Péneau, Sophiane Senni, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli and Lionel Torres 'Flot automatique d’évaluation pour l’exploration d’architectures à base de mémoires non volatiles', Conférence d’informatique en Parallélisme, Architecture et Système - Compas'16, Lorient, France, July 2016.


  1. -- 'MAGPIE: Manycore Architecture enerGy and Performance evaluatIon Environment', see MAGPIE homepage,  and a related announcement in MRAM-info news, June 2017.

  2. -- 'Silent store elimination in LLVM', see the corresponding homepage,  August 2017.

Invited talks

  1. -- Abdoulaye Gamatié. 'Leveraging Emerging Non-Volatile Memory Technologies for Energy-Efficient System Design', invited talk at FETCH 2018 (Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes), Saint-Malo - France,  January 2018.

  2. -- Lionel Torres. 'Beyond MRAM, CMOS/Mag integrated electronics', invited talk at Introductory course on Magnetic Random Access Memory (InMram’17), Grenoble - France,  July 2017.

  3. -- Abdoulaye Gamatié. 'Synergistic Design of Energy-Efficient Heterogeneous Compute Nodes', invited keynote at the Annual Symposium of the CNRS research cluster on Systems-on-Chip and Systems-in-Package (GdR SoC-SiP), Bordeaux - France,  June 2017.

  4. -- Rabab Bouziane. 'Silent stores optimization to reduce write activities to non-volatile memory', 12th Meeting of the French Compilation Group , Lyon - France,  June 2017.

  5. -- Erven Rohou. 'NVRAM: New Opportunities for Compilers', invited talk at the Workshop on « Raised Challenges by NVRAM » , Paris - France,  May 2017.

  6. -- Lionel Torres. 'From memory technology and architecture to computing with non-volatile memory', invited talk at 9ème école thématique « Architecture des systèmes matériels et logiciels embarqués, et méthodes de conception associées » (ARCHI’17), Nancy - France,  March 2017.

  7. -- Abdoulaye Gamatié. 'Simulation and Evaluation of Heterogeneous Embedded Multicore Architectures', invited talk at FETCH 2017 (Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes), Mont Tremblant - Québec, Canada,  January 2017.

  8. -- Lionel Torres. 'Processor Architecture Based on MRAM: High Performance Computing and Embedded systems', invited talk at Journées de la section électronique du club EEA 2016: Mémoires émergentes et Memristors pour les technologies de traitement et de stockage de l’information, Marseille - France,  November 2016.

  9. -- Abdoulaye Gamatié. 'Dealing with Energy-Efficiency in Next-Generation Compute Systems', invited talk at IRCICA (Institut de Recherche en Composants logiciels et matériels pour l’Information et la Communication Avancée), Lille - France,  June 2016.



  1. -- D4.2: Preliminary design specifications of the adaptive compute node (October 2017). This deliverable describes the initial design of the heterogeneous multicore compute node under consideration in the CONTINUUM project.

  2. -- D3.2: Evaluation of selected memory and communication technologies and exploitation opportunities in compilation (July 2017). This deliverable is devoted to evaluation of emerging memory and communication technologies w.r.t. performance and energy consumption in multicore heterogeneous systems. From presented results, some opportunities are discussed for leveraging the advantages of such technologies by considering compilation techniques and runtime system management.

  3. -- D1.2: Mid-term progress report (April 2017). This deliverable provides an overview of achieved effort on mid-term of the project.

  4. -- D2.2: Description of specific optimizations for low-power (April 2017). This deliverable is devoted to a study on possible compile-time optimizations that can enable energy-efficiency while exploiting the low leakage power that is inherent to non volatile memories.

  5. -- D4.1: State of the art on performance and power estimation of embedded and high-performance cores (October 2016). This deliverable presents a number of candidate core technologies, mainly from Cortus and ARM. Performance and power consumption numbers are given as an assessment of those technologies. The outcome of this survey will serve in choosing the suitable core technologies in the heterogeneous architecture expected in CONTINUUM.

  6. -- D3.1: Survey on emerging memory and communication technologies (June 2016). This deliverable surveys emerging non-volatile memory technologies and their current usage in computer architectures. It also addresses modern communication technologies, with a special focus on networks-on-chip, which play an important role in communication scalability in multicore/manycore systems.

  7. -- D2.1: Report on the selected relevant metrics: design and implementation choice (March 2016). This deliverable surveys a number of metrics found in literature, which are considered as relevant for assessing performance and energy consumption during studies within the CONTINUUM project.

  8. -- D1.1: Webpage of CONTINUUM Project is operational (November 2015).

Internship reports

  1. -- Thibaud Delobelle. 'Flot d’exploration d’architectures multicoeurs avec mémoires non-volatiles', (in French), LIRMM , Montpellier - France,  January 2016.

  2. -- Marcelo Pereira Novaes. 'Unassisted Code Placement on Embedded Heterogeneous Multi-core Architectures', LIRMM , Montpellier - France,  July 2017.

Funding agency

Portfolio 1

Involved partners