Portfolio 1

Design Continuum for Next Generation Energy‐Efficient Compute Nodes

CONTINUUM is a project addressing the design of next generation energy-efficient high-performance embedded compute nodes. It focuses at the same time on software, architecture and emerging memory and communication technologies in order to synergistically exploit their corresponding feautures.
The current page highlights the results obtained during the project.


  1. March 29/30, 2017: F2F meeting in Montpellier (LIRMM)

  2. Sep. 19/20, 2016: F2F meeting in Montpellier (Cortus)

  3. March 29/30, 2016: F2F meeting in Rennes (Inria)


Conferences and Workshops

  1. -- Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou 'LLVM-based Silent Stores Optimization to Reduce Energy Consumption on STT-RAM Cache Memory', European LLVM Developers Meeting, EuroLLVM'2017, Saarland Informatics Campus, Saarbrücken, Germany, March 2017.

  2. -- Thibaud Delobelle, Pierre-Yves Péneau, Abdoulaye Gamatié, Florent Bruguier, Sophiane Senni, Gilles Sassatelli and Lionel Torres 'MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory Technologies', Workshop on Emerging Memory Solutions - Technology, Manufacturing, Architectures, Design and Test at Design Automation and Test in Europe - DATE'2017, Lausanne, Switzerland, March 2017.

  3. -- Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Péneau, Lionel Torres, Abdoulaye Gamatié, Pascal Benoit and Gilles Sassatelli. 'Embedded Systems to High Performance Computing using STT-MRAM', Design Automation and Test in Europe - DATE'2017, Lausanne, Switzerland, March 2017.

  4. -- Pierre-Yves Péneau, Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres and Sophiane Senni 'Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy Tradeoffs', International Workshop on Power And Timing Modeling, Optimization and Simulation - PATMOS'16, Bremen, Germany, September 2016.

  5. -- Thibaud Delobelle, Pierre-Yves Péneau, Sophiane Senni, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli and Lionel Torres 'Flot automatique d’évaluation pour l’exploration d’architectures à base de mémoires non volatiles', Conférence d’informatique en Parallélisme, Architecture et Système - Compas'16, Lorient, France, July 2016.

Invited talks

  1. -- Lionel Torres. 'From memory technology and architecture to computing with non-volatile memory', invited talk at 9ème école thématique « Architecture des systèmes matériels et logiciels embarqués, et méthodes de conception associées » (ARCHI’17), Nancy - France,  March 2017.

  2. -- Abdoulaye Gamatié. 'Simulation and Evaluation of Heterogeneous Embedded Multicore Architectures', invited talk at FETCH 2017 (Ecole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes), Mont Tremblant - Québec, Canada,  January 2017.

  3. -- Lionel Torres. 'Processor Architecture Based on MRAM: High Performance Computing and Embedded systems', invited talk at Journées de la section électronique du club EEA 2016: Mémoires émergentes et Memristors pour les technologies de traitement et de stockage de l’information, Marseille - France,  November 2016.

  4. -- Abdoulaye Gamatié. 'Dealing with Energy-Efficiency in Next-Generation Compute Systems', invited talk at IRCICA (Institut de Recherche en Composants logiciels et matériels pour l’Information et la Communication Avancée), Lille - France,  June 2016.


  1. -- D2.2: Description of specific optimizations for low-power (April 2017). This deliverable is devoted to a study on possible compile-time optimizations that can enable energy-efficiency while exploiting the low leakage power that is inherent to non volatile memories.

  2. -- D4.1: State of the art on performance and power estimation of embedded and high-performance cores (October 2016). This deliverable presents a number of candidate core technologies, mainly from Cortus and ARM. Performance and power consumption numbers are given as an assessment of those technologies. The outcome of this survey will serve in choosing the suitable core technologies in the heterogeneous architecture expected in CONTINUUM.

  3. -- D3.1: Survey on emerging memory and communication technologies (June 2016). This deliverable surveys emerging non-volatile memory technologies and their current usage in computer architectures. It also addresses modern communication technologies, with a special focus on networks-on-chip, which play an important role in communication scalability in multicore/manycore systems.

  4. -- D2.1: Report on the selected relevant metrics: design and implementation choice (March 2016). This deliverable surveys a number of metrics found in literature, which are considered as relevant for assessing performance and energy consumption during studies within the CONTINUUM project.

Funding agency

Portfolio 1

Involved partners

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