Co-publications

 

Below are reported only co-publications between members of LIRMM and Politecnico di Torino, and/or University of Napoli..

Research Articles published in Peer-Reviewed International Journals

  • [J1] P. Bernardi, M. De Carvalho, E. Sanchez, M. Sonza Reorda, A. Bosio, L. Dilillo, M. Valka, P. Girard, “Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption”, Journal of Low Power Electronics, Vol. 9, N° 2, pp. 253-263, Août 2013.
  • [J2] I. Wali, A. Virazel, A. Bosio, P. Girard, S. Pravossoudovitch et M. Sonza Reorda, “A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores”, JETTA, Journal of Electronic Testing - Theory and Applications, Springer, Vol. 32, N° 2, pp. 147-161, Avril 2016.
  • [J3] A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, M. Sonza Reorda et E. Auvray, “Scan-Chain Intra-Cell Aware Testing”, in IEEE Transactions on Emerging Topics in Computing, vol. 6, no. 2, pp. 278-287, 1 April-June 2018. doi: 10.1109/TETC.2016.2624311.
  • [J4] I. Wali, B. Deveautour, A. Virazel, A. Bosio, P. Girard et M. Sonza Reorda, “A Low-cost Reliability vs. Cost Trade-off Methodology for Selectively Harden Logic Circuits”, Journal of Electronic Testing - Theory and Applications (JETTA), Springer, Vol. 33, N° 1, pp. 25-36, Février 2017. DOI: 10.1007/s10836-017-5640-6
  • [J5] A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi et M. Sonza Reorda, “Microprocessors Testing: Functional meets Structural Test”, Journal of Circuits, Systems, and Computers, Vol. 26, N° 8, Août 2017. DOI: 10.1142/S0218126617400072.
  • [J6] A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi, M. Sonza Reorda et E. Auvray, “Scan-Chain Intra-Cell Aware Testing”, IEEE Transactions on Emerging Topics in Computing, Vol. 6, N° 2, Avril-Juin 2018.
  • [J7] Marcello Traiola, Mario Barbareschi, Alberto Bosio, "Estimating dynamic power consumption for memristor-based CiM architecture". Microelectron. Reliab. 80: 241-248 (2018).
  • [J8] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-formulated Pattern Selection Procedure”, IEEE Transactions on Nanotechnology, Juin 2019, DOI: 10.1109/TNANO.2019.2923040.
  • [J9] M. Traiola, A. Savino et S. D. Carlo, “Probabilistic Estimation of the Application-Level Impact of Precision Scaling in Approximate Computing Applications”, Microelectronics Reliability, Volume 102, 2019, DOI: 10.1016/j.microrel.2019.06.002.
  • [J10] B. Deveautour, A. Virazel, P. Girard, et V. Gherman, “Exploring Advantages of Approximate Computing in Selective Hardening of Arithmetic Circuits”, JETTA, Journal of Electronic Testing - Theory and Applications, Springer, accepté et à paraître, Décembre 2019.
  • [J11] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “A Survey of Testing Techniques for Approximate Integrated Circuits”, Proceedings of the IEEE (IF=10.69), accepté et à paraître, juin 2020.
  • [J12] Alberto Bosio, Mario Barbareschi, “Special Issue on Design, Technology, and Test of Integrated Circuits and Systems”, Journal of Circuits, Systems, and Computers 28(Supplement-1): 1902001:1-1902001:1 (2019).
  • [J13] Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Marti Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo: "SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems". IEEE Trans. Computers 68(5): 765-783 (2019) .

Research Papers published in Formal Proceedings of International Conferences, Symposia and Workshops

  • [C1] S. Bernabovi, P. Bernardi, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, “An Intra-Cell Defect Grading Tool”, 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS), pp. 298-301, Varsovie, Pologne, 23-25 Avril 2014.
  • [C2] A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, P. Bernardi, “A Comprehensive Evaluation of Functional Programs for Power-Aware Test”, IEEE North Atlantic Test Workshop (NATW), pp. 69-72, Wakefield, USA, 14-16 Mai 2014.
  • [C3] A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, et M. Sonza Reorda, “Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing”, EDAA/IEEE/ACM Design Automation & Test in Europe (DATE) Conference, CDRom Proceedings, Grenoble, France, 9-13 Mars 2015.
  • [C4] A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi et M. Sonza Reorda, “Scan-Chain Intra-Cell Defects Grading”, IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Naples, Italie, 21-23 Avril 2015. DOI: 10.1109/DTIS.2015.7127349.
  • [C5] A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi et M. Sonza Reorda, “An effective ATPG flow for Gate Delay Faults”, IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Naples, Italie, 21-23 Avril 2015. DOI: 10.1109/DTIS.2015.7127350.
  • [C6] I. Wali, A. Virazel, A. Bosio, L. Dilillo, P. Girard et M. Sonza Reorda, “Design Space Exploration and Optimization of a Hybrid Fault-Tolerant Architecture”, IEEE International On-Line Testing Symposium (IOLTS), pp. 89-94, Halkidiki, Grèce, 6-8 Juillet 2015.
  • [C7] A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi et M. Sonza Reorda, “An Effective Approach for Functional Test Programs Compaction”, IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Košice, Slovaquie, 20-22 Avril 2016. DOI: 10.1109/DDECS.2016.7482466.
  • [C8] I. Wali, B. Deveautour, A. Virazel, A. Bosio, P. Girard et M. Sonza Reorda, “A Low-cost Selective Hybrid Fault Tolerant Architecture”, IEEE European Test Symposium (ETS), Amsterdam, Pays-Bas, 24-27 Mai 2016.
  • [C9] A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi et M. Sonza Reorda, “Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study”, IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, USA, 11-13 Juillet 2016.
  • [C10] J. Alt, P. Bernardi, A. Bosio, R. Cantoro, H. Kerkhoff, A. Leininger, W. Molzer, A. Motta, C. Pacha, A. Pagani, A. Rohani, R. Strasser, “Thermal issues in test: an overview of the significant aspects and industrial practice”, In IEEE VLSI Test Symposium (VTS), 2016.
  • [C11] P. Bernardi, A. Bosio, G. Di Natale, A. Guerriero, F. Venini, “Faster-than-at-speed execution of functional programs: an experimental analysis”, to appear in the proceedings of the IEEE VLSI-SOC, September 2016.
  • [C12] Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto Bosio, “XbarGen: a Memristor Based Boolean Logic Synthesis tool”, to appear in the proceedings of the IEEE VLSI-SOC, September 2016.
  • [C13] G. Harcha, A. Bosio, P. Girard, A. Virazel et P. Bernardi, “An Effective Fault-Injection Framework for Memory Reliability Enhancement Perspectives”, IEEE International conference on Design & Technology of Integrated Systems in nanoscale era, DOI: 10.1109/DTIS.2017.7930172, Palma de Mallorque, Espagne, 4-6 Avril 2017.
  • [C14] M. Barbareschi, A. Bosio, H. A. Du Nguyen, S. Hamdioui, M. Traiola and E. I. Vatajelu, “Memristive devices: Technology, design automation and computing frontiers,” IEEE International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DOI: 10.1109/DTIS.2017.7930178, Palma de Mallorca, Espagne, 4-6 Avril 2017.
  • [C15] I. Wali, M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Towards Approximation during Test of Integrated Circuits”, IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DOI: 10.1109/DDECS.2017.7934574, Dresde, Allemagne, 19-21 Avril 2017.
  • [C16] M. Traiola, M. Barbareschi and A. Bosio, “Formal Design Space Exploration for memristor-based crossbar architecture,” IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DOI: 10.1109/DDECS.2017.7934557, Dresden, Allemagne, 19-21 Avril 2017.
  • [C17] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Towards Digital Circuit Approximation by exploiting Fault Simulation”, IEEE East-West Design & Test Symposium, DOI: 10.1109/EWDTS.2017.8110108, Novi Sad, Serbie, 29 Sept.-2 Oct., 2017.
  • [C18] T.P. Ho, E. Faehn, A. Virazel, A. Bosio et P. Girard, “An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs”, IEEE International Test Conference, Pheonix, USA, 30 Octobre-3 Novembre 2018.
  • [C19] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Testing Approximate Digital Circuits: Challenges and Opportunities”, IEEE Latin-American Test Symposium, Sao Paulo, Brésil, 12-16 Mars 2018.
  • [C20] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “On the Comparison of Different ATPG approaches for Approximate Integrated Circuits”, IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Budapest, Hongrie, 25-27 Avril 2018
  • [C21] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Mean-Error Metrics Aware Testing of Approximate Integrated Circuits: Challenges and Opportunities”, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Chicago, USA, 8 – 10 Octobre 2018.
  • [C22] Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio, "Synthesis of Finite State Machines on Memristor Crossbars". DDECS 2018: 107-112
  • [C23] Marcello Traiola, Alessandro Savino, Mario Barbareschi, Stefano Di Carlo, Alberto Bosio, "Predicting the Impact of Functional Approximation: from Component- to Application-Level". IOLTS 2018: 61-64
  • [C24] A. Bosio, P. Bernardi, A. Ruospo et E. Sanchez, “A Reliability Analysis of a Deep Neural Network”, Proceedings of IEEE Latin American Test Symposium (LATS), pages 1–6, March 2019.
  • [C25] S. Mhamdi, P. Girard, A. Virazel, A. Bosio et A. Ladhar, “Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip”, Proceedings of IEEE International On-Line Testing Symposium, Rhodes, Grèce, 1-3 Juillet 2019.
  • [C26] Alberto Bosio, Wilson Javier Perez Holguin, Ernesto Sanchez: "Exploiting Approximate Computing to Increase System Lifetime". VLSI-SoC 2019: 311-316
  • [C27] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Achieving Full Gains in Yield for Approximate Circuits: a New Test Application Technique”, Proceedings of EDAA/IEEE/ACM Design Automation & Test in Europe (DATE) Conference, Grenoble, France, 9-13 Mars 2020.

Research Papers published in Informal Proceedings of International Conferences, Symposia and Workshops

  • [In1] M. Traiola, M. Barbareschi and A. Bosio, “Formal Design Space Exploration for memristor-based crossbar architecture,” MTDAC: 4th Workshop on Memristor Technology, Design, Automation and Computing @ HiPEAC17, 23 Janvier 2017, Stockholm, Suède.
  • [In2] I. Wali, M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Can we Approximate the Test of Integrated Circuits?”, 3rd Workshop On Approximate Computing (WAPCO), 25 Janvier 2017, Stockholm, Suède.
  • [In3] M. Traiola, M. Barbareschi and A. Bosio, “A Formal Approach for Design Space Exploration of Memristor-based Crossbar Architecture”, 5th Prague Embedded Systems Workshop (PESW), 29-30 juin 2017, Prague, République Tchèque.
  • [In4] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “Testing Integrated Circuits for Approximate Computing Applications”, 4th Workshop On Approximate Computing (WAPCO), Manchester, Angleterre, 22 Janvier 2018.
  • [In5] M. Traiola, A. Virazel, M. Barbareschi et P. Girard, “On the Testing of Approximate Integrated Circuits for Embedded applications considering Average-Error Metrics”, 3rd Workshop on Approximate Computing (AxC’18), Breme, Allemagne, 31 mai – 1 juin 2018.
  • [In6] M. Traiola, A. Virazel, P. Girard, M. Barbareschi et A. Bosio, “A Novel Test Flow for Approximate Digital Circuits”, EDAA/IEEE/ACM Design Automation & Test in Europe (DATE) Conference, PhD Forum, Grenoble, France, 9-13 Mars 2020.

Presentations in National Events

  • [N1] A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel et P. Bernardi, “Exploiting Functional Programs for Power-Aware Test”, Colloque National du GDR SoC-SiP, Paris, 11-13 Juin 2014.
  • [N2] I. Wali, A. Virazel, A. Bosio, L. Dilillo, P. Girard et M. Sonza Reorda, “A Fault-tolerant Architecture for Pipelined Microprocessor Cores”, Colloque National du GDR SoC-SiP, Paris, 11-13 Juin 2014.
  • [N3] I. Wali, A. Virazel, A. Bosio, L. Dilillo, P. Girard et M. Sonza Reorda, “A Hybrid Fault-Tolerant Architecture for Non-Linear Pipelines”, 18ième Journées Nationales du Réseau Doctoral en Microélectronique, Bordeaux, 5-7 Mai 2015.
  • [N4] A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi et M. Sonza Reorda, “Exploring the Impact of Functional Test Programs Re-Used for At-Speed Testing”, 19ième Journées Nationales du Réseau Doctoral en Microélectronique, Toulouse, 11-13 Mai 2016.
  • [N5] A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi et M. Sonza Reorda, “Exploring the Impact of Functional Test Programs Re-Used for At-Speed Testing”, Colloque National du GDR SoC-SiP, Nantes, 8-10 Juin 2016.
  • [N6] M. Traiola, A. Bosio, P. Girard et A. Virazel, “A Case Study on the Approximate Test of Integrated Circuits”, Colloque National du GDR SoC-SiP, Bordeaux, 14-16 Juin 2017.
  • [N7] B. Deveautour, A. Virazel, A. Bosio et P. Girard, On using Approximate Computing in Duplication Schemes”, Colloque National du GDR SOC2, Paris, 13-15 Juin 2018.
  • [N8] M. Traiola, A. Bosio, P. Girard et A. Virazel, “Automatic Test Pattern Generation for Approximate Integrated Circuits”, Colloque National du GDR SOC2, Paris, 13-15 Juin 2018.
  • [N9] M. Traiola, A. Virazel, P. Girard et A. Bosio, “Test Techniques for Approximate Integrated Circuits”, Colloque National du GDR SOC2, Montpellier, 19-21 Juin 2019.
  • [N10] B. Deveautour, A. Virazel et P. Girard, “On using Approximate Computing in Arithmetic Circuit Duplication Schemes”, Colloque National du GDR SOC2, Montpellier, 19-21 Juin 2019.