Presenter: Nassim RIADI 

Abstract:
During the design and the manufacturing of integrated circuits, risks of IP theft, malicious layout manipulation, over-production or even reverse engineering are undeniable. One possibility of protection is the logic locking. The objective of this thesis, is the analysis of power side channel attacks resilience of advanced Logic Locking schemes and suggestion of new logic locking schemes with countermeasures against side channel attacks. 

Date: Februray 13, 2024 from 2 to 4 pm (salle de séminiaires, LIRMM*)