Presenter: Enrique Vallejo
Abstract:
In this talk I will present some mechanisms designed to reduce latency and area in network-on-chip designs, both in traditional router-based designs and in multi-ring (or routerless) approaches.
In traditional NOCs, router bypass mechanisms are employed to skip some of the router stages when it is safe to do, reducing both latency and dynamic power. I will present single- and multi-hop bypass mechanisms, along with some contributions from our group that improve the efficiency of said mechanisms.
Multi-ring NOCs are alternative low-area interconnections that rely on sets of rings such that any pair
of nodes is directly connected by at least one ring. This design avoids the use of crossbars, arbitration or control signals, significantly reducing area and control overhead. Based on this design, I will present our previous work denoted AffineNOC, which combines routerless NOCs with long channels, similar to the approach in multi-hop bypass. Finally, I will introduce the current work, focused on finding alternative designs for routerless NOCs with long channels.
Date: July17th, 2024