Presenter: Felipe Paiva Alencar
Abstract:
Data retention time is a crucial factor in capacitor-less eDRAM, particularly when operating without a refresh circuit, as this can positively impact Power, Performance, and Area (PPA) metrics. However, this design requires careful management of data lifetime to align with memory retention capabilities. This talk will explore the trade-offs discovered during my master’s internship at imec, where I conducted a detailed analysis of heterogeneous on-chip memory technologies for edge inference architectures. The presentation will cover both the technical insights gained from this study and the framework used — Stream — including the new features I implemented to enable this analysis. By examining retention characteristics, energy consumption, and system latency, the study offers key guidelines for optimizing memory choices in energy-efficient, real-time AI processing for edge devices.
Date: October9, 2024 from 2 to 4 pm (« salle JPN » at Bat 5 (Room 02.022))