Publications

This the list of my scientific contributions since 2007: Journals, Patents, Books and Conference articles.

Journals

[J3EA15] F. Bruguier, P. Benoit, L. Torres, “Formation en Sécurité Numérique : Théorie et Mise en Pratique sous la Forme d’un Stage Technologique”, J3eA 14 2001 (2015), DOI: 10.1051/j3ea/2015028
[TETCSI15] F. Bruguier, P. Benoit, L. Torres, L. Barthe, M. Bourree, V. Lomne, “Cost-effective Design Strategies for Securing Embedded Processors”, IEEE Transactions on Emerging Topics in Computing, doi:10.1109/TETC.2015.2407832

[MIC14] F.L. Kastensmidt , J. Tonfat, T. Both, P. Rech, G. Wirth, R. Reis, F. Bruguier, P. Benoit, L. Torres, C. Frost, “Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs”, Microlectronics Reliability, Elsevier, August 2014
[TCAS13] Mansouri I., Benoit P., Torres L., Clermidy F., “Fine-grain dynamic energy tracking for system-on-chip”, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume:60,  Issue: 6, pp. 356 – 360
[TECS13] Ost L., Mandelli M., Almeida G. M., Moller L., Indrusiak L. S., Sassatelli G., Benoit P., Glesner M., Robert M., Moraes F., “Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach”, journal ACM Transactions on Embedded Computing Systems (TECS), Volume 12 Issue 3, March 2013, Article No. 75
[ESL11] G. Almeida, R. Busseuil, L. Ost, F. Bruguier, G. Sassatelli, P. Benoit, L. Torres, M. Robert, “PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip”, Embedded Systems Letters, IEEE, Volume: PP, Issue:99, ISSN: 1943-0663, DOI: 10.1109/LES.2011.2166373, September 2011, pp. 1-4
[IJES10] P. Benoit, L. Torres, G. Sassatelli, M. Robert, N. Saint-Jean, “Run Time Mapping for Dynamic Reconfiguration Management in Embedded Systems”, International Journal of Embedded Systems (IJES), Inderscience, Volume 4 – Issue 3/4 – 2010, pp. 276-291
[JOLPE10] I. Mansouri, P. Benoit, D. Puschini, L. Torres, F. Clermidy, G. Sassatelli, “Dynamic Energy Optimization in NoC-based System-on-Chips”, Journal of Low Power Electronics JOLPE – Vol. 6, N° 4, December 2010, pp. 564-577
[IJRC09a] G. Almeida, Saint-Jean Nicolas, Varyani Sameer, G. Sassatelli, P. Benoit, L. Torres, “An Adaptive Message Passing MPSoC Framework”, Hindawi International Journal of Reconfigurable Computing, Volume 2009, 242981 (2009) 18, pp. 1-18
[IJRC09b] Zipf P., Sassatelli G., Utlu N., Saint-Jean N., Benoit P., Glesner M., “A Decentralized Task Mapping Approach for Homogeneous Multi-Processor Network-On-Chips”, International Journal of Reconfigurable Computing, Volume 2009, 453970 (2009), pp. 1-10
[IJRC08] D. Puschini, P. Benoit, F. Clermidy, G. Sassatelli, “A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC”, International Journal of Reconfigurable Computing, Volume 2008, 403086 (2008), pp. 1-10

Books and book chapters
[SPRINGER12] Pascal Benoit, Gilles Sassatelli, Philippe Maurine, Lionel Torres, Nadine Azemard, Michel Robert, Fabien Clermidy, Marc Belleville, DiegoPuschini, Bettina Rebaud, Olivier Brousse, and Gabriel MarchesanAlmeida, “Towards Autonomous Scalable Integrated Systems”, Design Technology for Heterogeneous Embedded Systems, Nicolescu, Gabriela; O’Connor, Ian; Piguet, Christian (Eds.), SPRINGER, ISBN 978-94-007-1124-2, pp. 63-90

[SPRINGER11a] E. Wanderley, R. Vaslin, J. Crenne, P. Cotret, G. Gogniat, J.-P. Diguet, J.-L. Danger, P. Maurine, V. Fischer, B. Badrignans, L. Barthe, P. Benoit, and L. Torres, “Security FPGA Analysis”, Security trends for FPGAs, Badrignans, B.; Danger, J.L.; Fischer, V.; Gogniat, G.; Torres, L. (Eds.), 1st Edition., 2011, SPRINGER, ISBN 978-94-007-1337-6
[SPRINGER11b] J.-L. Danger, S. Guilley, L. Barthe, and P. Benoit, “Countermeasures Against Physical Attacks in FPGAs”, Security trends for FPGAs, Badrignans, B.; Danger, J.L.; Fischer, V.; Gogniat, G.; Torres, L. (Eds.), 1st Edition., 2011, SPRINGER, ISBN 978-94-007-1337-6
[SPRINGER11c] B. Badrignans, F. Devic, G. Sassatelli, L. Torres and P. Benoit, “Embedded Systems Security for FPGA”, Security trends for FPGAs, Badrignans, B.; Danger, J.L.; Fischer, V.; Gogniat, G.; Torres, L. (Eds.), 1st Edition., 2011, SPRINGER, ISBN 978-94-007-1337-6

[SPRINGER10] L. Torres, P. Benoit, G. Sassatelli, M. Robert, D. Puschini, F. Clermidy, “An Introduction to Multiprocessor System-on-Chip: Trends and Challenges”,Multiprocessor System-on-Chip Hardware Design and Tool Integration, M. Hübner, J. Becker (Eds.), 1st Edition, 2011, SPRINGER, ISBN: 978-1-4419-6459-5 pp. 1-24

[ISVLSI08]A. Smailagic, L. Torres, I. O’Connor, P. Benoit, A. Mukherjee, “IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, Trends in VLSI Technology and Design”, IEEE Computer Society, 2008, ISBN: 978-0-7695-3170-0

[RECO07] Benoit P., Sassatelli G., Glesner M., Bobda C., “Reconfigurable Communication-Centric SoCs”, 2007, ISBN: 2-9517461-3-X

Patents

[PAT14] Mansouri I., Clermidy F., Benoit P., “System and method for designing digital circuitry with an activity sensor“, US 8782592 B2, US, 15/07/2014
[PAT11b] Mansouri I., Clermidy F., Benoit P., “Système et procédé de conception de circuit numérique à capteur d’activité”, 1160261, France, 10/11/2011
[PAT11a] Mansouri I., Clermidy F., Benoit P., “Système et procédé de conception de circuit numérique à capteur d’activité, circuit numérique correspondant”, 1160267, France, 10/11/2011
[PAT10] Puschini D., Clermidy F., Benoit P., “Method for Optimising the Operation of a Multi-Processor Integrated Circuit, and Corresponding Integrated Circuit”, PCT/FR2009/050581, 2010

Conferences

[ISVLSI15] Jerome Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, and Mario Barbareschi, “Digital Right Management for IP Protection”, ISVLSI 2015, Montpellier, France
[REC15] Druyer, R.; Torres, L.; Benoit, P.; Bonzom, P.V.; Le-Quere, P., “A survey on security features in modern FPGAs,” in Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015 10th International Symposium on , vol., no., pp.1-8, June 29 2015-July 1 2015, doi: 10.1109/ReCoSoC.2015.7238102
[NEWCAS15] Yeter Akgul, Diego Puschini, Lionel Vincent, Pascal Benoit, Mauricio Altieri Scarpato, “Energy-efficient control through power mode placement with discrete DVFS and Body Bias”,  13th IEEE International NEWCAS Conference 2015
[DTIS15]  Maha Kooli, Alberto Bosio, Pascal Benoit, “Software Testing and Software Fault Injection”, 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era April 20-24, 2015, Napoli, Italy
[TRUDEVICE15] Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres,“Ring Oscillators Analysis for FPGA Security Purposes”, 3rd TRUDEVICE Workshop, March 13, 2015, Grenoble (France)

[ESR14] F. L. Kastensmidt, J. Tonfat, T. Both, P. Rech, G. Wirth, R. Reis, F. Bruguier, P. Benoit, L. Torres, C. Frost, ESREF 2014, 25th EUROPEAN SYMPOSIUM ON RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS
[FPL14b] Abdulazim Amouri, Florent Bruguier, Saman Kiamehr, Pascal Benoit, Lionel Torres, Mehdi Tahoori, “Aging Effects in FPGAs: an Experimental Analysis”, FPL’14: Field Programmable Logic and Applications (2014), Germany, to be published
[FPL14a] Mohamad Najem, Pascal Benoit, Gilles Sassatelli, Florent Bruguier, Lionel Torres, “Method for Dynamic Power Monitoring on FPGAs”, FPL’14: Field Programmable Logic and Applications (2014), Germany, to be published
[DAC14]  Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro Panades, Pascal Benoit, Lionel Torres, “Power management through DVFS and dynamic body biasing in FD-SOI circuits”, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), DAC 2014, 1-6
[Reco14] Maha Kooli, Pascal Benoit, Giorgio Di Natale, Volkmar Sieh and Lionel Torres, “Fault Injection Tools Based on Virtual Machines”, 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’2014)
[ETS14] F. L. Kastenschmidt, J. Tonfat, T. Both, P. Rech, G. Wirth, R. Reis, F. Bruguier, P. Benoit, L. Torres, C. Frost, “Analyzing the Impact of Aging and Voltage Scaling under Neutron-induced Soft Error Rate in SRAM-based FPGAs”, 19th IEEE European Test Symposium, May 26-30, 2014
[FETCH14] Benoit P., “Self-Adaptive Systems: Trends and Challenges”,  2014, FETCH, Ottawa, Canada Invited Talk

[PATMOS13] Y. Akgul, D. Puschini, S. Lesecq, E. Beigne, P. Benoit, L. Torres, “Methodology for Power Mode Selection in FD-SOI circuits with DVFS and Dynamic Body Biasing”, The International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2013
[ISVLSI13] J. F. Tarrillo, J. Tonfat, R. Reis, F. Kastensmidt, F. Bruguier, M. Bourrée, P. Benoit and L. Torres, “Using Electromagnetic Emanations for Variability Characterization in Flash­Based FPGAs”, Symposium on VLSI, 2013. ISVLSI ’13. IEEE Computer Society Annual, 2013, pp.
[FETCH13] Benoit P., “Distributed Approaches for Self-Adaptive Embedded Systems”,  2013, FETCH, Invited Talk

[ERSA12] Benoit P., “Distributed Approaches for Self-Adaptive Embedded Systems”, WORLDCOMP 2012, ERSA, Invited Talk
[FPL12] Devic F., Torres L., Crenne J., Badrignans B., Benoit P., “Secure DPR: Secure Update Preventing Replay Attacks for Dynamic Partial Reconfiguration”, FPL’12: Field Programmable Logic and Applications (2012), Norway, pp. 57-62
[EWME12]  Bourrée M., Benoit P., Torres L., Maurine P., “SECNUM: an Open Characterizing Platform for Integrated Circuits“, EWME 2012
[FTFC12] Akgul Y., Puschini D., Lesecq S., Miro-Panades I., Benoit P., Torres L., Beigne E., “Power Mode Selection in Embedded Systems with Performance”, FTFC 2012, Low Voltage Low Power Conference, 2012, France 
[DATE12] Perin G., Torres L., Benoit P., Maurine P., “Amplitude Demodulation-based EM Analysis of different RSA implementations”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 1167 – 1172, Best Paper Award Candidate

[REC11] Busseuil R., Barthe L., Almeida G. M., Ost L., Bruguier F., Sassatelli G., Benoit P., Robert M., Torres L., “Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration”, IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 357-362
[FPL11a] Barthe L., Cargnini L. V., Benoit P., Torres L., “Optimizing an Open-Source Processor for FPGAs: A Case Study”, IEEE FPL’11: Field Programmable Logic and Applications (2011), Greece, pp. 551-556
[FPL11b] Bruguier F., Benoit P., Maurine P., Torres L., “A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis”, IEEE FPL’11: Field Programmable Logic and Applications (2011), Greece, pp. 20-23
[VARI11] Bruguier F., Benoit P., Maurine P., Torres L.,“A novel Process Characterisation Method for FPGAs based on Electromagnetic Analysis”, VARI 2011, Grenoble, France
[JNRDM11] Bruguier F., Benoit P., Torres L.,“Capteurs Numériques pour la Gestion de Variations sur Circuits Logiques Programmables”, JNRDM 2011, Paris, France
[ISCAS11a] N. Hébert, G. M. Almeida, P. Benoit, G. Sassatelli, L. Torres, “Evaluation of a Distributed Fault Handler Method for MPSoC”, IEEE International Symposium on Circuits and Systems (ISCAS), May 15-18, 2011, Rio de Janeiro, Brazil, pp. 2329-2332
[ISCAS11b] G. M. Almeida, R. Busseuil, E. A. Carara, N. Hébert, P. Benoit, G. Sassatelli, F.G. Moraes, L. Torres, “Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip”, IEEE International Symposium on Circuits and Systems (ISCAS), May 15-18, 2011, Rio de Janeiro, Brazil, pp. 1500-1503
[RAW11a] L. Barthe, L. V. Cargnini, P. Benoit and L. Torres, “The SecretBlaze: A Configurable and Cost-Effective Open-Source Soft-Core Processor”, 25th IEEE International Parallel & Distributed Processing Symposium, May 16-20, 2011, Anchorage (Alaska) USA, pp. 310-313
[RAW11b] C. Roth, G. M. Almeida, O. Sander, L. Ost, N. Hebert, G. Sassatelli, P. Benoit, L. Torres and J. Becker, “Modular Framework for Multi-Level Multi-Device MPSoC Simulation”, 25th IEEE International Parallel & Distributed Processing Symposium, May 16-20, 2011, Anchorage (Alaska) USA, pp. 146-142
[RAW11c] Becker J., Benoit P., Cumplido R., “RAW Introduction”, IPDPS Workshops, 25th IEEE International Parallel & Distributed Processing Symposium, May 16-20, 2011, Anchorage (Alaska) USA, pp. 125-127

[ATS10] N. Hébert, P. Benoit, G. Sassatelli, L. Torres, “D-Scale: A Scalable System-Level Dependable Method for MPSoCs,” 19th IEEE Asian Test Symposium, 2010,  pp.198-205
[REC10b] N. Hébert, P. Benoit, G.M. Almeida, G. Sassatelli, L. Torres, “A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC”, IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2010 , pp. 346 – 351
[REC10a] G.M. Almeida, S. Varyani, R. Busseuil, N. Hebert, G. Sassatelli, P. Benoit, L. Torres, M. Robert, “Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism”, IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2010 , pp. 382 – 387
[SOCC10] Mansouri I., Clermidy F., Benoit P., Torres L., “A Run-time Distributed Cooperative Approach to Optimize Power Consumption in MPSoCs”, SOCC’10: 23th IEEE International SOC Conference, United States, pp. 25-30
[FPL10] Barthe L., Benoit P., Torres L., “Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures”, IEEE FPL’10: Field Programmable Logic and Applications (2010), Italy, pp. 139-144 Best Paper Award Candidate
[SBCCI10] G.M. Almeida, S. Varyani, R. Busseuil, G. Sassatelli, P. Benoit, L. Torres, E.A. Carara, F.G. Moraes, “Evaluating the Impact of Task Migration in Multi-Processor Systems-on-Chip”, ACM 23rd Symposium on Integrated Circuits and Systems Design (SBCCI’2010). September, 2010. Sao Paulo, Brazil, pp. 73-78
[ISVLSI10a] I. Mansouri, C. Jalier, F. Clermidy, P. Benoit, L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory”,  VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on, 2010 , pp. 422 – 427
[ISVLSI10b] C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, L. Torres, “A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio”, VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on, 2010, pp. 345 – 350
[DATE10] C. Jalier, D. Lattard, A.A. Jerraya, G. Sassatelli, P. Benoit, L. Torres, “Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem”,  Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, pp. 184 – 189
[DASIP10] E. Faure, G.M. Almeida, M. Benabdenbi, P. Benoit, F. Clermidy, F. Pêcheux, G. Sassatelli, L. Torres, “An in-memory monitoring database for self adaptive MP2SoCs” , Design and Architectures for Signal and Image Processing (DASIP), 2010 Conference on, 2010 , pp. 97 – 104
[GDR10a] L. Barthe, P. Benoit, L. Torres, “Side-Channel Attacks on Embedded Systems”,  Colloque National du GDR SOC-SIP, Cergy, France, 9-11 juin 2010
[GDR10b] S. Varyani, G. Marchesan Almeida, R. Busseuil, G. Sassatelli, P. Benoit, L. Torres, “Exploration of Virtualization Techniques for Achieving Adaptability in Heterogeneous MPSoCs”, Colloque National du GDR SOC-SIP, Cergy, France,  9-11 juin 2010
[GDR10c] F. Bruguier, P. Benoit, L. Torres, “AVariabilityCompensationFlowforFPGAs”, Colloque National du GDR SOC-SIP, Cergy, France, 9-11 juin 2010
[RECO10a] Bruguier F., Benoit P., Torres L., “Investigation of Digital Sensors for Variability Characterization on FPGAs”,  ReCoSoC’10: 5th International Workshop on Reconfigurable Communication-Centric Systems on Chip, France, pp. 95-100
[RECO10b] Busseuil R., Marchesan Almeida G., Varyani S., Sassatelli G., Benoit P., “A Self-Adaptive Communication Protocol Allowing Fine Tuning Between Flexibility and Performance in Homogeneous MPSoC Systems”,  Reconfigurable Communication-centric Systems on Chip, Allemagne, pp. 1-6
[ISCAS10] C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, L. Torres, “Flexible and distributed real-time control on a 4G telecom MPSoC”,  Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 3961 – 3964
[VSLI10] Poucheret F., Barthe L., Benoit P., Torres L., Maurine P., Robert M., “Spatial EM Jamming: a Countermeasure Against EM Analysis ?”,  VLSI-SoC’10: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, Spain, pp. 105-110

[SOC09] D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, “Adaptive energy-aware latency-constrained DVFS policy for MPSoC”, 2009 IEEE International SOC Conference (SOCC), IEEE, 2009, pp. 89-92
[DATE09] D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, “Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC”, Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE ’09., 2009, pp. 1564-1567
[GDR09] Almeida G., Varyani S., Sassatelli G., Busseuil R., Benoit P., Torres L., “Self-adaptability in Multi-processor Embedded Systems”,  Colloque GDR SoC SiP 2009, France
[GRETSI09] Nicolas Hebert, Lionel Torres, Gilles Sassatelli, Pascal Benoit, “Une approche pour la fiabilité des plateformes Multiprocesseurs”, 22ème édition du colloque GRETSI, Dijon, 2009
[JNRDM09] Nicolas Hebert, Lionel Torres, Gilles Sassatelli, Pascal Benoit, “Etude de la fiabilité sur la plateforme MP-SoC HS-Scale”, JNRDM – 12ème édition Journées Nationales du Réseau Doctoral de Microélectronique, Lyon, 2009

[REC08] D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, “Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC”, 2008 International Conference on Reconfigurable Computing and FPGAs, IEEE, 2008, pp. 235-240
[ISVLSI08a] N. Saint-Jean, P. Benoit, G. Sassatelli, L. Torres, and M. Robert, “MPI-Based Adaptive Task Migration Support on the HS-Scale System”, Symposium on VLSI, 2008. ISVLSI ’08. IEEE Computer Society Annual, 2008, pp. 105-110
[ISVLSI08b] D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, “Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory”, Symposium on VLSI, 2008. ISVLSI ’08. IEEE Computer Society Annual, 2008, pp. 375-380, (nominated for the best paper award)
[FPL08a] D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, and L. Torres, “Convergence analysis of run-time distributed optimization on adaptive systems using game theory”, 2008 International Conference on Field Programmable Logic and Applications, IEEE, 2008, pp. 555-558
[FPL08b] N. Saint-Jean, G. Sassatelli, P. Benoit, L. Torres, and M. Robert, “Bio-inspiration helps computers: A new machine”, 2008 International Conference on Field Programmable Logic and Applications, IEEE, 2008, pp. 697-698
[RECO08a] Zipf P., Sassatelli G., Utlu N., Saint-Jean N., Benoit P., Glesner M., “A Novel Task Allocation Approach for Homogeneous MPSOC”, ReCoSoC’08: Reconfigurable Communication−Centric SoCs 2008, ISBN 978-84-691-3603-4, 9-11 juillet 2008, Barcelone, Espagne, pp. 40−47
[RECO08b] G. Almeida, Saint-Jean Nicolas, Varyani Sameer, G. Sassatelli, P. Benoit, L. Torres, “Exploration of Task Migration Policies on the HS-Scale System”, ReCoSoC’08: Reconfigurable Communication−Centric SoCs 2008, ISBN 978-84-691-3603-4, 9-11 juillet 2008, Barcelone, Espagne, pp. 48−54

[SAMOS07] N. Saint-Jean, P. Benoit, G. Sassatelli, L. Torres, and M. Robert, “Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems”, 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IEEE, 2007, pp. 88-95
[ISVLSI07] N. Saint-Jean, G. Sassatelli, P. Benoit, L. Torres, and M. Robert, “HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI ’07), IEEE, 2007, pp. 21-28
[FCCM07] G. Sassatelli, N. Saint-Jean, P. Benoit, L. Torres, M. Robert, C. Woszezenki, I. Grehs, and F. Moraes, “Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs”, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), IEEE, 2007, pp. 295-296
[RECO07] N. Saint-Jean, Jalier C., G. Sassatelli, P. Benoit, L. Torres, and M. Robert, “HS Scale: A Run-Time Adaptable MP-SoC Architecture”, ReCoSoC’07: Reconfigurable Communication-Centric SoCs 2007, Montpellier, France, pp. 39-46