Presenter: Luis Bertran Alvarez (2nd year PhD student)
Abstract:
The increasing demand for computation in today’s world has led to the emergence of new technologies that provide various approaches in High Performance Computing (HPC) and data centers. HPC and data centers are becoming more heterogeneous, and maintaining high performance in such systems relies mainly on the interconnect. Novel types of interconnects are emerging, and major cloud providers are collaborating to establish different standards. However, there is currently a lack of accurate, freely available, and realistic simulation models for coherent chip-to-chip interconnects. To address this gap, our project aims to develop a simulation model specifically designed for the gem5 simulator.
This talk will focus on the concept of cache coherence in modern multi-core systems, including the reasons and strategies for expanding to multi-chip architectures. Additionally, we will provide a presentation of the development ecosystem associated with the gem5 simulator.
Date: June 21, 2023 from 2 to 4 pm (salle de séminiaires, LIRMM*)