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Welcome to RecoSoC'2014!

Over the past decade ReCoSoC has established itself as a reference international event for research in the areas of reconfigurable and communication-centric systems-on-chip. Its informal and dynamic philosophy encourages technical and scientific interactions of both academic and industrial participants through presentations and special sessions reporting latest advances in the related areas.

ReCoSoC'2014 will be held in Montpellier, France.

All accepted papers will be published in IEEE Xplore. In addition authors of the best papers will be invited to submit an extended versions of their papers for publication in special issue of a journal to be announced at a later point in time.

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Program of the Symposium

Monday, May 26th
08:15-08:45 Registration
(Room: Amphithéatre d'Anatomie)

Keynote 1: Embedded AI with humans in the loop

Andres Perez-Uribe, University of Applied Sciences Western Switzerland
Moderator: Manfred Glesner
(Room: Amphithéatre d'Anatomie)

10:15-10:45 Coffee break

S1: Design and exploration
Session Chair: Pascal Benoit
(Room: Amphithéatre d'Anatomie)

Exploring Alternate Trade-offs of Placement Quality versus Runtime in Simulated Annealing Algorithm to speedup placement in FPGAs. Bagar Raza, Husain Parvez and Muhammad Mohiuddin

A Prototyping Platform for Virtual Reconfigurable Units. Loic Lagadec, Jean-Christophe Le Lann and Théotime Bollengier

SoCRocket - A Virtual Platform for the European Space Agency's SoC development. Thomas Schuster, Rolf Meyer, Rainer Buchty, Luca Fossati and Mladen Berekovic

S2: Network on chip
Session Chair: Alberto Garcia Ortiz
(Room: Dugès)

Low Overhead Predictability Enhancement in Non-preemptive Network-On-Chip Routers using Priority Forwarded Packet Splitting (PFS). Bharath Sudev and Leandro Soares Indrusiak

LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip. Kris Heid, Haoyuan Ying, Christian Hochberger and Klaus Hofmann

A Hardware/Software Co-Design Reconfigurable Network-on-Chip FPGA Emulation Method. Haoyuan Ying, Thomas Hollstein and Klaus Hofmann

12:00-13:30 Lunch break

Special Session – Emerging Technologies
Organizer: S. Le Beux. Moderator: I. O'Connor
(Room: Amphithéatre d'Anatomie)

3D technologies for reconfigurable architectures. F. Clermidy, O. Turkyilmaz, O. Billoint, PE Gaillardon

Novel Configurable Logic Block Architecture Exploiting Controllable-Polarity Transistors. Pierre-Emmanuel Gaillardon, Xifan Tang, Giovanni De Micheli

Emerging Non-Volatile Memory Technologies for Future Low Power Reconfigurable System. Ali Ahari, Hossein Asadi, Mehdi Tahoori

A Reconfigurable Optical Network on Chip for Streaming Applications. Sébastien Le Beux, Hui Li and Ian O’Connor


Poster introduction
(Room: Amphithéatre d'Anatomie)

Reconfigurable Bus Monitor Tool Suite for On-Chip SoC for Performance and Protocol Monitoring. Ping-Chung Lee and Ing-Jer Huang

Design-Space Exploration between FPGA and ASIF. Muhammad Amin Qureshi and Husain Parvez

A Reconfigurable FPGA Embedded System Design for Ultrasound Guided Waves Testing - An Industrial Case Study. Lei Zhang and Wamadeva Balachandran

Interrupt aware Queue Implementation for Energy Efficient Multitasking Systems based on Cortex-M3 Architecture. Gregor Rebel, Francisco J. Estevez, Tsekoura Ioanna, Ingo Schulz and Peter Gloesekoetter

General Solutions for MTTF and Steady-State Availability of NMR Systems.Moslem Amiri and Vaclav Prenosil

A Based-FPGA Dynamic Power Management for Wireless Sensor Network Results of the art.Alexandre Silva and Fabio Pereira

A Review on Wireless Sensor Node Architectures.Fatma Karray, Mohamed Wassim Jmal, Abdulfattah Mohammad Obeid, Mohammed Abid and Mohammed S. Bensaleh

15:00-15:45 Coffee break / Poster session

S3:Manycore and multitasking
Session Chair: Vianney Lapotre
(Room: Amphithéatre d'Anatomie)

HNCP-II: A 16-core microprocessor ASIC for image processing algorithms. Mohamed Amine Boussadi, Thierry Tixier, Alexis Landrault and Jean-Pierre Derutin

MRAPI Resource Management Layer on Reconfigurable Systems-on-Chip. Laurent Gantel, Benkhelifa Mohamed El Amine, Francois Verdier and Fabrice Lemonnier

A reconfigurable distributed architecture for clock generation in large many-core SoC. Chuan Shan, Dimitri Galayko, François Anceau and Eldar Zianbetov

      S4: Reliability
Session Chair: Leonardo Zordan
(Room: Dugès)

Reliably Prototyping Large SoCs Using FPGA Clusters. Paul Fox, A. Theodore Markettos and Simon Moore

Fault Injection Tools Based on Virtual Machines. Maha Kooli, Pascal Benoit, Giorgio Di Natale, Volkmar Sieh and Lionel Torres

17:00-19:00 Visit of the anatomical museum of the faculty
19:00-20:30 Welcome Cocktail

Tuesday, May 27th

S5: Dynamic reconfiguration
Session Chair: Luciano Ost
(Room: Amphithéatre d'Anatomie)

An Application Scenario for Dynamically Reconfigurable FPGAs. Fynn Schwiegelshohn and Michael Huebner

Leveraging Partial Dynamic Reconfiguration on Zynq SoC FPGAs. Kurt Franz Ackermann and Jaime Correa Rodriguez

Communication-Centric Design for FMC based I/O System. Mokhtar Bouain, Viswanathan Venkatasubramanian, Ben Atitallah Rabie and Jean-Luc Dekeyser

      S6: New technologies
Session Chair: Lionel Torres
(Room: Dugès)

A coding-based configurable and asymmetrical redundancy scheme for 3D interconnects. Christof Osewold, Wolfgang Büter and Alberto García-Ortiz

Non-Intrusive DVFS Emulation in gem5 with Application to Self-Aware Architectures. Parham Haririan and Alberto Garcia-Ortiz

Power efficient Thermally Assisted Switching Magnetic memory based memory systems. Sophiane Senni, Lionel Torres, Gilles Sassatelli, Anastasiia Bukto and Bruno Mussard
10:15-10:45 Coffee break
Keynote 2: From M2M to Virtual Continuum
[how IoT can enable a new wealth of applications and business models]

Roberto Minerva, Telecom Italia
Moderator: Lionel Torres
(Room: Amphithéatre d'Anatomie)

12:00-13:30 Lunch break / Panel

Special Session – Internet of Things part 1

Organizer / Moderator: L. Torres
(Room: Amphithéatre d'Anatomie)

13:30 – 13:45: IoT Introduction & vision. Olivier Carmona, Awox

13:45 – 14:15: Bringing Internet of Things to Life. Patrizio Piasentin, Silicon Labs

14:15 – 15:00: Wireless sensor networks and Internet of things : the new challenges. Nathalie Mitton, INRIA

15:00 – 15:15: Introduction demos.
From Intel: Machine2Machine Demonstration.
From Cyleone Company: Drone Demonstration.

15:15-15:45 Coffee break / Demo Intel & Cycleone / Poster

Special Session – Internet of Things part 2
Organizer / Moderator: L. Torres
(Room: Amphithéatre d'Anatomie)

15:45 – 16:05: A RFID-enabled Sensor Platform for Pervasive Monitoring. Arnaud Vena, Brice Sorli, Alain Fouccaran, Yassin Belaizi

16:05 – 16:25: Incremental checkpointing of program state to NVRAM for transiently-powered systems. Fayçal Ait Aouda, Kevin Marquet, Guillaume Salagnac

16:25 – 16:45: A Hierarchical Reconfigurable Micro-coded Multi-core Processor for IoT Applications. Ning Ma, Zhuo Zou, Zhonghai Lu, Lirong Zheng, Stefan Blixt

16:45 – 17:05: Using JSON to manage Communication between Services in the Internet of Things. Philipp Wehner, Christina Piberger, Diana Göhringer

17:05 – 17:25: New Paradigms for Access Control in Constrained Environnements. Abdelkarim Cherkaoui, Lilian Bossuet, Ludwig Seitz, Goran Selander and Ravishankar Borgaonkar

19:30-... Social Event: Diner at restaurant l’Insensé (at Musée Fabre)
Address: 39 Boulevard des Bonnes Nouvelles in Montpellier

Wednesday, May 28th

Special Session – DreamCloud
Organizer / Moderator: Leandro Indrusiak
(Room: Amphithéatre d'Anatomie)

Dynamic Management of Multikernel Multithread Accelerators Using Dynamic Partial Reconfiguration. Alfonso Rodriguez, Juan Valverde, Eduardo de La Torre and Teresa Riesgo

Feedback-Based Admission Control for Task Allocation. Piotr Dziurzanski, Hashem Ali Ghazzawi and Leandro Indrusiak

10:15-10:45 Coffee break

S7: Simulation and modelling
Session Chair: Abdoulaye Gamatié
(Room: Amphithéatre d'Anatomie)

Inexact End-to-End Response Time Analysis as Fitness Function in Search-based Task Allocation Heuristics for Hard Real-time Network-on-Chips. Yunfeng Ma, Norazizi Sayuti and Leandro Indrusiak

Multi-shape Tasks Scheduling for Online Multitasking on FPGAs. Guy Wassi, Amine Benkhelifa, Geoff Lawday, François Verdier and Samuel Garcia

Reconciling performance and predictability on a many-core through off-line mapping. Thomas Carle, Manel Djemal, Daniela Genius, François Pêcheux, Dumitru Potop Butucaru, Robert de Simone, Franck Wajsbürt and Zhen Zhang

An evaluation of energy efficient microcontrollers. Ioanna Tsekoura, Gregor Rebel, Peter Gloesekoetter and Mladen Berekovic

12:00-12:20 Closing session
12:20-13:30 Lunch break