General goals

In the period 2005 – 2008, the CMOS technology 65nm will become available and 45nm will be developed. Furthermore, process options will be developed for 90nm. As documented in the ITRS roadmap , these new technologies impose new challenges on test methodology, triggered by an increasing number of gates per chip, smaller dimensions and new defect mechanisms. This is a real challenge, since the complexity of test-generation grows exponentially with the number of gates . With today’s test methodology, it will not be possible to achieve a high test-coverage and fast ramp-up at acceptable cost. This is confirmed by the Medea+ Design Automation (EDA) Roadmap , identifying nine areas for test innovations.

The European microelectronics companies AMIS, Infineon, NXP and ST intend to strengthen and realign their efforts dedicated to testing spent in Medea+ phase 1. They recognized that it is most efficient to build from the results of the projects Technodat and Associate in a single, focused project, NanoTEST, under Medea+ phase 2. The consortium is a mix of five large firms, two SMEs and three institutes. This guarantees efficient know-how transfer from academic research and industrial R&D down to production level, e.g. at ST/NXP/Motorola fab in Crolles (F), Infineon fabs in Villach (A) and Corbeil-Essonnes (F), NXP fabs in Nijmegen (NL) and Caen (F), AMIS fab in Oudenaarde (B).

NanoTEST will directly contribute to the commercial success of the European microelectronics industry in applying their new wafer and packaging technologies, targeting not only system-on-chip (SoC), but also system-in-package (SiP). It addresses two of the three identified areas of potential solutions of the ITRS test roadmap (see Figure 1). It will create breakthroughs in test, in the area of costs as well as achieved quality and time-to-market. The activities are split in three discipline-orientated work packages addressing the technology, design-for-test and tester disciplines, respectively (illustrated in Table 1).

This will result in:

• Reducing the cost of production testing by a factor of ten. The way to achieve this ambitious goal is to develop new methodologies that enhance tester throughput and reduce tester resources. For example, multi-site testing, low-cost test cells, advanced test interface boards, and test resource reduction by on-chip test provisions that go much further than current design-for-test practices. It is key now to determine the optimum balance between on-chip test provisions and off-chip test equipment. There is a growing market trend towards heterogeneous systems like SiPs in situations where this is more economical than a single SoC. This project also intends to reduce production test costs of SiPs. Issues to be addressed are for example test provisions for intra-package access and inter-die testing, wafer probe technologies, signal integrity issues affecting test, and development of standards.

• Improving the quality of test, despite the fact that occurrence of new defect types in 65nm and 45nm will initially drive the defect levels up. This will be achieved by developing test methodologies for new defect types, as well as extending the use of tester data into the domain of fault diagnosis for fast production ramp-up, characterization and self-repair. Delay fault test strategies play an essential role in covering new defect types. The work on diagnosis will provide the necessary feedback to zero-defect programs, driven by the automotive sector.

• Speeding up the complete design-for-test and test program generation flow by a factor of ten. This challenging goal can be achieved by deploying re-use at the optimum abstraction level. At the same time new methodologies will be developed for future designs, containing for example globally-asynchronous-locally-synchronous circuits, volatile and non-volatile memories, RF, mixed-signal blocks and sensors. Furthermore, tools will be developed to automate mixed-signal test specification and test program generation.

The design-for-test perspective: Design-for-test (DfT) offers powerful techniques to reduce product cost and test complexity. It offers the on-chip infrastructure to perform the tests demanded from the technology perspective. For digital designs, such techniques are much more advanced than for analogue, mixed-signal and RF designs. Examples are modular test and test wrappers standardised under IEEE1500. Although some mixed-signal DfT techniques have been proposed in recent years, they have so far failed to get wide industrial acceptance. The digital domain needs a major step in the development of DfT techniques as well, for example by introducing the use of DfT constraints during the design flow, and new techniques for test resource reduction. This is mainly caused by the growing data volume to be handled by the tester. The growing use of SiPs will drive the need for new design-for-test approaches focusing on intra-package access and testing.

The tester perspective: Dramatic improvements in the area of test engineering are considered indispensable to keep production test costs in-line with market prices. The costs are strongly influenced by the required tester memory size and tester features. Multi-site testing, BIST, advanced wafer probe card technologies will play an important role here. Special attention must be given to the test cost of products that go into low-priced consumer applications. Data sizes to be handled by the tester are growing and test frequencies go up. This becomes unmanageable if nothing is done about it. The link from design to the tester platforms should be improved by making use of standardization on STIL/CTL. Pure ATE aspects are outside the scope of the project (e.g. development of ATE equipment).

The technology perspective, addressed in WP1:
This work package addresses the areas 14.3, defect oriented testing, 14.6, failure analysis and diagnosis, and 14.7, on line testing and fault tolerance, of the Medea+ EDA Roadmap . The innovations proposed are:

• New fault models and implementation of novel defect-based test methods.
• Application of these methods in an early stage of ramp-up in the fab (yield learning).
• New structural test methods for logic, memory, mixed-signal and RF.
• Extension of memory BIST: characterization, diagnosis and self-repair capability.
• Test and diagnosis of dynamic faults and delay faults.

The design-for-test perspective, addressed in WP2:
This work package addresses the areas 14.1, core testing, 14.2, high-level test synthesis, 14.4, automatic test program generation, and 14.9, system in package, of the Medea+ EDA Roadmap. The innovations proposed are:

• Access and control concepts to perform the novel defect-based test methods developed under WP1.
• Test flow based on design constraints and RTL level infrastructure IP blocks such that it can be applied in modern design-synthesis flows.
• Minimise the costs by the right balance between on-chip (WP2) and off-chip (WP3).
• New techniques for test resource reduction, e.g. reduced pin count test, test data compaction, built in self-test and oscillation testing.
• DfT library of on-chip test provisions for embedded analogue, mixed-signal, RF,
  high-speed I/O, FPGA, volatile & non-volatile memory modules, sensors.
• Core-based test approach for mixed-signal blocks. Develop Mixed-signal BIST and BOST for high-resolution ADCs.

The tester perspective, addressed in WP3:
This work package addresses the areas 14.5, test development for SoC, of the Medea+ EDA Roadmap. The innovations proposed are:

• Advanced test interface board and wafer probe card technologies with higher probe count, frequency, signal integrity and power capabilities.
• Multi-site testing for mixed-signal & RF.
• Optimisation of the cost for a testability solution by combining DfT, BIST,
  built-out-self-test (BOST), wrapper-based mixed-signal modular test, and tester instrumentation for various functional blocks, e.g. high-speed I/O, memory,
  mixed-signal, RF. This will enable the use of low-cost test cells.
• Test specification and program generation tools to support the new cost-cutting test approaches (making use of techniques developed under WP1/WP2 and standards).
• SiP test methodology based on a known-good-die approach, involving the innovations to find the cost minimum between chip-level and package-level test efforts.
• Defect models for sensors, addressing new physical domains like magnetic fields.