IEEE 16th International Conference on
Design & Technology of Integrated System
in Nanoscale Era

June 28th - 30th, 2021, Apulia - Italy (Virtually)

Overview of the conference

The aim of the Conference is to cope with the rapidly progressing technology which, today, reaches the nanometer scale. The areas of interest include the design, test and technology of electronic products, ranging from integrated circuit modules and printed circuit boards to full systems and microsystems, as well as the methodologies and tools used in the design, verification and validation of such products.

The papers accepted to the conference will appear in formal IEEE proceedings.

Considering the influence of coronavirus outbreak and travel restrictions, and, with the intent to protect the health and safety to all of the participants, the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, scheduled in June 28th-30th 2021, will be virtualized (the participation of all contributors will be by videoconference).

 When

June 28th - 30th, 2021

 Where

Apulia - Italy (Virtually)

Important dates

Regular Papers

Paper submissions
April 25th, 2021
May 9th, 2021
Notification
June 01st, 2021
Camera ready
June 22nd, 2021

Special Sessions

Special Session abstract submission
April 11th, 2021 April 18th, 2021
Abstract acceptance notification
April 13th, 2021 April 20th, 2021
Special Session paper submission
May 04th, 2021
Special Session paper notification
June 01st, 2021
Camera ready
June 22nd, 2021

Extension to Special Issue

Microelectronics and Reliability ISSN: 0026-2714

The authors that submitted their work at DTIS 2021 are invited to submit an extended version of their papers to a Special Issue of Microelectronics & Reliability journal, Elsevier.

More details here.

Keynotes

Damien Querlioz

Memory-Centric Artificial Intelligence

Speaker: Damien Querlioz

Read abstract
Damien Querlioz is a CNRS Researcher at the Centre de Nanosciences et de Nanotechnologies of Université Paris-Saclay. His research focuses on novel usages of emerging non-volatile memory and other nanodevices, in particular relying on inspirations from biology and machine learning. He received his predoctoral education at Ecole Normale Supérieure, Paris and his PhD from Université Paris-Sud in 2009. Before his appointment at CNRS, he was a Postdoctoral Scholar at Stanford University and at the Commissariat a l'Energie Atomique. Damien Querlioz is the coordinator of the interdisciplinary INTEGNANO research group, with colleagues working on all aspects of nanodevice physics and technology, from materials to systems. He is a member of the bureau of the French Biocomp research network. He has co-authored one book, nine book chapters, more than 100 journal articles, and conference proceedings, and given more than 50 invited talks at national and international workshops and conferences. In 2016, he was the recipient of an ERC Starting Grant to develop the concept of natively intelligent memory. In 2017, he received the CNRS Bronze medal. He has also been a co-recipient of the 2017 IEEE Guillemin-Cauer Best Paper Award and of the 2018 IEEE Biomedical Circuits and Systems Best Paper Award.

When performing artificial intelligence tasks, central and graphics processing units consume considerably more energy for moving data between logic and memory units than for doing actual arithmetic. Brains, by contrast, achieve superior energy efficiency by fusing logic and memory entirely, performing a form of “in-memory” computing. Currently emerging memory nanodevices such as (mem)resistive, phase change, and magnetic memories give us an opportunity to achieve similar tight integration between logic and memory. In this talk, we will look at neuroscience inspiration to extract lessons on the design of in-memory computing systems. We will first study the reliance of brains on approximate memory Continue reading strategies, which can be reproduced for artificial intelligence. We will give the example of a hardware binarized neural network relying on resistive memory. Binarized neural networks are a class of deep neural networks discovered in 2016, which can achieve state-of-the-art performance with a highly reduced memory and logic footprint with regards to conventional artificial intelligence approaches. Based on measurements on a hybrid CMOS and resistive hafnium oxide memory chip exploiting a differential approach, we will see that such systems can exploit the properties of emerging memories without the need for error-correcting codes, and achieve extremely high energy efficiency. Then, we will present a second approach where the probabilistic nature of emerging memories, instead of being mitigated, can be fully exploited to implement a type of probabilistic learning. We show that the inherent variability in hafnium oxide memristors can naturally implement the sampling step in the Metropolis-Hastings Markov Chain Monte Carlo algorithm, and train experimentally an array of 16,384 memristors to recognize images of cancerous tissues using this technique. These results highlight the interest in understanding and embracing the unreliable nature of emerging devices in artificial intelligence designs.

Ali Zadeth

COTS domain combined with ultra deep sub micron technologies with focus on radiation issues in space

Speaker: Ali Zadeh

ESA – European Space Agency
Head of the Data Systems, Microelectronics and Component Technology Division (TEC-ED)
Electrical Department (TEC-E)
Directorate of Technology, Engineering & Quality (D/TEC)

Conference committee

Luigi Dilillo

General Chair: Luigi Dilillo

Daniela De Venuto

Vice-General Chair: Daniela De Venuto

Hassen Aziza

Program Chair: Hassen Aziza

Eduardo A. Bezerra

Integrated Systems Design Track Chair: Eduardo A. Bezerra

Mihalis Psarakis

Test and Reliability Track Chair: Mihalis Psarakis

Vincenzo Della Marca

Integrated Systems Technology Track co-Chair: Vincenzo Della Marca

Mathieu Moreau

Publicity Chair: Mathieu Moreau

Marcello Traiola

Special Session Chair: Marcello Traiola

Jeremy postel-pellerin

Integrated Systems Technology Track co-Chair: Jeremy Postel-Pellerin

Alberto Bosio

Publication Chair: Alberto Bosio

Arnaud Virazel

Finance Chair: Arnaud Virazel

Douglas A. Santos

Web Chair: Douglas A. Santos

Lucas Matana

Audio/Visual Co-Chair: Lucas Matana

André Mattos

Audio/Visual Co-Chair: André Mattos

Steering committee

S. Hamdioui Technische Universiteit Delft, The Netherlands
P. Girard LIRMM, Université de Montpellier/CNRS, France
I. Voyiatzis Technological Educational Institute of Athens, Greece
M. Masmoudi École nationale d’ingénieurs de Sfax, Tunisia

Sponsors

Contact Us

Any questions can be addressed to general and program chairs

General Chair: Luigi Dilillo

luigi.dilillo@lirmm.fr

Vice-General Chair: Daniela De Venuto

daniela.devenuto@poliba.it

Program Chair: Hassen Aziza

hassen.aziza@im2np.fr