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ADAC: ADAptive Computing

L’équipe ADAC réunit des chercheurs et enseignants-chercheurs aux compétences complémentaires réunis autour de la thématique fédératrice de la conception de systèmes adaptatifs, composants capables de s’autogérer pour optimiser leurs performances au sens de propriétés diverses (puissance de calcul, consommation, fiabilité, sécurité). Les domaines d’application adressés sont larges, et concernent plus spécifiquement les systèmes embarqués, l’internet des objets (IoT) et les grilles de calcul. L’équipe bénéficie d’une reconnaissance nationale et internationale de ses activités, que ce soit pour les travaux menés sur les structures innovantes à base de mémoires magnétiques ou bien les travaux sur les systèmes multiprocesseurs adaptatifs.

Activités scientifiques

Les recherches menées par l’équipe s’inscrivent dans un des trois axes suivants, chaque permanent étant en général impliqué sur 2 axes (un axe principal et un axe secondaire).

Axe 1 : Architecture matérielles et logicielles innovantes

Les recherches menées dans cet axe visent à apporter des réponses à des problèmes divers tels que l’efficacité énergétique ou l’optimisation des performances. Les approches proposées relèvent de la définition d’architectures matérielles et logicielles avec une emphase particulière portée sur l’adaptation [A1] [A2]. Les solutions sont de type systèmes multicoeurs/multiprocesseurs homogènes ou hétérogènes, l’accent étant mis sur les questions du support permettant la mise en place de solutions adaptatives[A3] (monitoring, migration d’objets logiciels) ainsi que la prise de décision (modélisation, prédiction et prise de décision). Les travaux concernent à la fois les systèmes sur puce et les grilles de calcul, avec notamment un projet innovant associant le concept de l’adaptation à un transfert d’énergie entre noeuds de calcul.

Axe 2 : Intégration technologique

Les travaux menés dans cet axe relèvent de la prise en compte ou de l’exploitation intelligente du substrat technologique pour optimiser les performances des systèmes au sens large du terme. Ceci concerne des travaux sur les technologies mémoires émergentes (MRAM notamment) avec des contributions sur des cellules hybrides, s’appuyant sur la technologie CMOS et sur des mémoires MRAM non-volatiles [I3], innovantes et brevetées, à des fins d’intégrations architecturales pour les systèmes embarqués ou encore pour la hiérarchie mémoire de systèmes multicoeurs [I1] [I2].

Des travaux sont également menés sur les réseaux de communication intégrés (NoC) avec prise en compte des procédés de fabrication (3D TSV, asynchrones, FDSOI) ou bien encore sur la construction de modèles compacts pour l’estimation de la consommation ou de la température de fonctionnement en utilisant des approches de fouille de données.

Axe 3 : Sécurité des systèmes

Enfin, l’équipe conduit des recherches dans le domaine de la sécurisation des systèmes embarqués contre différents types de menaces tels que les attaques par canaux cachés, la contrefaçon, la protection des échanges de données sur puce [S1][S2], ou encore la sécurisation des réseaux industriels et des objets connectés. Différents types de solutions ont été proposés par l’équipe qui par ailleurs gère la plateforme de sécurité numérique SECNUM (plateforme ouverte unique en France permettant l’analyse sécuritaire de circuits intégrés). Cette plateforme est utilisée à des fins de recherche mais aussi pour de la pré-évaluation de circuits industriels et pour la formation dans le cadre des Services Nationaux du GIP-CNFM.

Au-delà des recherches menées au sein de ces 3 axes, il convient de souligner que l’équipe porte une attention particulière à sa politique de prospective scientifique et dédie une partie de ses activités à des actions exploratoires.

Contrats de Recherche

DREAM CLOUD :

Dynamic Resource Allocation In Embedded and High Performance Computing

Travaux sur l’assignation dynamique de ressources dans les systèmes multicoeurs (axe1)

IOTEROP :

Architecture distribuée de passerelles réseaux interopérables et collaborative

Accompagnement de la maturation de la startup IOTEROP (axe1)

MONT-BLANC3 : 

European scalable and power efficient HPC platform based on low power embedded technology

Travaux sur la simulation orienté traces, l’exploration de systèmes multicoeurs hétérogènes et les mémoires émergentes pour le calcul intensif (axes1et 2)

www.montblanc-projet.eu

SECNUM :

Plateforme SECNUM Cryptographie et sécurité Numérique (FEDER)

Projet d'investissement pour la plateforme sécurité numérique SECNUM (support de l'axe 3)

 

MULTISMART :

Plateforme sécurisée à mémoire magnétique Multi bits innovante pour Smart Cards

Conception à l'aide de mémoire MRAM Multi[bits (Axe2)

MASTA :

MRAM BASED DESIGN, TEST AND RELIABILITY FOR ULTRA LOW POWER SoC

Projet sur la conception d'architectures logicielles/matérielles ultra basse consommation à base de MRAM (Axe2)

 

GREAT :

Hetero Geneous integrated Magnetic technology using multifunctional standardized sTack (MSS)

Conception de systèmes très faible consommation à base de mémoires MRAM, application à l'IOT (Axe1et 2)

 

CONTINUUM :

Design Continuum for Next Generation Energy Efficient Compute Nodes

Travaux sur des architectures matérielles hétérogènes intégrant des mémoires non volatiles, et des techniques de compilation adaptées (axe1)

 

Rayonnement

Le rayonnement des membres de l’équipe se caractérise à partir des indicateurs suivants sur la période 2013-2016 :

• Evaluation / Expertise

- Comité d’Evaluation ANR Défis Micro et Nanotechnologies,

- Membre du comité Scientifique de l'ANR Nanosciences & STIC,

- Participations à plusieurs groupes de travail prospectifs,

- Croucher Fundation – Fondation privée pour la recherche - Hong-Kong

• Communication et évènements scientifiques

- Organisation du Colloque BRAFITEC 2016 (Franco-Brésilien)

- Création du workshop RECOSOC, organisation des éditions 2011 et 2014

- Membre de Comités de pilotage : IEEE FPL, RECOSOC, IEEE ISVLSI, CRYPTARCHI, IEEE NVMSA,

- Working group IFIP 10.5 : « Design and Engineering of Electronic Systems »,

- Associate Editor : ACM Transactions on Embedded Computing Systems,

  Membre de comité des programmes des principales conférences du domaine.

Members

Permanents

No permanents

Publications depuis 2013 - Evaluation 2019

Articles de revues internationales

2018

  1. A high-reliability and low-power computing-in-memory implementation within STT-MRAM
    Liuyang Zhang, Erya Deng, Hao Cai, You Wang, Lionel Torres, Aida Todri-Sanial, Youguang Zhang
    Microelectronics Journal, Elsevier, In press. <10.1016/j.mejo.2018.09.005>
  2. Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation
    Charles Effiong, Gilles Sassatelli, Abdoulaye Gamatié
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2018, 60, pp.173-184.
  3. Addressing the Thermal Issues of STT-MRAM From Compact Modeling to Design Techniques
    Liuyang Zhang, Yuanqing Cheng, Kang Wang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial
    IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2018, 17 (2), pp.345-352.
  4. Static Prediction of Silent Stores
    Fernando Magno Quintão Pereira, Guilherme Leobas, Abdoulaye Gamatié
    ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, In press.

2017

  1. Design Space Exploration of LDPC Decoders Using High-Level Synthesis
    João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva
    IEEE Access, IEEE, 2017, 5, pp.14600-14615.
  2. A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring
    Mohamad Najem, Pascal Benoit, Mohamad El Ahmad, Gilles Sassatelli, Lionel Torres
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2017, 36 (7), pp.1153-1166.
  3. Computing reliability: On the differences between software testing and software fault injection techniques
    Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, Lionel Torres
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2017, 50, pp.102-112.
  4. Fine-Grained Monitoring For Self-Aware Embedded Systems
    Mohamad Najem, Mohamad El Ahmad, Pascal Benoit, Gilles Sassatelli, Lionel Torres
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2017, 48, pp.3-10.
  5. A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions
    Mario Barbareschi, Giorgio Di Natale, Lionel Torres, Antonino Mazzeo
    IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, In press, pp.1-23.
  6. Enseignement de la sécurité numérique : De la sensibilisation à l'expertise
    Florent Bruguier, Pascal Benoit, Lionel Torres
    Journal sur l'enseignement des sciences et technologies de l'information et des systèmes, EDP Sciences, 2017, 16. <10.1051/j3ea/20171004>
  7. Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices
    Sophiane Senni, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Gilles Sassatelli
    IEEE Magnetics Letters, IEEE, 2017, 8, pp.1-5.

2016

  1. Ring oscillators analysis for security purposes in Spartan-6 FPGAs
    Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (Part A), pp.3-10.
  2. Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices
    Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié
    ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, 13 (2), pp.1-23.
  3. Model-based design of correct controllers for dynamically reconfigurable architectures
    Xin An, Eric Rutten, Jean-Philippe Diguet, Abdoulaye Gamatié
    ACM Transactions on Embedded Computing Systems (TECS), ACM, 2016, 15 (3), pp.#51.
  4. Exploring MRAM Technologies for Energy Efficient Systems-On-Chip
    Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems, IEEE, 2016, 6 (3), pp.279-292.
  5. Cost-Effective Design Strategies for Securing Embedded Processors
    Florent Bruguier, Pascal Benoit, Lionel Torres, Lyonel Barthe, Morgan Bourrée, Victor Lomné
    IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2016, 4 (1), pp.60-72.
  6. STT-MRAM-Based PUF Architecture exploiting Magnetic Tunnel Junction Fabrication-Induced Variability
    Ioana Vatajelu, Giorgio Di Natale, Mario Barbareschi, Lionel Torres, Marco Indaco, Paolo Prinetto
    ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, 13 (1). <10.1145/2790302>

2015

  1. Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures
    Rafael Garibotti, Anastasiia Butko, Luciano Ost, Abdoulaye Gamatié, Gilles Sassatelli, Chris Adeniyi-Jones
    IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2015, 65 (8), pp.2645-2651.
  2. Disposable configuration of remotely reconfigurable systems
    Lilian Bossuet, Viktor Fischer, Lubos Gaspar, Lionel Torres, Guy Gogniat
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2015, 39 (6), pp.382-392.
  3. High-level design space exploration for adaptive applications on multiprocessor systems-on-chip
    Xin An, Abdoulaye Gamatié, Eric Rutten
    Journal of Systems Architecture, Elsevier, 2015, 61 (3-4), pp.172-184.
  4. Progressive and explicit refinement of scheduling for multidimensional data-flow applications using UML MARTE
    Calin Glitia, Julien Deantoni, Frédéric Mallet, Jean-Vivien Millo, Pierre Boulet, Abdoulaye Gamatié
    Design Automation for Embedded Systems, Springer Verlag, 2015, 19 (1-2), pp.1-33.
  5. Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions
    Bojan Jovanovic, Raphael M. Brum, Lionel Torres
    IEEE Transactions on Magnetics, Institute of Electrical and Electronics Engineers, 2015, 51 (2). <10.1109/TMAG.2014.2347009>
  6. Vertical and horizontal correlation attacks on RNS-based exponentiations
    Guilherme Perin, Laurent Imbert, Philippe Maurine, Lionel Torres
    Journal of Cryptographic Engineering, Springer, 2015, 5 (3), pp.171-185.

2014

  1. Evaluation of hybrid MRAM/CMOS cells for “normally-off and instant-on” computing
    Bojan Jovanovic, Raphael M. Brum, Lionel Torres
    Analog Integrated Circuits and Signal Processing, Springer Verlag, 2014, 81 (3), pp.607-621.
  2. Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory
    Luís Vitório Cargnini, Lionel Torres, Raphael M. Brum, Sophiane Senni, Gilles Sassatelli
    Journal of Low Power Electronics and Applications, MDPI AG, Basel, Switzerland, 2014, 4 (3), pp.214-230.
  3. Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs
    Fernanda Lima Kastensmidt, Jorge Tonfat, Thiago Hanna Both, Paolo Rech, Gilson Wirth, Ricardo Da Luz Reis, Florent Bruguier, Pascal Benoit, Lionel Torres, Christopher Frost
    Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2344-2348.
  4. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design
    Bojan Jovanovic, Raphael M. Brum, Lionel Torres
    Journal of Applied Physics, American Institute of Physics, 2014, 115 (13), pp.134316.

2013

  1. Spintronic Memory-Based Reconfigurable Computing
    Weisheng Zhao, Raphael M. Brum, Lionel Torres, Jacques-Olivier Klein, Gilles Sassatelli, DafinÉ Ravelosona, Claude Chappert
    SPIN, World Scientific Publishing, 2013, 3 (4), pp.1340010.
  2. Fine-grain dynamic energy tracking for system-on-chip
    Imen Mansouri, Pascal Benoit, Lionel Torres, Fabien Clermidy
    IEEE Transactions on Circuits and Systems Part 2 Analog and Digital Signal Processing, Institute of Electrical and Electronics Engineers (IEEE), 2013, 60 (6), pp.4.
  3. Special section on modeling of reactive systems
    Étienne Craye, Abdoulaye Gamatié
    Discrete Event Dynamic Systems, Springer Verlag, 2013, 23 (4), pp.341-342.
  4. Novel Techniques for Smart Adaptive Multiprocessor SoCs
    Gilles Sassatelli, Luciano Ost, Rafael Garibotti, Gabriel Marchesan, Michel Robert, Rémi Busseuil, Anastasiia Butko, Juergen Becker
    IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2013, pp.14.
  5. Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
    Luciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Moller, Leandro Soares Indrusiak, Gilles Sassatelli, Pascal Benoit, Manfred Glesner, Michel Robert, Fernando Moraes
    ACM Transactions on Embedded Computing Systems (TECS), ACM, 2013, 12 (3), pp.75:22.

Communications internationales

2018

  1. Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM
    Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié
    RTNS: Real-Time Networks and Systems, Oct 2018, Poitiers, France. 26th International Conference on Real-Time Networks and Systems, pp.148-158, 2018.
  2. Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing
    David Novo, Alejandro Nocua, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli
    ReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2018, Lille, France. 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018. <https://recosoc-2018.sciencesconf.org>
  3. A Compiler-Centric Infra-Structure for Whole-Board Energy Measurement on Heterogeneous Android Systems
    Junio Cezar Ribeiro Da Silva, Fernando Magno Quinto Pereira, Michael Frank, Abdoulaye Gamatié
    ReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2018, Lille, France. IEEE, 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018. <10.1109/ReCoSoC.2018.8449378>
  4. A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM
    Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2018, Hong Kong, China. IEEE Computer Society Annual Symposium on VLSI, 2018. <10.1109/ISVLSI.2018.00058>
  5. FPGA-based platform for fast accurate evaluation of Ultra Low Power SoC
    Guillaume Patrigeon, Pascal Benoit, Lionel Torres
    PATMOS: Power and Timing Modeling, Optimization and Simulation, Jul 2018, Platja d'Aro, Spain. IEEE, 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, 2018. <10.1109/PATMOS.2018.8464173>
  6. Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement Policy
    Pierre-Yves Péneau, David Novo, Florent Bruguier, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié
    ARCS: Architecture of Computing Systems, Apr 2018, Braunschweig, Germany. 31st International Conference on Architecture of Computing Systems, LNCS (10793), pp.168-180, 2018.
  7. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
    Manu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, José Ignacio Gómez, Gouri Sankar Kar, Arnaud Furnemont, Francky Catthoor, Sophiane Senni, David Novo, Abdoulaye Gamatié, Lionel Torres
    DATE: Design, Automation and Test in Europe, Mar 2018, Dresden, Germany. IEEE, 21st Design, Automation & Test in Europe Conference & Exhibition, 2018. <10.23919/DATE.2018.8341987>
  8. Using multifunctional standardized stack as universal spintronic technology for IoT
    Mehdi B. Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frédéric Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, Alexandru Atitoaie, Ioana Firastrau, G. Di Pendina, Guillaune Prenat
    DATE: Design, Automation and Test in Europe, Mar 2018, Dresden, Germany. IEEE Design, Automation & Test in Europe Conference & Exhibition, 2018. <10.23919/DATE.2018.8342143>
  9. Compile-Time Silent-Store Elimination for Energy Efficiency: an Analytic Evaluation for Non-Volatile Cache Memory
    Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié
    RAPIDO: Rapid Simulation and Performance Evaluation, Jan 2018, Manchester, United Kingdom. ACM, 10th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, pp.1-8, 2018.

2017

  1. How Could Compile-Time Program Analysis help Leveraging Emerging NVM Features?
    Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié
    EDiS: Embedded and Distributed Systems, Dec 2017, Oran, Algeria. 1st International conference on Embedded & Distributed Systems, pp.1-6, 2017.
  2. Performance and Energy Assessment of Last-Level Cache Replacement Policies
    Pierre-Yves Péneau, David Novo, Florent Bruguier, Gilles Sassatelli, Abdoulaye Gamatié
    EDiS: Embedded and Distributed Systems, Dec 2017, Oran, Algeria. 1st international conference on Embedded & Distributed Systems, 2017. <https://sites.google.com/view/edis2017>
  3. Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect
    Charles Effiong, Gilles Sassatelli, Abdoulaye Gamatié
    NOCS: Networks-on-Chip Symposium, Oct 2017, Seoul, South Korea. 11th IEEE/ACM International Symposium on Networks-on-Chip, pp.Article No. 2, 2017.
  4. LTE-M adaptive eNodeB for emergency scenarios
    Ahmad Hani El Fawal, Ali Mansour, Mohamad Najem, Frédéric Le Roy, Denis Le Jeune
    ICTC: Information and Communication Technology Convergence, Oct 2017, Jeju Island, South Korea. IEEE, International Conference on Information and Communication Technology Convergence, 2017. <10.1109/ICTC.2017.8191035>
  5. Trace-driven simulation of multithreaded applications in gem5
    Gilles Sassatelli, Alejandro Nocua, Florent Bruguier, Anastasiia Butko
    ARM Research Summit 2017 Workshop, Sep 2017, Cambridge, United Kingdom. 2017. <https://developer.arm.com/research/summit/previous-summits/2017>
  6. Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing
    Charles Effiong, Gilles Sassatelli, Abdoulaye Gamatié
    DSD: Digital System Design, Aug 2017, Vienna, Australia. Euromicro Conference on Digital System Design, 2017. <10.1109/DSD.2017.55>
  7. A novel SRAM -STT-MRAM hybrid cache implementation improving cache performance
    Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit
    NANOARCH: Nanoscale Architectures, Jul 2017, Newport, United States. IEEE/ACM International Conference on Nanoscale Architectures, 2017. <10.1109/NANOARCH.2017.8053704>
  8. ElasticSimMATE: a Fast and Accurate gem5 Trace-Driven Simulator for Multicore Systems
    Alejandro Nocua, Florent Bruguier, Gilles Sassatelli, Abdoulaye Gamatié
    ReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2017, Madrid, Spain. IEEE, 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017. <10.1109/ReCoSoC.2017.8016146>
  9. GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack
    Mehdi B. Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory Di Pendina, Guillaune Prenat
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2017, Bochum, Germany. IEEE International Symposium on Very Large Scale Integration, 2017. <10.1109/ISVLSI.2017.67>
  10. Roundabout: A Network-on-Chip router with adaptive buffer sharing
    Charles Effiong, Gilles Sassatelli, Abdoulaye Gamatié
    NEWCAS: New Circuits and Systems Conference, Jun 2017, Strasbourg, France. 15th IEEE International New Circuits and Systems Conference, 2017. <10.1109/NEWCAS.2017.8010106>
  11. Efficient Programming for Multicore Processor Heterogeneity: OpenMP versus OmpSs
    Anastasiia Butko, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli
    OpenSuCo 1 (ISC17), Jun 2017, Frankfurt, Germany. Workshop on Open Source Supercomputing Held in conjunction with the The International Conference for High Performance Computing, Networking, Storage and Analysis (SC17), Denver, Colorado, 2017. <http://www.opensuco.community/2017/01/30/opensuco-1/>
  12. MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory Technologies
    Thibaud Delobelle, Pierre-Yves Péneau, Abdoulaye Gamatié, Florent Bruguier, Sophiane Senni, Gilles Sassatelli, Lionel Torres
    EMS: Emerging Memory Solutions, Mar 2017, Lausanne, Switzerland. 2nd International Workshop on Emerging Memory Solutions Co-located with DATE'17 conference at March 31, 2017 in Lausanne, Switzerland, 2017. <https://ems.eit.uni-kl.de/en/ems-workshop/>
  13. Embedded systems to high performance computing using STT-MRAM
    Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Péneau, Lionel Torres, Abdoulaye Gamatié, Pascal Benoit, Gilles Sassatelli
    DATE: Design, Automation and Test in Europe, Mar 2017, Lausanne, Switzerland. 20th Conference & Exhibition of Design, Automation & Test in Europe, pp.536-541, 2017.

2016

  1. Embedded Hardware and IoT Security
    Lionel Torres
    Symposium on Emerging Trends in Computing, Oct 2016, Montreux, Switzerland. 2016.
  2. Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration
    Anastasiia Butko, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli, David Novo, Lionel Torres, Michel Robert
    MCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016. <10.1109/MCSoC.2016.20>
  3. Exploiting Large Memory using 32-bit Energy-Efficient Manycore Architectures
    Mohamed Lamine Karaoui, Pierre-Yves Péneau, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner
    MCSoC: Many-core Systems-on-Chip, Sep 2016, Lyon, France. IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016, MCSoC 2016. <http://www.mcsoc-forum.org/2016/>
  4. Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy Tradeoffs
    Pierre-Yves Péneau, Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres, Sophiane Senni
    PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.162-169, 2016, Proceedings of the 26th International Workshop on Power and Timing Modeling, Optimization and Simulation.
  5. Performance Prediction of Application Mapping in Manycore Systems with Artificial Neural Networks
    Abdoulaye Gamatié, Roman Ursu, Manuel Selva, Gilles Sassatelli
    MCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. IEEE, 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016. <http://mcsoc-forum.org/2016/>
  6. An SEU Tolerant MRAM based non-volatile asynchronous circuit design
    Jeremy Lopes, Gregory Dipendina, Edith Beigne, Lionel Torres
    RADECS: Radiation and its Effects on Components and Systems, Sep 2016, Bremen, Germany. 16th European Conference on Radiation and Its Effects on Components and Systems, 2016. <10.1109/RADECS.2016.8093151>
  7. An SEU tolerant MRAM based non-volatile asynchronous circuit design
    Jeremy Lopes, Gregory Di Pendina, Edith Beigne, Lionel Torres
    RADECS: Radiation and its Effects on Components and Systems, Sep 2016, Bremen, Germany. IEEE, 16th European Conference on Radiation and its Effects on Components and Systems, 2016. <10.1109/RADECS.2016.8093151>
  8. Speed and Accuracy Dilemma in NoC Simulation: What about Memory Impact?
    Manuel Selva, Abdoulaye Gamatié, David Novo, Gilles Sassatelli
    ReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jun 2016, Tallinn, Estonia. 2016.
  9. Quantitative evaluation of reliability and performance for STT-MRAM
    Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng, Weisheng Zhao
    ISCAS: International Symposium on Circuits and Systems, May 2016, Montréal, QC, Canada. IEEE, http://iscas2016.org, pp.1150-1153, 2016.
  10. Hardware security: From concept to application
    Florent Bruguier, Pascal Benoit, Lionel Torres, Lilian Bossuet
    EWME: European Workshop on Microelectronics Education, May 2016, Southampton, United Kingdom. 11th European Workshop on Microelectronics Education, 2016. <10.1109/EWME.2016.7496483>
  11. Reliability and performance evaluation for STT-MRAM under temperature variation
    Liuyang Zhang, Yuanqing Cheng, Wang Kang, Youguang Zhang, Lionel Torres, Weisheng Zhao, Aida Todri-Sanial
    EuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2016, Montpellier, France. 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, pp.1-4, 2016.
  12. Correlative electromagnetic analysis on an AES cryptoprocessor
    Florent Bruguier
    Training School on Trustworthy Manufacturing and Utilization of Secure Devices, Apr 2016, Leukerbad, Switzerland. 2016.
  13. A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud Infrastructures
    Roman Ursu, Khalid Latif, David Novo, Manuel Selva, Abdoulaye Gamatié, Gilles Sassatelli, Dmitry Khabi, Alexey Cheptsov
    DREAMCloud: Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing, Jan 2016, Prague, Czech Republic. 2nd International Workshop on Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing January 19, 2016, Prague, Czech Republic, 2016.
  14. Position Paper: OpenMP scheduling on ARM big.LITTLE architecture
    Anastasiia Butko, Louisa Bessad, David Novo, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli, Lionel Torres, Michel Robert
    MULTIPROG: Programmability and Architectures for Heterogeneous Multicores, Jan 2016, Prague, Czech Republic. 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, 2016. <http://research.ac.upc.edu/multiprog/multiprog2016/>
  15. Design space exploration for complex automotive applications: an engine control system case study
    Khalid Latif, Manuel Selva, Charles Effiong, Roman Ursu, Abdoulaye Gamatié, Gilles Sassatelli, Leonardo Zordan, Luciano Ost, Piotr Dziurzanski, Leandro Soares Indrusiak
    RAPIDO: Rapid Simulation and Performance Evaluation, Jan 2016, Prague, Czech Republic. 8th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2016. <10.1145/2852339.2852341>
  16. Processor Architecture Based on MRAM, from embedded systems to high performance computing
    Lionel Torres
    7th MRAM Global Innovation Forum 2016, 2016, Zurich, Switzerland. 2016.

2015

  1. For a Design Continuum to Build Next Generation Energy-Efficient Compute Nodes
    Abdoulaye Gamatié
    EDiS: Embedded and Distributed Systems, Nov 2015, Oran, Algeria. 1st National Conference on Embedded and Distributed Systems, 2015.
  2. Adaptive Power monitoring for self-aware embedded systems
    Mohamad El Ahmad, Mohamad Najem, Pascal Benoit, Gilles Sassatelli, Lionel Torres
    NORCAS: Nordic Circuits and Systems Conference, Oct 2015, Oslo, Norway. IEEE, Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015, 2015. <10.1109/NORCHIP.2015.7364364>
  3. Ring Oscillators Analysis for FPGA Security Purposes
    Mario Barbareschi, Lionel Torres, Giorgio Di Natale
    TRUDEVICE Workshop, Sep 2015, St Malo, France. Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, 2015.
  4. An Integrated Framework for Model-Based Design and Analysis of Automotive Multi-Core Systems
    Khalid Latif, Charles Effiong, Abdoulaye Gamatié, Gilles Sassatelli, Leonardo Zordan, Luciano Ost, Piotr Dziurzanski, Leandro Soares Indrusiak
    FDL: Forum on specification & Design Languages, Sep 2015, Barcelona, Spain. 2015, Work-in-Progress Session. <http://ecsi.org/fdl2015>
  5. A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core Systems
    Marcelo Mandelli, Guilherme Castilhos, Gilles Sassatelli, Luciano Ost, Fernando G. Moraes
    SBCCI: Symposium on Integrated Circuits and Systems Design, Aug 2015, Salvador de Bahia, Brazil. 28th Symposium on Integrated Circuits and Systems Design, Chip in is Bahia, 2015. <10.1145/2800986.2800992>
  6. Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures
    Anastasiia Butko, Abdoulaye Gamatié, Gilles Sassatelli, Lionel Torres, Michel Robert
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.551-556, 2015.
  7. STT-MRAM-Based Strong PUF Architecture
    Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo Prinetto
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.467-472, 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
  8. Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture
    Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.460-460, 2015.
  9. On the Performance Exploration of 3D NoCs with Resistive-Open TSVs
    Charles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, Khalid Latif
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.579-584, 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
  10. Implementation of AES Using NVM Memories Based on Comparison Function
    Jérémie Clément, Bruno Mussard, David Naccache, Lionel Torres
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. IEEE Computer Society Annual Symposium on VLSI, pp.356-361, 2015.
  11. Digital Right Management for IP Protection
    Jerome Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, Mario Barbareschi
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.200-203, 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
  12. Radiative Effects on MRAM-Based Non-Volatile Elementary Structures
    Jeremy Lopes, Gregory Di Pendina, Eldar Zianbetov, Edith Beigne, Lionel Torres
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.321-326, 2015.
  13. A survey on security features in modern FPGAs
    Rémy Druyer, Lionel Torres, Pascal Benoit
    ReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jun 2015, Brême, Germany. 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015), pp.1-8, 2015.
  14. An architecture-level cache simulation framework supporting advanced PMA STT-MRAM
    Bi Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao
    NANOARCH: Nanoscale Architectures, Jun 2015, Boston, MA, United States. Nanoscale Architectures (NANOARCH), 2015 IEEE/ACM International Symposium on, pp.7-12, 2015.
  15. Asynchronous Design for Harsh Environments
    Jeremy Lopes, Gregory Di Pendina, Edith Beigne, Lionel Torres
    ASYNC: International Symposium on Asynchronous Circuits and Systems, May 2015, Montain View, Silicon Valley, California, United States. IEEE, 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015. <http://ee.usc.edu/async2015/>
  16. Software testing and software fault injection
    Maha Kooli, Alberto Bosio, Pascal Benoit, Lionel Torres
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015. <10.1109/DTIS.2015.7127370>
  17. Ring Oscillators Analysis for FPGA Security Purposes
    Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres
    TRUDEVICE Workshop, Mar 2015, Grenoble, France. Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, W10, 2015.
  18. Potential Applications Based on NVM Emerging Technologies
    Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard
    DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. IEEE, pp.1012-1017, 2015.
  19. Trading-off System Load and Communication in Mapping Heuristics for Improving NoC-Based MPSoCs Reliability
    Marcelo Mandelli, Luciano Ost, Gilles Sassatelli, Fernando G. Moraes
    ISQED: International Symposium on Quality Electronic Design, Mar 2015, Santa Clara, United States. 16th International Symposium on Quality Electronic Design, pp.392-396, 2015.
  20. Discrete Control-Based Design of Adaptive and Autonomic Computing Systems
    Xin An, Gwenaël Delaval, Jean-Philippe Diguet, Abdoulaye Gamatié, Soguy Mak-Karé Gueye, Hervé Marchand, Noel De Palma, Eric Rutten
    ICDCIT: International Conference on Distributed Computing and Internet Technology, Feb 2015, Bhubaneswar, India. Springer, 11th International Conference on Distributed Computing and Internet Technology, LNCS (8956), 2015. <10.1007/978-3-319-14977-6_6>
  21. A trace-driven approach for fast and accurate simulation of manycore architectures
    Anastasiia Butko, Rafael Garibotti, Luciano Ost, Chris Adeniyi-Jones, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli
    ASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2015, Chiba, Tokyo, Japan. 2015, 20th Asia and South Pacific Design Automation Conference. <10.1109/ASPDAC.2015.7059093>
  22. Performance of a Smartphone based Star Tracker
    Andrey Khorev, Lionel Torres, Eric Nativel
    iCubeSat: Interplanetary CubeSat, 2015, Londres, United Kingdom. 4th Interplanetary CubeSat Workshop, 2015.

2014

  1. Evidence of a larger EM-induced fault model
    Sébastien Ordas, Ludovic Guillaume-Sage, Karim Tobich, Jean-Max Dutertre, Philippe Maurine
    CARDIS: Smart Card Research and Advanced Application, Nov 2014, Paris, France. 13th Smart Card Research and Advanced Application Conference, LNCS (8968), pp.245-259, 2015, Smart Card Research and Advanced Applications.
  2. Analysing the Impact of Aging and Voltage Scaling under Neutron-induced Soft Error Rate in SRAM-based FPGAs
    Fernanda Lima Kastensmidt, Tonfat Jorge, Thiago Both, Paolo Rech, Gilson Wirth, Ricardo Da Luz Reis, Florent Bruguier, Pascal Benoit, Lionel Torres, Christopher Frost
    ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Sep 2014, Berlin, Germany. 25th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.
  3. Aging effects in FPGAs: an experimental analysis
    Abdulazim Amouri, Florent Bruguier, Saman Kiamehr, Pascal Benoit, Lionel Torres, Mehdi B. Tahoori
    FPL: Field Programmable Logic and Applications, Sep 2014, Munich, Germany. 24th International Conference on Field Programmable Logic and Applications, pp.1-4, 2014.
  4. Method for dynamic power monitoring on FPGAs
    Mohamad Najem, Pascal Benoit, Florent Bruguier, Gilles Sassatelli, Lionel Torres
    FPL: Field Programmable Logic and Applications, Sep 2014, Munich, Germany. 24th International Conference on Field Programmable Logic and Applications, 2014. <10.1109/FPL.2014.6927457>
  5. Performance exploration of partially connected 3D NoCs under manufacturing variability
    Anelise Kologeski, Fernanda Lima Kastensmidt, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial
    NEWCAS: International New Circuits and Systems Conference, Jun 2014, Trois-Rivieres, QC, Canada. IEEE, New Circuits and Systems Conference (NEWCAS), 2014 IEEE 12th International, pp.61-64, 2014.
  6. Power management through DVFS and dynamic body biasing in FD-SOI circuits
    Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro-Panades, Pascal Benoit, Lionel Torres
    DAC: Design Automation Conference, Jun 2014, San Francisco, United States. 51st Annual Design Automation Conference, pp.1-6, 2014.
  7. Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs
    Fernanda Lima Kastensmidt, Jorge Tonfat, Thiago Both, Paolo Rech, Gilson Wirth, Ricardo Reis, Florent Bruguier, Pascal Benoit, Lionel Torres, Christopher Frost
    ETS: European Test Symposium, May 2014, Paderborn, Germany. 19th IEEE European Test Symposium, 2014. <10.1109/ETS.2014.6847845>
  8. Power efficient Thermally Assisted Switching Magnetic memory based memory systems
    Sophiane Senni, Lionel Torres, Gilles Sassatelli, Anastasiia Butko, Bruno Mussard
    ReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, 2014. <10.1109/ReCoSoC.2014.6861357>
  9. Fault injection tools based on Virtual Machines
    Kooli Maha, Giorgio Di Natale, Pascal Benoit, Alberto Bosio, Lionel Torres, Volkmar Sieh
    ReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. 2014, Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on. <10.1109/ReCoSoC.2014.6861351>
  10. Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs
    Fernanda Lima Kastensmidt, Jorge Tonfat, Thiago Both, Paolo Rech, Gilson Wirth, Ricardo Reis, Florent Bruguier, Pascal Benoit, Lionel Torres, Christopher Frost
    ETS: European Test Symposium, May 2014, Paderborn, Germany. IEEE, 19th IEEE European Test Symposium, 2014. <10.1109/ETS.2014.6847845>
  11. Attacking Randomized Exponentiations Using Unsupervised Learning
    Guilherme Perin, Laurent Imbert, Lionel Torres, Philippe Maurine
    COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2014, Paris, France. COSADE'2014: 5th International Workshop on Constructive Side-Channel Analysis and Secure Design, LNCS (8622), pp.144-160, 2014, Constructive Side-Channel Analysis and Secure Design.

2013

  1. Instruction-Driven Timing CPU Model for Efficient Embedded Software Development Using OVP
    Felipe Da Rosa, Luciano Ost, Ricardo Reis, Gilles Sassatelli
    ICECS: International Conference on Electronics, Circuits, and Systems, Dec 2013, Abu Dhabi, United Arab Emirates. 20th IEEE International Conference on Electronics, Circuits, and Systems, pp.855-858, 2013.
  2. Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic Attacks
    Guilherme Perin, Laurent Imbert, Lionel Torres, Philippe Maurine
    CARDIS: Smart Card Research and Advanced Application, Nov 2013, Berlin, Germany. Springer, 12th Smart Card Research and Advanced Application Conference, LNCS (8419), pp.200-215, 2013.
  3. Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing
    Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigne, Pascal Benoit, Lionel Torres
    PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.199-206, 2013.
  4. Discrete Control for Reconfigurable FPGA-based Embedded Systems
    Xin An, Eric Rutten, Jean-Philippe Diguet, Nicolas Le Griguer, Abdoulaye Gamatié
    DCDS: Dependable Control of Discrete Systems, Sep 2013, York, United Kingdom. 4th IFAC Workshop on Dependable Control of Discrete Systems, 2013.
  5. Electromagnetic Analysis on RSA Algorithm Based on RNS
    Guilherme Perin, Laurent Imbert, Lionel Torres, Philippe Maurine
    DSD: Digital System Design, Sep 2013, Santander, Spain. IEEE, 16th Euromicro Conference on Digital System Design, pp.345-352, 2013, Digital System Design.
  6. Using electromagnetic emanations for variability characterization in Flash-based FPGAs
    Florent Bruguier, Lionel Torres, Pascal Benoit, Morgan Bourrée, Jimmy Tarrillo, Tonfat Jorge, Fernanada Kastensmidt, Ricardo Da Luz Reis
    ISVLSI: International Symposium on Very Large Scale Integration, Aug 2013, Natal, Brazil. pp.109-114, 2013, Proceedings of the 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
  7. Autonomic Management of Dynamically Partially Reconfigurable FPGA Architectures Using Discrete Control
    Xin An, Eric Rutten, Jean-Philippe Diguet, Nicolas Le Griguer, Abdoulaye Gamatié
    ICAC: International Conference on Autonomic Computing, Jun 2013, San Jose CA, United States. 10th International Conference on Autonomic Computing, 2013.
  8. Embedded memory hierarchy exploration based on magnetic RAM
    Luís Vitório Cargnini, Lionel Torres, Raphael Martins Brum, Sophiane Senni, Gilles Sassatelli
    FTFC: Faible Tension Faible Consommation, Jun 2013, Paris, France. IEEE Faible Tension Faible Consommation, 2013. <10.1109/FTFC.2013.6577780>
  9. Evaluation of hybrid MRAM/CMOS cells for reconfigurable computing
    Lionel Torres, Raphael M. Brum, Yoann Guillemenet, Luís Vitório Cargnini, Gilles Sassatelli
    NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. IEEE, 11th International New Circuits and Systems Conference, 2013. <10.1109/NEWCAS.2013.6573676>
  10. Simultaneous multithreading support in embedded distributed memory MPSoCs
    Rafael Garibotti, Luciano Ost, Rémi Busseuil, Mamady Kourouma, Chris Adeniyi-Jones, Gilles Sassatelli, Michel Robert
    DAC: Design Automation Conference, May 2013, Austin, United States. 50th ACM/EDAC/IEEE Design Automation Conference, pp.83:1-83:7, 2013.
  11. Trends on the Application of Emerging Nonvolatile Memory to Processors and Programmable Device
    Lionel Torres, Raphael M. Brum, Luís Vitório Cargnini, Gilles Sassatelli
    ISCAS: International Symposium on Circuits and Systems, May 2013, Beijing, China. IEEE International Symposium on Circuits and Systems (IS, pp.101-104, 2013.

Tags

Systèmes embarqués adaptatifs, Technologies mémoires émergentes, Architectures multicœurs / multiprocesseurs, Systèmes hétérogènes, modèles de programmation, MPSoC, Sécurité numérique, Calcul haute performance

Last update on 27/06/2018