The work carried out within the TEST team (‘Tests and Dependability of Integrated Microelectronic Systems’) is mainly aimed at developing models, methods and tools to guarantee the quality of microelectronic devices after they have been manufactured.
Our main contributions concern the impact of recent and emerging technologies on device quality, as well as the costs associated with their implementation. In particular, we are focusing on the challenges associated with the complexity of integration, the variability of manufacturing parameters, and the increasing energy consumption of integrated circuits. Our work also covers the specific constraints of secure circuits. The technologies studied, and their integration into a design flow for the creation of reliable and testable systems, encompass advanced CMOS technologies, such as FDSOI/FinFET, as well as disruptive technologies such as 3D integration or emerging memory technologies.
The research carried out leads to the proposal of new fault models, the development of monitoring instruments or new design methods with a view to testing, and the proposal of new hardware architectures integrated into the system in order to monitor its operation throughout its life.
Staff
Patrick Girard, Directeur de recherche, CNRS
Mariane Comte, Maître de conférences, UM
Florence Azaïs, Chargé de recherche, CNRS
Arnaud Virazel, Professeur des universités, UM
Sophie Dupuis, Maître de conférences, UM
Associates and Students
Dorian Ronga, CNRS
Sid Ali Riabi, STMicroelectronics
Danillo Chaves Vieira, UM
Hugo Closquinet, Nucletudes
Regular Co-workers
Ana Tacuri, CDD Ingénieur-Technicien, CNRS
Gianmarco Mongelli, ATER, UM
Bruno Rouzeyre, Invité longue durée Eméritat, UM
In order to structure our research, the TEST team’s scientific activities are organised around three main areas which address reliability and test issues in the following fields:
- Topic 1: Reliability and Test of Digital, Analogue and RF Circuits
- Topic 2: Reliability, Test, Confidence and Security of Integrated Circuits
- Topic 3: Reliability and Test of emerging technologies and paradigms
Topic 1 : Reliability and Testing of Digital, Analogue and RF Circuits
The miniaturisation of technologies poses major challenges in terms of PVT variations, faults and circuit reliability. At the same time, the integration of heterogeneous blocks poses problems of accessibility and cost. Faced with these challenges, the aim is to develop models, methods and tools to improve the testing and reliability of digital, analogue and RF circuits.
Significant progress has been made in this area, notably with the implementation of an intra-cell fault diagnostic flow for digital circuits, the use of artificial intelligence for cell characterisation to limit the need for costly analogue simulations, and the development of solutions to ease the constraints on analogue test equipment (generation of analogue stimuli using digital resources, indirect test solutions based on artificial intelligence techniques).
Topic 2: Reliability, Test, Confidence and Security of Integrated Circuits
As technologies develop and production chains become more complex, integrated circuits are increasingly exposed to security threats. Hardware attacks and loss of control over design and manufacturing represent major challenges, compromising the integrity and confidentiality of electronic systems. To meet these challenges, design-for-trust solutions are being developed to guarantee the security of circuits right from the design stage.
In addition, effective countermeasures are being put in place to protect against fault injection attacks and the exploitation of test chains via Scan interfaces. Major advances include “Logic Locking” to secure digital and analogue circuits, as well as strategies to protect access and secure system test resources.
Topic 3 : Reliability and testing of emerging technologies and paradigms
The emergence of new transistor structures and memory technologies, as well as the rise of innovative computing paradigms such as Approximate Computing (AxC), In-Memory Computing (IMC) and Neural Networks (NN), pose challenges in terms of reliability and testing. In response, efforts are being made to model and analyse faulty behaviour, and to develop test procedures and integrated test solutions. Notable advances include fault-tolerant architectures exploiting approximate computation, integrated test solutions designed for CMOS imagers, and new test approaches developed for in-memory computing architectures.
These areas of research are fully in line with the cross-disciplinary themes of the Microelectronics department, as well as with three of the laboratory’s six cross-disciplinary themes (AI and Data Science, Security and Safety, Software Science).
HADES :
Hierarchy-Aware and secure embedded test infrastructure for Dependability and performance Enhancement of integrated Systems.
EDITSoC :
Electrical Diagnosis for IoT SoCs in automotive Diagnostic Electrique des Systèmes-sur-Puce dédiés aux Applications IoT pour le Secteur Automobile.
MOOSIC :
Multi-Objective Optimised Synthesis to Improve Cybersecurity.
LIA LAFISI :
French-Italian research LAboratory on hardware-software Integrated Systems.
The team members are strongly involved in the following conferences: ETS “European Test Symposium” (organization in 2013, Program Chair from 2015 to 2016, Publication Chair from 2015 to 2016 and Steering Committee members), VTS “VLSI Test Symposium” (Publication Chair since 2012, General chair in 2013 and Member of the Program Committee) and DATE “Design Automation and Test in Europe” (Program Vice Chair in 2016 and Program Chair in 2017, Member of the Executive Committee since 2013).
We also participate very actively in international conferences and workshops related to our research areas: IEEE Computer Society Annual Symposium VLSI (Program Co-Chair in 2016, General co-Chair in 2015, Track Chair from 2015 to 2017 and Publication Chair in 2015), Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (General Chair from 2013 to 2016 and Program Chair from 2013 to 2014), IEEE International Mixed-Signals Test Workshop (Chair of the Steering Committee from 2013 to 2016 and Program Chair in 2014). Members of the team are also involved in the review committees of major journals in our field: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Computers, JETTA – Journal of Electronic Testing – Theory and Applications, IEEE Transactions on Large Scale Integration Systems, IEEE Transactions on Emerging Topics in Computing, JOLPE – Journal of Low Power Electronics, ACM Journal of Emerging Technologies in Computing Systems.
We are also very active in the IEEE Computer Society European TTTC “Test Technology Technical Council” (Chair since 2014, Electronic Media Chair since 2012).
At the national level, we are strongly involved in the GdR SoC-SiP/SoC2 (Deputy Director, Responsible of the “Safety of Material Systems” working group, Members of the Steering Committee), in the pre-GdR Security (Member) and in the ERRATA GdR (Member).