The TEST (Test and dEpendability of Integrated Microelectronics SysTems) team’s main objective is the development of models, methods and tools to ensure the post-production quality of integrated microelectronic devices. The team focuses on designing test-ready integrated systems to make post-production verification steps simpler, more efficient and less costly.
Our main contributions harness emerging tech-nologies, as we pay particular attention to complexity, variability and consumption issues, non-monolithic integration approaches with 3D integration technologies, and to novel devices in the development of reliability and test approaches. This research is most often accompanied by the development of new test methods, but also relies on proposing fault models or designing hardware architectures which are integrated into the systems to monitor their performance throughout their life cycle.
Staff
Thibault Vayssade, , UM
Serge Pravossoudovitch, Professeur des universités, UM
Patrick Girard, Directeur de recherche, CNRS
Mariane Comte, Maître de conférences, UM
Marie-Lise Flottes, Chargé de recherche, CNRS
Florence Azaïs, Chargé de recherche, CNRS
Arnaud Virazel, Professeur des universités, UM
Sophie Dupuis, Maître de conférences, UM
Associates & Students
Lila Ammoura, UM
Nassim Riadi, CNRS
Dorian Ronga, CNRS
André Martins Pio De Mattos, UM
Kamilia Tahraoui, UM
Xhesila Xhafa, CNRS
Julia Lefèvre, STMicroelectronics
Gianmarco Mongelli, STMicroelectronics
Douglas Almeida Dos Santos, UM
Regular Co-workers
Bruno Rouzeyre, Invité longue durée Eméritat, UM
The scientific activities of the TEST team are structured around four research topics addressing Reliability and Test issues:
• Topic 1: Digital, Analog and RF circuits
• Topic 2: Secure circuits
• Topic 3: Emerging Technologies and Paradigms
• Topic 4: Spatial and Radiative Environments
Topic 1 groups the “core activities” of the team and Topics 2, 3 and 4 are linked to the work carried out in the transversal themes of the Microelectronics department, taking into account specific constraints related to secure circuits, emerging technologies and paradigms as well as harsh environments.
Topic 1: Reliability and Testing of Digital, Analog and RF Circuits
The systems-on-a-chip have seen their surface increased by a factor of 10 and their consumption multiplied by 5 during the last ten years. Each technological node that allowed this integration also added new constraints that hindered the system reliability. For example, the increase of PVT variations or density, the nature of the defects, the adding of specific structures for controlling the power consumption …
It is therefore necessary to develop test and reliability improvement solutions in order to guarantee the production yield (the highest possible) and applicable during the life time of the system. Moreover, the integration of analog and RF blocks poses many problems, mainly related to the fact that the state-of-the-art methods used to test these blocks require to use specific test resources extremely expensive compared to digital resources available on a standard test equipment.
Topic 2: Reliability, Testing, Trust and Security of Integrated Circuits
The huge increase in the use of communicating systems has introduced security as a pivot of their development. In addition, as the design and manufacturing of these systems has become extremely complex operations and geographically distributed around the globe, new security and trust vulnerabilities have emerged. As a result, the entire hardware production flow has itself become subject to security and trust issues, including side channel attacks, reverse engineering, Intellectual Property (IP) hacking and hardware Trojan.
Topic 3: Reliability and Testing of Emerging Technologies
The planned end of the race for miniaturization is now leading the community towards a breakthrough, usually called “More than Moore”. The strategy in this context is to explore solutions related to the use of new materials, architectures, methods or design paradigms.
Axis 4: Reliability and, Testing in Space and Radiative Environments
Electronic components can operate in harsh environments and thus be subject to different sources of radiation depending on the application context (natural environments such as space and atmosphere or artificial environments such as particle accelerators or nuclear reactors).
These radiations can cause disturbances in the operation of integrated microelectronic systems. Many sensitive applications cannot tolerate a high failure rate because of their criticality. Due to the complexity of the effects induced by ionizing radiations, our work concerns the development of analysis and experimentation methods. In addition to the radiative effects, the effects of temperature are also taken into account.
HADES :
Hierarchy-Aware and secure embedded test infrastructure for Dependability and performance Enhancement of integrated Systems.
EDITSoC :
Electrical Diagnosis for IoT SoCs in automotive Diagnostic Electrique des Systèmes-sur-Puce dédiés aux Applications IoT pour le Secteur Automobile.
MOOSIC :
Multi-Objective Optimised Synthesis to Improve Cybersecurity.
LIA LAFISI :
French-Italian research LAboratory on hardware-software Integrated Systems.
The team members are strongly involved in the following conferences: ETS “European Test Symposium” (organization in 2013, Program Chair from 2015 to 2016, Publication Chair from 2015 to 2016 and Steering Committee members), VTS “VLSI Test Symposium” (Publication Chair since 2012, General chair in 2013 and Member of the Program Committee) and DATE “Design Automation and Test in Europe” (Program Vice Chair in 2016 and Program Chair in 2017, Member of the Executive Committee since 2013).
We also participate very actively in international conferences and workshops related to our research areas: IEEE Computer Society Annual Symposium VLSI (Program Co-Chair in 2016, General co-Chair in 2015, Track Chair from 2015 to 2017 and Publication Chair in 2015), Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (General Chair from 2013 to 2016 and Program Chair from 2013 to 2014), IEEE International Mixed-Signals Test Workshop (Chair of the Steering Committee from 2013 to 2016 and Program Chair in 2014). Members of the team are also involved in the review committees of major journals in our field: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Computers, JETTA – Journal of Electronic Testing – Theory and Applications, IEEE Transactions on Large Scale Integration Systems, IEEE Transactions on Emerging Topics in Computing, JOLPE – Journal of Low Power Electronics, ACM Journal of Emerging Technologies in Computing Systems.
We are also very active in the IEEE Computer Society European TTTC “Test Technology Technical Council” (Chair since 2014, Electronic Media Chair since 2012).
At the national level, we are strongly involved in the GdR SoC-SiP/SoC2 (Deputy Director, Responsible of the “Safety of Material Systems” working group, Members of the Steering Committee), in the pre-GdR Security (Member) and in the ERRATA GdR (Member).