OpenScale: Open-source multiprocessor hardware/software framework
OpenScale is a scalable and open-source NoC-based MPSoC platform, which can be used for design space exploration of MPSoCs.
OpenScale hardware is based on the replication of network processing units (NPUs), inside a 2D-mesh network-on-chip (NoC). Each NPU is composed of: (i) a SecretBlaze processor (ii) an embedded RAM and cache, (iii) an interrupt controller, (iv) a timer, (v) a UART, (vi) a NI, a (vii) HERMES-based router and a (viii) Wishbone v4 bus
(i) SecretBlaze :
- MicroBlaze ISA
- Optional Multiplier, Divider and Shift Register
- Optional branch predictor scheme coupled with branch target cache
- MMU-less design
(ii) Internal RAM and Cache :
- Instruction and Data Cache
- Tunable Write-Through or Copy Back policies
(iii) Hermes Router :
- XY Wormhole algorithm (predictive)
- Size tunable incoming FIFOs
- Round Robin Service algorithm
OpenScale provides a set of functions and services that can be used or even extended to allow different performance analysis (e.g. application latency). OpenScale provides design flexibility, allowing the execution of standalone application, as well as applications running onto a Real Time Operating System (RTOS). The developed RTOS was implemented in such a way that users can easily choose which features are needed in their implementation in order to either save memory or meet performance requirements.
This RTOS provides multi-threaded preemptive execution, using a scheduler based on thread priorities that is executed periodically according to a fixed timeslot, which can be defined by the user. A round robin scheduling algorithm is executed when all tasks have the same priority. Furthermore, the RTOS allows the use of semaphores and mutexes, communication between local and remote tasks, and dynamic memory allocation, as well.
OpenScale tools & prototyping
OpenScale provides a user interface that enables application compilation and hardware configuration, as illustrated in the figure below.
- Optional IOs (Timer, UART, Internal/External RAM, …)
- Memory size, FIFO size
- Cache sizes, cache policies
- Number of NPU
- Optional CPU optimization (Multiplier, Divider, Barrel Shifter)
OpenScale also provides simulation and synthesis scripts, which can be used for design space exploration of NoC-based MPSoCs. Further, Open-Scale has been successfully tested on Xilinx Virtex 5 ® and arrays of Spartan 3 ® FPGAs.
To download Open-Scale click HERE.
A tutorial covering the main platform features will be published soon.
A list of publications using the Open-Scale framework is available here. Feel free to contact us for referencing any published material based on Open-Scale.