MONDAY, DECEMBER 3rd, 2001

8:30 - 9:00 OPENING SESSION • Welcome • Program Introduction             9:00 - 9:45 PLENARY SESSION A   Design Technology for Systems-on-Chip (abstract)   R. Camposano, Synopsys             9:45 - 10:00 Coffee Break             10:00 - 11:00 SESSION 1.a: High Level Design Methodologies         Moderators: K.H. Diener, FhG IIS/EAS L. Maillet-Contoz, ST-Microelectronics • A Standardized Co-Simulation Backbone B.A. de Mello, F.R. Wagner Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil. • Automatic Code-Transformations, and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory S. Meftali, F. Gharsalli, F. Rousseau, A.A. Jerraya TIMA laboratory, Grenoble, France. • Design and Synthesis of Behavioral Level Virtual Components S. Pillement, O. Sentieys, D. Chillet, E. Casseau, P. Coussy, E. Martin, G. Savaton, S. Roux LASTI-ENSSAT, Lannion, France.       10:00 - 11:00 SESSION 1.b: Interconnects         Moderators: R. Reis, UFRGS D. Deschacht, LIRMM • Fast Estimation of Interconnect Delay Prior to Routing C. Chen, M. Ahmadi University of Windsor, Ontario, Canada. • Closed-Form Models for Inter- and Intra-Layer Capacitance in a VDSM CMOS Technology D. Bernard, C. Landrault, P. Nouet LIRMM / Univ. Montpellier II, Montpellier, France. • High-Speed Driven Technological Improvements Impact on Interconnect Thermal M. Casu, M. Graziano, G. Masera, G. Piccinini, M. Zamboni Electronics dept., Politecnico di Torino, Torino, Italy.             11:00 - 11:15 Coffee Break             11:15 - 12:15 SESSION 2.a: FPGA-based Reconfigurable Architectures         Moderators: C. Robach, LCIS/INPG M. Paindavoine, U. Bourgogne • Proposition of Temporal Partitioning Methodology for Optimization of Run-Time-Reconfiguration Implementation of Data-Path in FPGA C. Tanougast, Y. Berviller, S. Weber L.I.E.N., Vandoeuvre, France. • FPGA Fully Reconfigurable Lifting Kernel for Multimedia Processing M. Martina, G. Masera, G. Piccinini, F. Vacca, M. Zamboni Dipartimento di Elettronica - Politecnico di Torino, Torino, Italy. • ARCHITECT-R: A System for Reconfigurable Robots Design - An Overview and Initial Results R.A. Gonçalves, D.F. Wolf, M.I. Rodrigues, L.F. Osorio, P.A. Moraes, L.B. Genuário, M.A. Teixeira, A.A.L. Ribeiro, R.A.F. Romero, E. Marques Instituto de Ciências Matemáticas e de Computação - ICMC/USP, São Carlos-SP, Brazil.       11:15 - 12:15 SESSION 2.b: Power Issues         Moderators: O. Sentieys, ENSSAT P. Girard, LIRMM • Dynamic Power Simulation Model for VLIW DSP Processor VLSI Cores with Secure Applications R. Muresan, C. Gebotys University of Waterloo, Canada, Kitchener ON, Canada. • Power Consumption Model for the DSP OAK Processor C. Belleudy, P. Guitton-Ouhamou, M. Auguin Laboratoire I3S, Sophia-Antipolis Cedex, France. • Technology Mapping for Low Power SOC Using Genetic Algorithms G.R. Cho, T. Chen Colorado State University, Fort Collins, USA.             12:15 - 14:15 Lunch             14:15 - 15:15 SESSION 3.a: Architectures for Signal Processing         Moderators: P. Ienne, EPFL S. Pillement, ENSSAT • Two ASICs for Low and Middle Levels of Real Time Image Processing P. Lamaty, B. Mazar, D. Demigny, L. Kessal, M. Karabernou ETIS, Cergy Pontoise, France. • Optimized CORDIC Implementations based on Iterative and Unfolded Architectures H. Kebbati, J.Ph. Blonde, F. Braun Laboratoire d'électonique et de Physique des Systèmes Instrumentaux, Strasbourg, France. • Images Filtering VLSI for the Optical Character Reading A. Lamine, G. Bouvier, A. Bouhdada Faculté des Sciences, Casablanca, Morocco.       14:15 - 15:15 SESSION 3.b: Digital Testing         Moderators: M. Marzouki, LIP6/ASIM M. Renovell, LIRMM • Sessionless Test Scheme: Power-constrained Test Scheduling for System-on-a-Chip M.L. Flottes, J. Pouget, B. Rouzeyre LIRMM, Montpellier, France. • RSIC Generation: A Solution for Logic BIST R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel LIRMM, Montpellier, France. • Mutation Testing Applied to Hardware: the Mutants Generation T.B. Nguyen, C. Robach LCIS-ESISAR, Valence, France.             15:15 - 15:30 Coffee Break             15:30 - 16:30 SESSION 4.a: Verification & Validation (1)         Moderators: D. Borrione, TIMA/INPG J. Rampon, Simplicity • Formal Verification on the RT Level - Computing One-To-One Design Abstractions by Signal Width Reduction P. Johannsen, R. Drechsler Siemens Corporation, Munich, Germany. • Functional Test Generation using Constraint Logic Programming Z. Zeng, M. Ciesielski, B. Rouzeyre Univ. Ahmherst, Montpellier, France. • Efficient Verification of Sequential Circuits with Same State Encoding R. Mukherjee, J. Jain, V. Boppana, M. Fujita Fujitsu Laboratories of America, Sunnyvale, CA, USA.       15:30 - 16:30 SESSION 4.b: Signal Integrity         Moderators: D. Demigny, ENSEA P. Nouet, LIRMM/U. Montpellier • Crosstalk Prediction: a New Expression for Taking Into Account On-Chip Inductance G. Servel, D. Deschacht, F. Saliou, J.L. Mattei, F. Huret LIRMM/Université Montpellier II, Montpellier, France. • Efficient Green's Functions for Substrate Coupling Modeling in VLSI Circuits N. Masoumi, S. Safavi-Naeini, M.I. Elmasry VLSI Research Group, Waterloo, Canada. • Simulation of electromagnetic radiations produced by integrated circuits J.Y. Oberle Texas Instruments France, Villeneuve Loubet, France.             16:30 - 16:45 Coffee Break             16:45 - 17:45 SESSION 5.a: SoC Design Methodologies         Moderators: F. Rousseau, TIMA/INPG G. Cambon, LIRMM/U. Montpellier • Virtual System Prototyping with Pre-verified IP Cores P. Bricaud , A. Vignollet Mentor Graphics, Sophia-Antipolis, France. • Enabling Reuse via an IP Core-centric Communications Protocol: Open Core Protocols W.D. Weber, P. Martin SONICS, Sophia Antipolis, France. • Bus Analysis and Performance Evaluation on a SOC Platform at the System Level Design G. Pelissier, R. Hersemeule, L. Torres, G. Cambon, M. Robert LIRMM/Université de Montpellier, Montpellier, France.       16:45 ­ 17:45 SESSION 5.b: Design for Specific Constraints         Moderators: M. Glesner, U. Darmstadt C. Landrault, LIRMM • A Comparative Study on Fault Secure Signed Multiplication Designs K.S. Papadomanolakis, A.P. Kakarountas, V. Kokkinos, N. Sklavos, C.E. Goutis University of Patras, Patras, Greece. • Integration of Robustness in the Design of a Cell J.M. Dutertre, F.M. Roche, G. Cathebras LIRMM/UM2, Montpellier, France. • Impact of Technology Spreadings on MEMS Design Robustness V. Beroulle, L. Latorre, M. Dardalhon, O. Coumar, G.Perez, F. Pressecq, P. Nouet LIRMM, Montpellier, France.             20:00 RECEPTION

TUESDAY, DECEMBER 4th, 2001

9:00 - 9:45 PLENARY SESSION B   Philips' Approach to Core-Based System Chip Testing (abstract)   E.J. Marinissen, Philips             9:45 - 10:00 Coffee Break             10:00 - 11:00 SESSION 6.a: Architectures         Moderators: F. Moraes, PUCRS J. Galy, LIRMM/U. Montpellier • A New VLSI Architecture for Full Search Block Matching N. Roma, L. Sousa Instituto Superior Técnico / INESC-ID, Lisboa, Portugal. • An Improved Digital Quadrature Frequency Up-converter Architecture F. Curticapean, J. Niittylahti Digital Media Institute / Digital and Computer Systems Laboratory, Tampere, Finland. • Design Considerations for a Low-Power, Low-Complexity Turbo Decoder S. Pisuk, P. Wu MIT Lincoln Laboratory, Lexington, USA.       10:00 - 11:00 SESSION 6.b: Low Power / Low Voltage         Moderators: E. Martin, LESTER/U. Bretagne Sud E. Schmidt, OFFIS • Low-Voltage 0.25µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors B. Curran, M. Gifaldi, J. Martin, A. Buyuktosunoglu, M. Margala, D. Albonesi University of Rochester, Rochester, New York, USA. • Technological Assignment for a Minimal Power Consumption P. Maurine, N. Azemard, D. Auvergne LIRMM, Montpellier, France. • Encoding Schemes for Address Buses in Energy Efficient SOC Designs J. Henkel, H. Lekatsas, V. Jakkula NEC USA Inc., Princeton, New Jersey, USA.             11:00 - 11:15 Coffee Break             11:15 - 12:15 SESSION 7.a: Dynamically Reconfigurable Architectures         Moderators: R. Hartenstein, U. Kaiserslautern S. Weber, LIEN • A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals R. David, D. Chillet, S. Pillement, O. Sentieys ENSSAT, Lannion, France. • A Dynamically Reconfigurable Architecture for High Throughput Processing G. Sassatelli, L. Torres, C. Diou, G. Cambon, M. Robert, J. Galy LIRMM, Montpellier, France. • Reconfigurable Architecture using High Speed FPGA L. Kessal, R. Bourguiba, D. Demigny, N. Boudouani, M. Karabernou ETIS - ENSEA/UCP URA D2235 CNRS, Cergy Pontoise, France.       11:15 - 12:15 SESSION 7.b: Cells and Libraries         Moderators: A. Amara, ISEP D. Auvergne, LIRMM/U. Montpellier • Design of a Branch-Based Carry-Select Adder IP portable in 0.25 µm Bulk and Silicon-on-Insulator CMOS Technologies A. Nève, D. Flandre Laboratoire de Microélectronique, Louvain-la-Neuve, Belgium. • Montgomery Modular-Multiplication IP Core A. Pérez, J.M. Portal, A. Labbé L2MP-ICF (UMR CNRS 6137), Marseille, France. • Low-Power Low-Voltage Standard Cell and Gate-Array Libraries with a Limited Number of Cells J.M. Masgonty, S. Cserveny, C. Arm, P.D. Pfister, M.C. Pasquier, C. Piguet CSEM, Neuchatel, Switzerland.             12:15 - 14:15 Lunch             14:15 - 15:15 SESSION 8.a: CAD Tools (1)         Moderators: F. Wagner, UFRGS N. Azémard, LIRMM • Distributed Collaborative Design over Cave2 Framework L.S. Indrusiak, J. Becker, M. Glesner, R. Reis Informatica-UFRGS, Porto Alegre, Brazil. • ProtoEnvGen - Rapid Prototyping Environment Generator M. Cakir, E. Grimpe University Oldenburg / Germany, Oldenburg, Germany. • A Design Approach of Reusable Cores A. Landrault, L. Pellier, A. Richard, C. Jay, M. Robert, D. Auvergne Infineon Technologies, Sophia Antipolis, France.       14:15 - 15:15 SESSION 8.b: Sensors         Moderators: P. Fouillat, IXL/U. Bordeaux F. Azaïs, LIRMM • A CMOS MEMS for magnetic field sensing with improved SNR V. Beroulle, Y. Bertrand, L. Latorre, P. Nouet LIRMM, Montpellier, France. • Design of a Fast CMOS APS Imager for High Speed Laser Detections B. Casadei, J.P. Lenormand, B. Cunin, Y. Hu Strasbourg, France. • Development of a System on Chip Integrating a Porous Silicon Based Humidity Sensor with a Porous Silicon based Seven Segment Display H. Saha, S. Dey, J. Das, S.M. Hossain IC Centre, Dept of ETCE, Jadavpur University, Calcutta, India.             15:15 - 15:30 Coffee Break             15:30 - 16:30 SESSION 9.a: Signal & Image Processing         Moderators: H. Hugli, U. Neuchâtel L. Torres, LIRMM/U. Montpellier • 64 x 64 Pixels General Purpose Digital Vision Chip T. Komuro, M. Ishikawa The University of Tokyo, Bunkyo-ku, Tokyo, Japan. • A Vision System on Chip for Industrial Control E. Senn., D. Emzivat, E. Martin LESTER - University of South-Brittany, Lorient, France. • Fast Recursive Implementation of the Gaussian Filter D. Demigny, L. Kessal, J. Pons ETIS, Cergy Pontoise, France.       15:30 - 16:30 SESSION 9.b: Analog Testing         Moderators: J. Figueras, UPC • On-Chip Generator of a Saw-Tooth Test Stimulus for ADC BIST F. Azaïs, S. Bernard, Y. Bertrand, M. Renovell LIRMM, Montpellier, France. • Built-In Test of Analog Non-Linear Circuits in a SOC Environment L. Carro, A.C. Nácul, D. Janner, M. Lubaszewski Universidade Federal do Rio Grande do Sul, Porto Alegre/RS, Brazil. • An Embedded Iddq/delta Iddq BIST for Analog and Mixed-Signal Cores in System-on-Chip Test Applications S. Dragic, M. Margala University of Rochester, Rochester, New York, USA.             16:30 - 16:45 Coffee Break             16:45 - 17:25 SESSION 10.a: CAD Tools (2)         Moderators: C. Jay, Infineon D. Leclerc, Synopsys • High Performance Java Hardware Engine and Software Kernel for Embedded Systems M.H. Miki, M. Kimura, T. Onoye, I. Shirakawa Osaka University, Suita, Japan. • An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures J.C. Otero, F.R. Wagner Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil.       16:45 ­ 17:25 SESSION 10.b: Power Applications         Moderators: Y. Bertrand, LIRMM/U. Montpellier P. Nouet, LIRMM/U. Montpellier • What Makes a Power SoC Different? B. Allard, J.L. Schanen, D. Bergogne, H. Morel CEGELY-INSA Lyon, Villeurbanne, France. • IP Modules for Motor Control FPGA/ASIC Integration Y. Kebbati, Y.A. Chapuis, F. Braun Laboratoire d'Electronique et de Physique des Systèmes Instrumentaux, Strasbourg, France.

WEDNESDAY, DECEMBER 5th, 2001

9:00 - 9:45 PLENARY SESSION C   Low-Voltage Embedded-RAM Technology: Present and Future (abstract)   K. Itoh, Hitachi             9:45 - 10:00 Coffee Break             10:00 - 11:00 SESSION 11.a: Verification & Validation (2)         Moderators: M. Velev, Carnegie Mellon University M. Ciesielski, U. Massachussetts/Amherst • Fast and Efficient Equivalence Checking based on NAND-BDDs R. Drechsler, M. Thornton University of Freiburg, Germany. • Compact BDD Representations for Multiple-Output Functions and Their Application T. Sasao, M. Matsuura, Y. Iguchi, S. Nagayama Department of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka, Japan. • Mechanizing a Proof of Completeness for a Set of RTL Transformations E. Teica, R. Vemuri University of Cincinnati, Cincinnati, U.S.A.       10:00 - 11:00 SESSION 11.b: Timing Issues         Moderators: S. Pravossoudovitch, LIRMM/U. Montpellier L. Latorre, LIRMM/U. Montpellier • Digital Full Custom Design - Key Technology for System-on-Chip Integration C. Heer, W. Kamp, R. Künemund Infineon Technologies, München, Germany. • Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems J.B. Rigaud, J. Quartana, L. Fesquet, M. Renaudin TIMA Laboratory, Grenoble, France. • Timing Closure Management based on Delay Bound Determination N. Azemard, M. Aline, P. Maurine, D. Auvergne LIRMM, Montpellier, France.             11:00 - 11:15 Coffee Break             11:15 - 12:15 SESSION 12.a: IP Reuse         Moderators: M. Lubaszewski, UFRGS • New Approach to Design for Reusability of Datapath Architectures in System-on-Chips M. Margala, H. Wang University of Rochester, Rochester, New York, USA. • Abstract Communication Model and Automatic Interface Generation for IP Integration in Hardware/Software Co-design C. Araujo, E. Barros Centro de Informática UFPE, Paulista - PE, Brazil. • A Novel Approach to Design Space Exploration of Parameterized SOCs G. Ascia, V. Catania, M. Palesi DIIT - University of Catania, Catania, Italy.       11:15 - 12:15 SESSION 12.b: Advance in Mixed Signal         Moderators: D. Mlynek, EPFL S. Bernard, LIRMM • A Digital Decimation Filter Architecture for a Three Channel 20 bits Sigma-Delta Converter J.P. Ferlet, F. Anstotz, L. Hebrard, F. Braun LEPSI, Strasbourg, France. • CMOS Mixed-Signal Circuits Design on a Digital Array Using Minimum Transistors J.H. Choi, S. Bampi Federal University of Rio Grande do Sul, Porto Alegre, Brazil. • A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd Generation MOS Model of a Deep Submicron Transistor C. Lallement, F. Pecheux, Y. Herve PHASE/ERM, Illkirch, France.             12:15 - 14:15 Lunch