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Monday
December 3, 2001
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Tuesday
December 4, 2001
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Wednesday
December 5, 2001
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8:30 - 9:00
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OPENING SESSION
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9:00 - 9:45
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PLENARY SESSION A
Design Technology for SoC
R. Camposano, Synopsys
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PLENARY SESSION B
Core-Based System Chip Testing
E.J. Marinissen, Philips
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PLENARY SESSION C
Low-Voltage Embedded-RAM Technology: Present & Future
K. Itoh, Hitachi
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9:45 - 10:00
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Coffee Break
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Coffee Break
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Coffee Break
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10:00 - 11:00
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SESSION 1.a
High Level Design Methodologies
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SESSION 1.b
Interconnects
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SESSION 6.a
Architectures
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SESSION 6.b
Low Power / Low Voltage
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SESSION 11.a
Validation & Verification (2)
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SESSION 11.b
Timing Issues
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11:00 - 11:15
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Coffee Break
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Coffee Break
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Coffee Break
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11:15 - 12:15
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SESSION 2.a
FPGA-based Reconfigurable
Architectures
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SESSION 2.b
Power Issues
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SESSION 7.a
Dynamically Reconfigurable
Architectures
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SESSION 7.b
Cells and Libraries
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SESSION 12.a
IP Reuse
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SESSION 12.b
Advance in Mixed-Signal
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12:15 - 14:15
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Lunch
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Lunch
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Lunch
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14:15 - 15:15
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SESSION 3.a
Architectures for Signal
Processing
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SESSION 3.b
Digital Testing
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SESSION 8.a
CAD Tools (1)
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SESSION 8.b
Sensors
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15:15 - 15:30
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Coffee Break
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Coffee Break
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15:30 - 16:30
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SESSION 4.a
Verification & Validation (1)
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SESSION 4.b
Signal Integrity
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SESSION 9.a
Signal & Image Processing
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SESSION 9.b
Analog Testing
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16:30 - 16:45
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Coffee Break
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Coffee Break
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16:45 - 17:45
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SESSION 5.a
SoC Design Methodologies
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SESSION 5.b
Design for Specific Constraints
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SESSION 10.a
CAD Tools (2)
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SESSION 10.b
Power Applications
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CONFERENCE
RECEPTION
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