TUESDAY, APRIL 10


 

Registration

8:15 - 9:00

Opening session

Paolo Bernardi (Politecnico di Torino), General Chair
Alberto Bosio (LIRMM), Mario Barbareschi (Università di Napoli Federico II), Program Co-Chairs
9:00 - 9:30

Keynote 1

Moderator: Alberto Bosio (LIRMM)
9:30 - 10:30
THE DIGITAL REVOLUTION: THE INDUSTRY PERSPECTIVE
Carmelo PAPA (STMicroelectronics)

Poster Session 1


10:30 - 11:00
ANALOG FAULT SIMULATION AUTOMATION AT SCHEMATIC LEVEL WITH RANDOM SAMPLING TECHNIQUES
Liang WU, Mohammad Khizer HUSSAIN, Saed ABUGHANNAM, Wolfgang MULLER, Christoph SCHEYTT (Heinz Nixdorf Institute), Wolfgang ECKER (Infineon Technologies AG)
METHODOLOGY FOR IMPROVED EVENT-DRIVEN SYSTEM-LEVEL SIMULATION OF AN RF TRANSCEIVER SUBSYSTEM FOR WIRELESS SOCS
Fabian SPEICHER, Christoph BEYERSTEDT, Markus SCHOLL, Tobias SAALFELD, Vahid BONEHI, Moritz SCHREY, Ralf WUNDERLICH, Stefan HEINEN (RWTH Aachen University)
A NOVEL HARDWARE-ACCELERATED REAL-TIME TASK SCHEDULER BASED ON ROBUST EARLIEST DEADLINE ALGORITHM
Lukas KOHUTKA, Viera STOPJAKOVA (Slovak University of Technology in Bratislava)
DYNAMIC PARTIAL RECONFIGURATION VERIFICATION USING ASSERTION BASED VERIFICATION
Islam AHMED (Mentor Graphics), Hassan MOSTAFA, Ahmed MOHIELDIN (Electronics and Communications Engineering Department, Cairo University)
MEMRISTOR BASED ADAPTIVE IMPEDANCE AND FREQUENCY TUNING NETWORK
Chithra PALSON, Deepti KRISHNA (Rajagiri School of Engineering & Technology), Jimson MATHEW (Indian Institute of Technology Patna), ROSLIND JOSE BABITA (Division of Electronics Engineering, School of Engineering, Cochin University of Science and Technology, Kochi-39), OTTAVI Marco (Department of Electronic Engineering, University of Rome Tor Vergata, Rome)

Session 1: Test strategies

Session Chair: Luigi Dilillo (LIRMM)
11:00 - 12:30
A FULLY CONTACTLESS WAFER-LEVEL TESTING FOR UHF RFID TAG WITH ON-CHIP ANTENNA
Alberto PAGANI, Alessandro MOTTA, Giovanni GIRLANDO, Alessandro FINOCCHIARO (STMicroelectronics)
CHALLENGES AND EMERGING SOLUTIONS IN TESTING HBM IO AND SYSTEMS
Salem ABDENNADHER (Intel Corporation), Michael ALTMANN, Bin XUE (Intel)
THE TEST COST REDUCTION BENEFITS OF COMBINING A HIERARCHICAL DFT METHODOLOGY WITH EDT CHANNEL SHARING–A CASE STUDY
Rick FISETTE (Mentor Graphics), Binghua LU, Selina SHA, Jincheng WANG, Zhigao ZHANG (Spreadtrum), Fanjin MENG (Mentror Graphics), Dragon HSU (Mentor Graphics)

Lunch

12:30 - 14:30

Session 2: Reliability issues and solutions

Session Chair: Petr Fiser (Czech Technical University in Prague)
14:30 - 16:00
TRADING-OFF RELIABILITY AND PERFORMANCE IN FPGA-BASED RECONFIGURABLE HETEROGENEOUS SYSTEMS
Alessandro VALLERO, Carelli ALBERTO, Stefano DI CARLO (Politecnico di Torino)
PARALLEL SOFTWARE-BASED SELF-TEST SUITE FOR MULTI-CORE SYSTEM-ON-CHIP: MIGRATION FROM SINGLE-CORE TO MULTI-CORE AUTOMOTIVE MICROCONTROLLERS
Davide PIUMATTI, Andrea FLORIDIA, ERNESTO SANCHEZ (Politecnico di Torino), Sergio DE LUCA, Alessandro SANSONETTI (STMicroelectronics)
IS APROXIMATE COMPUTING SUITABLE FOR SELECTIVE HARDENING OF ARITHMETIC CIRCUITS?
Bastien DEVEAUTOUR, Arnaud VIRAZEL, Patrick GIRARD, Serge PRAVOSSOUDOVITCH (LIRMM), Valentin GHERMAN (CEA LIST)

Poster Session 2


16:00 - 16:30
UNIFIED FIELD MULTIPLIER FOR ECC: INHERENT RESISTANCE AGAINST HORIZONTAL SCA ATTACKS
Ievgen KABIN, Zoya DYKA, Dan KREISER, Peter LANGENDOERFER (IHP)
SECCS: SECURE CONTEXT SAVING FOR IOT DEVICES
Emanuele VALEA, Mathieu DA SILVA, Giorgio DI NATALE, Marie-Lise FLOTTES, Bruno ROUZEYRE (LIRMM)
TWO DIMENSIONAL FFT ARCHITECTURE WITH EFFICIENT OUTPUT REORDERING
Jimson MATHEW (Indian Institute of Technology Patna)
AN AUTOMATIC APPROACH TO INTEGRATION TESTING FOR CRITICAL AUTOMOTIVE SOFTWARE
Jacopo SINI, Alessandra MUGONI, Massimo VIOLANTE (Politecnico di Torino), Aldo QUARIO, Concetta ARGIRI, Flavio FUSETTI (TXT e-solutions SpA)
SETUP AND EXPERIMENTAL RESULTS ANALYSIS OF CCD AND COTS SRAMS TESTS AT THE ISIS FACILITY
Marco OTTAVI, Dario ASCIOLLA, Tiziano FIORUCCI, Elena GROSSO, Carla MARZULLO, Alessandro SCARAMELLA, Simone STRAMACCIONI ,  Alessia ZIBECCHI, Carla ANDREANI, Gian Carlo CARDARILLI (University of Rome), Carlo CAZZANIGA (Rutherford Appleton Laboratory-ISIS), Luca DI NUNZIO, Rocco FAZZOLARI, Marco RE (University of Rome), Pedro REVIRIEGO (Universidad Antonio de Nebrija), Gianluca FURANO (EUROPEAN SPACE AGENCY), Roberto SENESI (University of Rome)

Session 3: Technology I

Session Chair: Hassen Haziza (IM2NP - Aix-Marseille Université)
16:30 - 18:00
DEVICE AND CIRCUIT MODELS OF INALN/GAN D- AND DUAL-GATE E-MODE HEMTS FOR DESIGN AND CHARACTERISATION OF MONOLITHIC NAND LOGIC CELL
Ales CHVALA, Lukas NAGY, Juraj MAREK, Juraj PRIESOL, Daniel DONOVAL (Slovak University of Technology in Bratislava), Alexander SATKA (Slovak University of Technology), Michal BLAHO, Dagmar GREGUSOVA, Jan KUZMIK (Slovak Academy of Sciences)
AMMONIA SENSORS BASED ON IN SITU FABRICATED NANOCRYSTALLINE GRAPHENE FIELD-EFFECT DEVICES
Dennis NOLL (Technische Universität Darmstadt), Udo SCHWALKE (TU Darmstadt)
RECONFIGURABLE ELECTROSTATICALLY DOPED 2.5-GATE PLANAR FIELD-EFFECT TRANSISTORS FOR DOPANT-FREE CMOS
Tillmann KRAUSS (Technische Universität Darmstadt), Frank WESSELY, Udo SCHWALKE (TU Darmstadt)

WEDNESDAY, APRIL 11


Registration

8:00 - 8:30

Session 4: Technology II

Session Chair: Zoran Stamenkovic (IHP)
8:30 - 10:00
ANALYTICAL MODELING OF RESPONSE TIME AND FULL WELL CAPACITY OF A PINNED PHOTO DIODE
Akshay K,  Parvathy R PILLAI, Bhuvan B (National Institute of Technology, Calicut)
AN ENERGY-AUTONOMOUS WIRELESS SENSOR NETWORK DEVELOPMENT PLATFORM
Michelangelo GROSSO, Salvatore RINAUDO (STMicroelectronics s.r.l.), Andrea ACQUAVIVA, Edoardo PATTI (Politecnico di Torino)
A POWER-SUPPLY NOISE AWARE DYNAMIC TIMING ANALYSIS METHODOLOGY, BASED ON A STATISTICAL PREDICTION ENGINE
Michael TSIAMPAS (Helic Inc.), Nestor EVMORFOPOULOS (Department of Electrical and Computer Engineering, University of Thessaly), Konstantis DALOUKAS (Helic Inc.), John MOONDANOS, Georgios STAMOULIS (Department of Electrical and Computer Engineering, University of Thessaly)

Poster Session 3


10:00 - 10:30
A RESOURCE-EFFICIENT FFT/IFFT ARCHITECTURE FOR PRIME PLC SYSTEMS
Jing YANG, Nianxiong TAN (Zhejiang University), Ching-Kae Harris TZOU (Hangzhou Vango Communications, Inc)
CONFIGURABLE OPERATIONAL AMPLIFIER BASED ON OXIDE RESISTIVE RAMS
Hassen AZIZA, Christian DUFAZA , Annie PEREZ (IM2NP - Aix-Marseille Université)
SIC PAIR GENERATION IN NEAR-OPTIMAL TIME WITH CARRY-LOOK AHEAD ADDERS
Ioannis VOYIATZIS, Costas EFSTATHIOU (TEI of Athens)
CROSS-PRODUCT FUNCTIONAL COVERAGE ANALYSIS USING MACHINE LEARNING CLUSTERING TECHNIQUES
Eman EL MANDOUH (Mentor Graphics, Siemens Bussiness), Ashraf SALEM, Mennatallah AMER (Mentor Graphics), Amr G. WASSAL (Cairo University)
WIRELESS SEMG/FOOTSWITCH DRIVEN FPGA EMBEDDED DIGITAL PROCESSOR FOR DYNAMIC MFCV ESTIMATION
Giovanni MEZZINA, Vito Leonardo GALLO, Daniela DE VENUTO (Politecnico di Bari)

Session 5: Temperature-Aware Design

Session Chair: Andreas Leininger (Intel)
10:30 - 12:00
EVALUATION OF A MEDIAN THRESHOLD BASED EEPROM-PUF CONCEPT IMPLEMENTED IN A HIGH TEMPERATURE SOI CMOS TECHNOLOGY
Benjamin WILLSCH (Fraunhofer Institute for Microelectronic Circuits and Systems)
THERMAL ANALYSIS APPROACH FOR PREDICTING POWER DEVICE LIFETIME
Sebastiano RUSSO, Gaetano BAZZANO, Daniela Grazia CAVALLARO, Alessandro SITTA, Michele CALABRETTA (STMicroelectronics)
EVALUATION OF THE TEMPERATURE INFLUENCE ON SEU VULNERABILITY OF DICE AND 6T-SRAM CELLS
Emna FARJALLAH, Valentin GHERMAN, Jean-marc ARMANI (CEA LIST), LUIGI DILILLO (LIRMM)

Lunch

12:00 - 13:30

Keynote 2

Moderator: Carmen G. Almudever (TU Delft)
13:30 - 14:30
QUANTUM COMPUTATION: PROSPECTS AND CHALLENGES
Robert WILLE (JOHANNES KEPLER UNIVERSITY LINZ)

Special Session: The Engineering Challenges for Quantum Computing


Organizers: Carmen G. Almudever, Nader Khammassi (TU Delft)
14:30 - 16:00
HETEROGENEOUS QUANTUM COMPUTING: THE NEXT ACCELERATOR TECHNOLOGY
Koen BERTELS (QuTech, Delft University of Technology)
CRYO-CMOS PLATFORMS FOR THE CLASSICAL CONTROL OF QUANTUM PROCESSORS
Masoud BABAIE (TU Delft)
Si MOS technology for spin-based quantum information
Louis Hutin (CEA-LETI)

THURSDAY, APRIL 12


Registration

9:00 - 9:30

Embedded Tutorial

Moderator: Alberto Bosio (LIRMM)
9:30 - 10:30
A NOVEL MAC PROTOCOL FOR INDUSTRIAL WLAN: HARDWARE ASPECTS
Zoran STAMENKOVIC (IHP)

Poster Session 4


10:30 - 11:00
PROGRAMMABLE LOGIC FOR SINGLE-OUTPUT FUNCTIONS
Ioannis VOYIATZIS, Costas EFSTATHIOU (TEI of Athens)
GIVE ME YOUR BINARY, I'LL TELL YOU IF IT LEAKS
Antoine BOUVET (Secure-IC), Adrien FACON (Secure-IC / Département d'informatique de l'ENS, CNRS), Sylvain GUILLEY (Secure-IC / LTCI, CNRS, Télécom ParisTech / Département d'informatique de l'ENS, CNRS), Damien MARION (Secure-IC / LTCI, CNRS, Télécom ParisTech)
TOWARDS NOVEL FORMAT FOR REPRESENTATION OF POLYMORPHIC CIRCUITS
Adam CRHA, Vaclav SIMEK, Richard RUZICKA (Brno University of Technology)
A 1KX32 BIT WDSRAM PAGE WITH RAPID WRITE ACCESS
Theodoros SIMOPOULOS (University of Patras), Themistoklis HANIOTAKIS (Southern Illinois University Carbondale, USA), George ALEXIOU (University of Patras, Greece)

Session 6: Design

Session Chair: Michelangelo Grosso (STMicroelectornics)
11:00 - 12:30
OPTIMUM POLYMORPHIC CIRCUITS SYNTHESIS METHOD
Petr FISER (Czech Technical University in Prague), Vaclav SIMEK (Brno University of Technology)
LOW-ENERGY KEY EXCHANG FOR AUTOMATION SYSTEMS
Dan KREISER, Zoya DYKA, Ievgen KABIN, Peter LANGENDOERFER (IHP)
IMPACT OF DYNAMIC PARTIAL RECONFIGURATION ON CONNECT NETWORK-ON-CHIP FOR FPGAS
Rami ALI (Mentor Graphics, a Siemens Business), Hassan MOSTAFA, Ahmed HUSSEIN (Electronics and Communications Engineering Department, Cairo University)

Closing Session

12:30 - 13:00

Lunch

13:00 - 14:30
DTIS 2018