TEST: Test and dEpendability of microelectronic integrated SysTems
The TEST (Test and dEpendability of Integrated Microelectronics SysTems) team’s main objective is the development of models, methods and tools to ensure the post-production quality of integrated
microelectronic devices. The team focuses on designing test-ready integrated systems to make post-production verification steps simpler, more efficient and less costly. Our main contributions harness emerging tech-nologies, as we pay particular attention to complexity, variability and consumption issues, non-monolithic integration approaches with 3D integration technologies, and to novel devices in the development of reliability and test approaches. This research is most often accompanied by the development of new test methods, but also relies on proposing fault models or designing hardware architectures which are integrated into the systems to
monitor their performance throughout their life cycle.
Research topics
The scientific activities of the TEST team are structured around four research topics addressing Reliability and Test issues:
• Topic 1: Digital, Analog and RF circuits
• Topic 2: Secure circuits
• Topic 3: Emerging Technologies and Paradigms
• Topic 4: Spatial and Radiative Environments
Topic 1 groups the “core activities” of the team and Topics 2, 3 and 4 are linked to the work carried out in the transversal themes of the Microelectronics department, taking into account specific constraints related to secure circuits, emerging technologies and paradigms as well as harsh environments.
Topic 1: Reliability and Testing of Digital, Analog and RF Circuits
The systems-on-a-chip have seen their surface increased by a factor of 10 and their consumption multiplied by 5 during the last ten years. Each technological node that allowed this integration also added new constraints that hindered the system reliability. For example, the increase of PVT variations or density, the nature of the defects, the adding of specific structures for controlling the power consumption ...
It is therefore necessary to develop test and reliability improvement solutions in order to guarantee the production yield (the highest possible) and applicable during the life time of the system. Moreover, the integration of analog and RF blocks poses many problems, mainly related to the fact that the state-of-the-art methods used to test these blocks require to use specific test resources extremely expensive compared to digital resources available on a standard test equipment.
Topic 2: Reliability, Testing, Trust and Security of Integrated Circuits
The huge increase in the use of communicating systems has introduced security as a pivot of their development. In addition, as the design and manufacturing of these systems has become extremely complex operations and geographically distributed around the globe, new security and trust vulnerabilities have emerged. As a result, the entire hardware production flow has itself become subject to security and trust issues, including side channel attacks, reverse engineering, Intellectual Property (IP) hacking and hardware Trojan.
Topic 3: Reliability and Testing of Emerging Technologies
The planned end of the race for miniaturization is now leading the community towards a breakthrough, usually called “More than Moore”. The strategy in this context is to explore solutions related to the use of new materials, architectures, methods or design paradigms.
Axis 4: Reliability and, Testing in Space and Radiative Environments
Electronic components can operate in harsh environments and thus be subject to different sources of radiation depending on the application context (natural environments such as space and atmosphere or artificial environments such as particle accelerators or nuclear reactors).
These radiations can cause disturbances in the operation of integrated microelectronic systems. Many sensitive applications cannot tolerate a high failure rate because of their criticality. Due to the complexity of the effects induced by ionizing radiations, our work concerns the development of analysis and experimentation methods. In addition to the radiative effects, the effects of temperature are also taken into account.
Research Contracts
TRUDEVICE :
Trustworthy Manufacturing and Utilization of Secure Devices
CLERECO :
Cross-Layer Early Reliability Evaluation for the Computing cOntinuum
MTCUBE :
Memory Test CUBEsat
TEEVA :
TEEVA - Trusted Execution Environment
Outreach
The team members are strongly involved in the following conferences: ETS “European Test Symposium” (organization in 2013, Program Chair from 2015 to 2016, Publication Chair from 2015 to 2016 and Steering Committee members), VTS “VLSI Test Symposium” (Publication Chair since 2012, General chair in 2013 and Member of the Program Committee) and DATE “Design Automation and Test in Europe” (Program Vice Chair in 2016 and Program Chair in 2017, Member of the Executive Committee since 2013).
We also participate very actively in international conferences and workshops related to our research areas: IEEE Computer Society Annual Symposium VLSI (Program Co-Chair in 2016, General co-Chair in 2015, Track Chair from 2015 to 2017 and Publication Chair in 2015), Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (General Chair from 2013 to 2016 and Program Chair from 2013 to 2014), IEEE International Mixed-Signals Test Workshop (Chair of the Steering Committee from 2013 to 2016 and Program Chair in 2014). Members of the team are also involved in the review committees of major journals in our field: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Computers, JETTA - Journal of Electronic Testing - Theory and Applications, IEEE Transactions on Large Scale Integration Systems, IEEE Transactions on Emerging Topics in Computing, JOLPE - Journal of Low Power Electronics, ACM Journal of Emerging Technologies in Computing Systems.
We are also very active in the IEEE Computer Society European TTTC “Test Technology Technical Council” (Chair since 2014, Electronic Media Chair since 2012).
At the national level, we are strongly involved in the GdR SoC-SiP/SoC2 (Deputy Director, Responsible of the “Safety of Material Systems” working group, Members of the Steering Committee), in the pre-GdR Security (Member) and in the ERRATA GdR (Member).
Members
Staff
- Florence Azaïs, Research Fellow CNRS
- Mariane Comte, Assistant Professor UM
- Luigi Dilillo, Research Fellow CNRS
- Sophie Dupuis, Assistant Professor UM
- Marie-Lise Flottes, Research Fellow CNRS
- Patrick Girard, Research Director CNRS
- Serge Pravossoudovitch, Professor UM
- Bruno Rouzeyre, Professor UM
- Arnaud Virazel, Assistant Professor UM
Associates & Students
- Douglas Almeida Dos Santos, PhD student UM
- Amine Ayaou, PhD student UM
- Pierre D'Hondt, PhD student STMicroelectronics SAS
- Bastien Deveautour, PhD student UM
- Sebastien Lapeyre, PhD student INVIA THALES DIS DESIGN SERVICES SAS
- Julia Lefèvre, PhD student STMicroelectronics SAS
- Lucas Matana Luza, PhD student UM
- Quang Linh Nguyen, PhD student UM
- Béatrice Pradarelli, Research associate UM
Regular Co-workers
- Eduardo Bezerra, Universidade Federal de Santa Catarina (UFSC)
Publications 2014 - 2019: Evaluation period
International Journals
2020
- A Survey of Test and Reliability Solutions for Magnetic Random Access MemoriesPatrick Girard, Yuanqing Cheng, Arnaud Virazel, Weisheng Zhao, Rajendra Bishnoi, Mehdi TahooriProceedings of the IEEE, Institute of Electrical and Electronics Engineers, In press, pp.1-21.
- Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low Power and Low-Orbit Aerospace ApplicationsAibin Yan, Yan Chen, Zhelong Xu, Zhili Chen, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing WenIEEE Transactions on Aerospace and Electronic Systems, Institute of Electrical and Electronics Engineers, 2020, 56 (5), pp.3931-3940.
- Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation EnvironmentsAibin Yan, Zhelong Xu, Xiangfeng Feng, Jie Cui, Zhili Chen, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing WenIEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, In press. <10.1109/TETC.2020.3025584>
- Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node UpsetsAibin Yan, Yang Cheng, Yuanjie Hu, Jun Zhou, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing WenIEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, In press. <10.1109/TCSI.2020.3018328>
- Cell-Aware Defect Diagnosis of Customer Returns Based on Supervised LearningSafa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Eric Faehn, Aymen LadharIEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2020, 20 (2), pp.329-340.
- Information Assurance through Redundant Design: A Novel TNU Error Resilient Latch for Harsh Radiation EnvironmentAibin Yan, Yuanjie Hu, Jie Cui, Zhili Chen, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing WenIEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2020, 69 (6), pp.789-799.
- A Survey of Testing Techniques for Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto BosioProceedings of the IEEE, Institute of Electrical and Electronics Engineers, In press. <10.1109/JPROC.2020.2999613>
- Investigations on the Use of Ensemble Methods for Specification-Oriented Indirect Test of RF CircuitsHassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, François LefèvreJournal of Electronic Testing, Springer Verlag, 2020, 36 (2), pp.189-203.
- Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells based Multiple-Node-Upset-Tolerant Latch DesignsAibin Yan, Yafei Ling, Jie Cui, Zhili Chen, Zhengfeng Huang, Jie Song, Patrick Girard, Xiaoqing WenIEEE Transactions on Circuits and Systems Part 1 Fundamental Theory and Applications, Institute of Electrical and Electronics Engineers (IEEE), 2020, 67 (3), pp.879-890.
- On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic CircuitsBastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin GhermanJournal of Electronic Testing, Springer Verlag, 2020, 36, pp.33-46.
2019
- Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers DesignDouglas Melo, Cesar Zeferino, Luigi Dilillo, Eduardo Augusto BezerraSensors, MDPI, 2019, 19 (24), pp.5416-5439.
- Probabilistic estimation of the application-level impact of precision scaling in approximate computing applicationsMarcello Traiola, Alessandro Savino, Stefano Di CarloMicroelectronics Reliability, Elsevier, 2019, 102, pp.#113309.
- Study of the impact of the LHC radiation environments on the Synergistic Displacement Damage and Ionizing Dose Effect on Electronic ComponentsRudy Ferraro, Salvatore Danzeca, Chiara Cangialosi, Rubén García Alía, Francesco Cerutti, Andrea Tsinganis, Luigi Dilillo, Markus Brugger, Alessandro MasiIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2019, 66 (7), pp.1548-1556.
- SEE flux and spectral hardness calibration of neutron spallation and mixed field facilitiesMatteo Cecchetto, Pablo Fernandez-Martinez, Rubén García Alía, Rudy Ferraro, Salvatore Danzeca, Frédéric Wrobel, Carlo Cazzaniga, Christopher FrostIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2019, 66 (7), pp.1532-1540.
- Pre-flight qualification test procedure for nanosatellites using sounding rocketsLeonardo Kessler Slongo, João Reis, Daniel Gaiki, Pedro von Hohendorff Seger, Sara Vega Martinez, Bruno Vale Barbosa Eiterer, Tulio Gomes Pereira, Mario Baldini Neto, Mateus dos Santos Frata, Juan Florez Mera, Kleber Paiva, Marcia Barbosa Henriques Mantelli, Luigi Dilillo, Eduardo Augusto BezerraActa Astronautica, Elsevier, 2019, 159, pp.564-577.
- Pre-flight qualification test procedure for nanosatellites using sounding rocketsLeonardo Kessler Slongo, João Gabriel Reis, Daniel Gaiki, Pedro von Hohendorff Seger, Sara Vega Martínez, Bruno Vale Barbosa Eiterer, Tulio Gomes Pereira, Mario Baldini Neto, Matheus dos Santos Frata, Henrique Daniel Hamisch, André Martins Pio De Mattos, Juan Pablo Florez Mera, Kleber Vieira De Paiva, Marcia Barbosa Henriques Mantelli, Luigi Dilillo, Eduardo Augusto BezerraActa Astronautica, Elsevier, 2019, 159, pp.564-577.
- A Survey on Security Threats and Countermeasures in IEEE Test StandardsEmanuele Valea, Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreIEEE Design & Test, IEEE, 2019, 36 (3), pp.95-116.
- Logic Locking: A Survey of Proposed Methods and Evaluation MetricsSophie Dupuis, Marie-Lise FlottesJournal of Electronic Testing, Springer Verlag, 2019, 35 (3), pp.273-291.
- Improvement of the Tolerated Raw Bit Error Rate in NAND Flash-based SSDs with Selective RefreshEmna Farjallah, Jean-Marc Armani, Valentin Gherman, Luigi DililloMicroelectronics Reliability, Elsevier, 2019, 96, pp.37-45.
- SyRA: Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Memory Arrays of Microprocessor SystemsAlessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera Villanueva, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Dimitris Gizopoulos, Stefano Di CarloIEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2019, 68 (5), pp.765-783.
- Stream vs Block ciphers for scan encryptionEmanuele Valea, Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreMicroelectronics Journal, Elsevier, 2019, 86, pp.65-76.
- Preventing Scan Attacks on Secure Circuits Through Scan Chain EncryptionMathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2019, 38 (3), pp.538-550.
- Low-Cost Digital Test Solution for Symbol Error Detection of RF ZigBee TransmittersThibault Vayssade, Florence Azaïs, Laurent Latorre, Francois LefèvreIEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2019, 19 (1), pp.16-24.
- Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI TechnologiesAmit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel RenovellJournal of Electronic Testing, Springer Verlag, 2019, 35 (1), pp.59-75.
- Actions de vulgarisation du guichet national de formation continue du GIP-CNFMBéatrice Pradarelli, Pascal Nouet, Pascal Benoit, Olivier BonnaudJournal sur l'enseignement des sciences et technologies de l'information et des systèmes, EDP Sciences, 2019, 18, pp.1022.
- Novel Quadruple Cross-Coupled Memory Cell Designs Protected against Single Event Upsets and Double-Node UpsetsAibin Yan, Yuanjie Hu, Jun Zhou, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing WenIEEE Access, IEEE, 2019, 7, pp.176188-176196.
- A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Space ApplicationsAibin Yan, Kang Yang, Jie Cui, Patrick Girard, Xiaoqing WenIEEE Transactions on Aerospace and Electronic Systems, Institute of Electrical and Electronics Engineers, In press.
- Sensitivity to Laser Fault Injection: CMOS FD-SOI vs. CMOS bulkJ.-M. Dutertre, Vincent Beroulle, Philippe Candelier, Stephan de Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hely, R. Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno RouzeyreIEEE Transactions on Device and Materials Reliability, Institute of Electrical and Electronics Engineers, 2019, 19 (1), pp.6-15.
- A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection ProcedureMarcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto BosioIEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2019, 18, pp.849-857.
2018
- An efficient EDAC approach for handling multiple bit upsets in memory arrayRoger Goerl, Paulo R.C. Villa, Letícia Poehls, Eduardo Augusto Bezerra, Fabian Luis VargasMicroelectronics Reliability, Elsevier, 2018, 88-90, pp.214-218.
- Assessing Body Built-In Current Sensors for Detection of Multiple Transient FaultsRaphael Andreoni Camponogara-Viera, Jean-Max Dutertre, Marie-Lise Flottes, Olivier Potin, Giorgio Di Natale, Bruno Rouzeyre, Rodrigo Possamai BastosMicroelectronics Reliability, Elsevier, 2018, 88-90 (29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2018)), pp.128-134.
- Single-Event Effects in the Peripheral Circuitry of a Commercial Ferroelectric Random Access MemoryAlexandre Louis Bosser, Viyas Gupta, Arto Javanainen, Georgios Tsiligiannis, Stephen Lalumondiere, Dale Brewe, Véronique Ferlet-Cavrois, Helmut Puchner, Heikki Kettunen, Thierry Gil, Frédéric Wrobel, F. Saigné, Ari Virtanen, Luigi DililloIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2018, 65 (8), pp.1708-1714.
- On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation ConstraintsStéphane David-Grignot, Achraf Lamlih, Mohamed Moez Belhaj, Vincent Kerzérho, Florence Azaïs, Fabien Soulier, Philippe Freitas, Tristan Rouyer, Sylvain Bonhommeau, Serge BernardJournal of Electronic Testing, Springer Verlag, 2018, 34 (3), pp.281-290.
- Agent-Based Simulation of Learning Dissemination in a Project-Based Learning Context Considering the Human AspectsLaio Oriel Seman, Romeu Hausmann, Eduardo Augusto BezerraIEEE Transactions on Education, Institute of Electrical and Electronics Engineers, 2018, 61 (2), pp.101-108.
- Detectability Challenges of Bridge Defects in FinFET Based Logic CellsFreddy Forero, Jean-Marc Galliere, Michel Renovell, Victor ChampacJournal of Electronic Testing, Springer Verlag, 2018, 34 (2), pp.123-134.
- A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAsVictor Manuel Gonçalves Martins, Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Marcelo Daniel Berejuck, Eduardo Augusto BezerraMicroelectronics Reliability, Elsevier, 2018, 83, pp.50-63.
- Guest Editorial: <italic>IEEE Transactions on Emerging Topics in Computing</italic> Special Issue on Design & Technology of Integrated Systems in Deep Submicron EraGiorgio Di Natale, Marco OttaviSubmicron Era. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2018, 6 (2), pp.170-171.
- A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working ConditionsMario Barbareschi, Giorgio Di Natale, Lionel Torres, Antonino MazzeoIEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2018, 65 (2), pp.700-711.
- Scan-Chain Intra-Cell Aware TestingAymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Matteo Sonza Reorda, Paolo Bernardi, Etienne AuvrayIEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2018, 6 (2), pp.278-287.
- Towards a Dependable True Random Number Generator With Self-Repair CapabilitiesHonorio Martin, Giorgio Di Natale, Luis EntrenaIEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2018, 65 (1), pp.247-256.
- Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges AheadSophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreIEEE Design & Test, IEEE, 2018, 35 (2), pp.73-90.
- Test and Reliability in Approximate ComputingLorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana VatajeluJournal of Electronic Testing, Springer Verlag, 2018, 34 (4), pp.375-387.
- Estimating dynamic power consumption for memristor-based CiM architectureMarcello Traiola, Mario Barbareschi, Alberto BosioMicroelectronics Reliability, Elsevier, 2018, 80, pp.241-248.
2017
- A calculation method to estimate single event upset cross sectionFrédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Jérôme Boch, Frédéric SaignéMicroelectronics Reliability, Elsevier, 2017, 76-77, pp.644-649.
- HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power CharacterizationArnaud Virazel, Alejandro Nocua, Alberto Bosio, Patrick Girard, Cyril ChevalierJournal of Circuits, Systems, and Computers, World Scientific Publishing, 2017, 26 (8), pp.#1740004.
- Microprocessor Testing: Functional Meets Structural TestAymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza ReordaJournal of Circuits, Systems, and Computers, World Scientific Publishing, 2017, 26 (08). <10.1142/S0218126617400072>
- Heavy Ion Induced Degradation in SiC Schottky Diodes: Incident Angle and Energy Deposition DependenceArto Javanainen, Marek Turowski, Kenneth Galloway, Christopher Nicklaw, Véronique Ferlet-Cavrois, Alexandre Louis Bosser, Jean-Marie Lauenstein, Michele Muschitiello, Francesco Pintacuda, Robert Reed, Ronald Schrimpf, Robert Weller, Ari VirtanenIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2017, 64 (8), pp.2031-2037.
- Report on DATE 2017 in LausanneDavid Atienza, Giorgio Di NataleIEEE Design & Test, IEEE, 2017, 34 (4), pp.76-77.
- Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET TechnologiesAmit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel RenovellJournal of Electronic Testing, Springer Verlag, 2017, 33 (4), pp.515-527.
- Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI TechnologyAmit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel RenovellIEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2017, 16 (3), pp.417-430.
- Computing reliability: On the differences between software testing and software fault injection techniquesMaha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, Lionel TorresMicroprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2017, 50, pp.102-112.
- Design of a radiation tolerant system for total ionizing dose monitoring using floating gate and RadFET dosimetersRudy Ferraro, Salvatore Danzeca, Matteo Brucoli, Alessandro Masi, Markus Brugger, Luigi DililloJournal of Instrumentation, IOP Publishing, 2017, 12 (4), pp.#C04007.
- A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic CircuitsArnaud Virazel, Imran Wali, Bastien Deveautour, Alberto Bosio, Patrick Girard, Matteo Sonza ReordaJournal of Electronic Testing, Springer Verlag, 2017, 33 (1), pp.25-36.
- A Cross-Level Power Estimation Technique to Improve IP Power Models QualityAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril ChevalierJournal of Low Power Electronics, American Scientific Publishers, 2017, 13 (1), pp.10-28.
2016
- Soft errors in commercial off-the-shelf static random access memoriesLuigi Dilillo, Georgios Tsiligiannis, Viyas Gupta, Alexandre Louis Bosser, Frédéric Saigné, Frédéric WrobelSemiconductor Science and Technology, IOP Publishing, 2016, Special Issue on Radiation Effects in Semiconductor Devices, 32 (1). <10.1088/1361-6641/32/1/013006>
- Frontside Versus Backside Laser Injection: A Comparative StudyStephan de Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise FlottesACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, Special Issue on Secure and Trustworthy Computing, 13 (1), pp.7.
- An Effective Power-Aware At-Speed Test Methodology for IP Qualification and CharacterizationKapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick GirardJournal of Electronic Testing, Springer Verlag, 2016, 32 (6), pp.721-733.
- Ring oscillators analysis for security purposes in Spartan-6 FPGAsMario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel TorresMicroprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (Part A), pp.3-10.
- The Power Law Shape of Heavy Ions Experimental Cross SectionFrédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Eric Lorfèvre, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 64 (1), pp.427-433.
- Methodologies for the Statistical Analysis of Memory Response to RadiationAlexandre Louis Bosser, Viyas Gupta, Georgios Tsiligiannis, Christopher Frost, Ali Mohammad Zadeh, Jukka Jaatinen, Arto Javanainen, Helmut Puchner, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi DililloIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2122-2128.
- Proton-Induced Single-Event Degradation in SDRAMsAxel Rodriguez, Frédéric Wrobel, Anne Samaras, Francoise Bezerra, Benjamin Vandevelde, Robert Ecoffet, Antoine Touboul, Christian Chatry, Luigi Dilillo, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2115-2121.
- Heavy-Ion Radiation Impact on a 4 Mb FRAM Under Different Test Modes and ConditionsViyas Gupta, Alexandre Louis Bosser, Georgios Tsiligiannis, Ali Mohammad Zadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi DililloIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2010-2015.
- A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing CoresImran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza ReordaJournal of Electronic Testing, Springer Verlag, 2016, 32 (2), pp.147-161.
- SSB Phase Noise Evaluation of Analog/IF Signals on Standard Digital ATEFlorence Azaïs, Stéphane David-Grignot, Laurent Latorre, François LefevreJournal of Electronic Testing, Springer Verlag, 2016, 32 (1), pp.69-82.
- Design for Test and Diagnosis of Power SwitchesMiroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane GuilhotJournal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.1640013.
- Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE)Lilian Bossuet, Giorgio Di Natale, Paris KitsosMicroprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (A), pp.1-2.
- Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated CircuitsFlorence Azaïs, Stéphane David-Grignot, Laurent Latorre, François LefevreJournal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.#1640014.
- STT-MRAM-Based PUF Architecture exploiting Magnetic Tunnel Junction Fabrication-Induced VariabilityElena Ioana Vatajelu, Giorgio Di Natale, Mario Barbareschi, Lionel Torres, Marco Indaco, Paolo PrinettoACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, 13 (1). <10.1145/2790302>
2015
- SEE on Different Layers of Stacked-SRAMsViyas Gupta, Alexandre Louis Bosser, Georgios Tsiligiannis, Mathias Rousselet, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi DililloIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2015, 62 (6), pp.2673-2678.
- Investigation on MCU Clustering Methodologies for Cross-Section Estimation of RAMsAlexandre Louis Bosser, Viyas Gupta, Georgios Tsiligiannis, Arto Javanainen, Heikki Kettunen, Helmut Puchner, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi DililloIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2015, 62 (6), pp.2620-2626.
- Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategiesSyhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel RenovellMicroelectronics Journal, Elsevier, 2015, 46 (11), pp.1091-1102.
- Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overviewAlessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Alessandro Savino, Politano Gianfranco, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di CarloMicroprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2015, 39 (8), pp.1204-1214.
- Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement RangeStéphane David-Grignot, Florence Azaïs, Laurent Latorre, François LefevreJournal of Electronic Testing, Springer Verlag, 2015, 31 (5-6), pp.443-459.
2014
- Heavy Ion SEU Cross Section Calculation Based on Proton Experimental Data, and Vice VersaFrédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Robert Ecoffet, Eric Lorfèvre, Francoise Bezerra, Markus Brugger, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3564-3571.
- Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude vs. Underground Experiments, Modeling and Numerical Monte Carlo SimulationGeorgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Philippe Cocquerez, Jean-Luc Autran, Antonio Litterio, Frédéric Wrobel, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3380-3388.
- Dynamic Compact Model of Self-Referenced Magnetic Tunnel JunctionJoão Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Jérémy Alvarez-Hérault, Ken MackayIEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2014, 61 (11), pp.3877-3882.
- Dynamic Test Methods for COTS SRAMsGeorgios Tsiligiannis, Luigi Dilillo, Viyas Gupta, Alberto Bosio, Patrick Girard, Arnaud Virazel, Helmut Puchner, Alexandre Louis Bosser, Arto Javanainen, Ari Virtanen, Christopher Frost, Frédéric Wrobel, Laurent Dusseau, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3095-3102.
- Testing Methods for PUF-Based Secure Key Storage CircuitsMafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di NataleJournal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.581-594.
- Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOSJean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Alexandre SarafianosMicroelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2289-2294.
- On the Test and Mitigation of Malfunctions in Low-Power SRAMsLeonardo B. Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil BadereddineJournal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.611-627.
- Testing for Gate Oxide Short Defects using the Detectability Interval ParadigmJean-Marc Galliere, Florence Azaïs, Mariane Comte, Michel RenovellInformation Technology, Oldenbourg Verlag, 2014, 56 (4), pp.173-181.
- Gate Voltage Contribution to Neutron-Induced SEB of Trench Gate Fieldstop IGBTLionel Foro, Antoine Touboul, Alain Michez, Frédéric Wrobel, Paolo Rech, Luigi Dilillo, Christopher Frost, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1739-1746.
- Evaluating a Radiation Monitor for Mixed-Field Environments based on SRAM TechnologyGeorgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Frédéric Wrobel, Frédéric SaignéJournal of Instrumentation, IOP Publishing, 2014, 9 (5), pp.#C05052.
- Multiple Cell Upset Classification in Commercial SRAMsGeorgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Helmut Puchner, Christopher Frost, Frédéric Wrobel, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1747-1754.
- TRUDEVICE: A COST Action on "Trustworthy Manufacturing and Utilization of Secure Devices" (Editorial)Giorgio Di NataleInformation Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.205-207.
- Multi-Level Ionizing-Induced Transient Fault SimulatorFeng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreInformation Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.251-264.
- On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel AnalysisSophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreInformation Security Journal: A Global Perspective, Taylor & Francis, 2014, Trustworthy Manufacturing and Utilization of Secure Devices, 22 (5-6), pp.226-236.
- Thwarting Scan-Based Attacks on Secure-ICs with On-Chip ComparisonJean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreIEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (4), pp.947-951.
- Determining Realistic Parameters for the Double Exponential Law that Models Transient Current PulsesFrédéric Wrobel, Luigi Dilillo, Antoine Touboul, Vincent Pouget, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1813-1818.
- Enhancing Confidence in Indirect Analog/RF Testing against the Lack of Correlation between Regular Parameters and Indirect MeasurementsHaithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel RenovellMicroelectronics Journal, Elsevier, 2014, 45 (3), pp.336-344.
- An SRAM Based Monitor for Mixed-Field Radiation EnvironmentsGeorgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Frédéric Wrobel, Frédéric SaignéIEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1663-1670.
- Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective AccelerometersAhmed Rekik, Florence Azaïs, Frédérick Mailly, Pascal NouetJournal of Electronic Testing, Springer Verlag, 2014, 30 (1), pp.87-100.
- Globally Constrained Locally Optimized 3-D Power Delivery NetworksAida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud VirazelIEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (10), pp.2131-2144.
- A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMsJoão Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Hérault, Ken MackayIEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (11), pp.2326-2335.
- A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and SystemsAhn Duc Tran, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Hans-Joachim WunderlichJournal of Electronic Testing, Springer Verlag, 2014, 30 (4), pp.401-413.
- Intra-Cell Defects DiagnosisZhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne AuvrayJournal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.541-555.
- Test versus Security: Past and PresentJean da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid VerbauwhedeIEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2014, 2 (1), pp.50-62.
International Communications
2020
- Electron-Induced Upsets and Stuck Bits in SDRAMs in the Jovian EnvironmentDaniel Soderstrom, Lucas Matana Luza, Heikki Kettunen, Arto Javanainen, Wilfrid Farabolini, Antonino Gilardi, Andrea Coronetti, Christian Poivey, Luigi DililloIEEE Nuclear and Space Radiation Effects Conference (NSREC), Nov 2020, Santa Fe (virtual), United States. <http://www.nsrec.com/>
- A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node UpsetsAibin Yan, Yan Chen, Jun Zhou, Tianming Ni, Xiaoqing Wen, Patrick GirardIEEE 28th Asian Test Symposium (ATS), Nov 2020, Penang, Malaysia.
- A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer ReturnsSafa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen LadharIEEE International Test Conference (ITC), Nov 2020, Washington DC, United States. <http://www.itctestweek.org/>
- Evaluating Data Encryption Effects on the Resilience of an Artificial Neural NetworkRiccardo Cantoro, Nikolaos Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele ValeaInternational Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2020, Frascati (on line), Italy. pp.1-4.
- Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing SystemsLucas Matana Luza, Daniel Soderstrom, Georgios Tsiligiannis, Helmut Puchner, Carlo Cazzaniga, Ernesto Sanchez, Alberto Bosio, Luigi DililloIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2020, Frascati, Italy. pp.1-6.
- EVM measurement of RF ZigBee transceivers using standard digital ATEThibault Vayssade, Florence Azaïs, Laurent Latorre, François LefèvreIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2020, Frascati, Italy. pp.1-6.
- Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical ApplicationsAibin Yan, Zhelong Xu, Jie Cui, Zuobin Ying, Zhengfeng Huang, Huaguo Liang, Patrick Girard, Xiaoqing WenIEEE International Symposium on Circuits and Systems (ISCAS), Oct 2020, Sevilla (virtual), Spain. pp.1-5.
- Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft ErrorsZhengda Dou, Aibin Yan, Jun Zhou, Yuanjie Hu, Yan Chen, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing WenIEEE International Test Conference in Asia (ITC-Asia), Sep 2020, Taipei, Taiwan. pp.35-40.
- On-board Compressing of Hyperspectral Images using CCSDS 123Douglas Almeida dos Santos, Cesar Albenes Zeferino, Eduardo Augusto Bezerra, Luigi Dilillo, Douglas Rossi MeloComputer on the Beach, Sep 2020, Balneário Camboriú, Brazil. pp.332-336.
- HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical ApplicationsAibin Yan, Xiangfeng Feng, Xiaohui Zhao, Hang Zhou, Jie Cui, Zuobin Ying, Patrick Girard, Xiaoqing Wen57th ACM/IEEE Design Automation Conference (DAC), Jul 2020, San Francisco, CA, United States. pp.1-6.
- Impact of Aging on Soft Error Susceptibility in CMOS CircuitsAmbika Shah, Patrick GirardIEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul 2020, Napoli, Italy. pp.1-4.
- A Secure Scan Controller for Protecting Logic LockingQuang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul 2020, Napoli, Italy. pp.1-6.
- An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAMPanagiota Papavramidou, Michael Nicolaidis, Patrick GirardIEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul 2020, Napoli, Italy. pp.1-6.
- Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICsFlorence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzérho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, Thibault Vayssade, Arnaud Virazel26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul 2020, Napoli, Italy. pp.1-4.
- A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace ApplicationsPablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen AzizaIEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul 2020, Napoli, Italy. pp.1-6.
- Indirect test of RF circuits using ensemble methodsHassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, François LefèvreEuropean Test Symposium (ETS), May 2020, Tallinn, Estonia. <https://ets2020.ttu.ee/index.php?page=70>
- Learning-Based Cell-Aware Defect Diagnosis of Customer ReturnsSafa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen LadharIEEE European Test Symposium (ETS), May 2020, Tallinn, Estonia. pp.1-2.
- Low-cost testing of a 2.4GHz ZigBee transmitter using standard digital ATEThibault Vayssade, Florence Azaïs, Laurent Latorre, François LefèvreEuropean Test Symposium (ETS), May 2020, Tallinn, Estonia. <https://ets2020.ttu.ee/index.php?page=70>
- Design, Verification, Test and In-Field Implications of Approximate Computing SystemsAlberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sanchez, Alessandro Savino, Lukas Sekanina, Marcello Traiola, Zdeněk Vašíček, Arnaud VirazelIEEE European Test Symposium (ETS), May 2020, Tallinn, Estonia. pp.1-10.
- QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead ReductionBastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick GirardIEEE European Test Symposium (ETS), May 2020, Tallinn, Estonia. pp.1-6.
- A Low-Cost Fault-Tolerant RISC-V Processor for Space SystemsDouglas Almeida dos Santos, Lucas Matana Luza, Cesar Albenes Zeferino, Luigi Dilillo, Douglas Rossi Melo15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Apr 2020, Marrakech, Morocco. pp.1-5.
- Effects of Thermal Neutron Irradiation on a Self-Refresh DRAMLucas Matana Luza, Daniel Soderstrom, Helmut Puchner, Ruben Garcia Alia, Manon Letiche, Alberto Bosio, Luigi Dilillo15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Apr 2020, Marrakech, Morocco. pp.1-6.
- Evaluating the Code Encryption Effects on Memory Fault ResilienceRiccardo Cantoro, Nikolaos Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele ValeaLatin American Test Symposium (LATS), Mar 2020, Maceio, Brazil. pp.1-6.
- Implementing indirect test of RF circuits without compromising test quality: a practical case studyHassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, François Lefèvre, Ingrid GorenflotIEEE Latin American Test Symposium (LATS), Mar 2020, Maceio, Brazil. pp.1-6.
- Maximizing Yield for Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto BosioDesign, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.810-815.
2019
- Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial ApplicationsAibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, Xiaoqing Wen, Patrick GirardIEEE 28th Asian Test Symposium (ATS), Dec 2019, Kolkata, India. pp.55-60.
- Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial ApplicationsAibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard, Xiaoqing WenIEEE 28th Asian Test Symposium (ATS), Dec 2019, Kolkata, India. pp.43-435.
- Teaching Hardware Security: Earnings of an Introduction proposed as an Escape GameFlorent Bruguier, Emmanuelle Lecointre, Béatrice Pradarelli, Loïc Dalmasso, Pascal Benoit, Lionel TorresInternational Conference on Interactive Collaborative and Blended Learning (ICBL), Nov 2019, Santiago de Cuba, Cuba. <https://onlinelab.space/conference/icbl2019/>
- Cell-Aware Diagnosis of Automotive Customer Returns Based on Supervised LearningSafa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar4th Automotive Reliability and Test Workshop (ART), Nov 2019, Washington, United States. <http://cas.polito.it/ART2019/>
- Effects of Heavy Ion and Proton Irradiation on a SLC NAND Flash MemoryLucas Matana Luza, Alexandre Bosser, Viyas Gupta, Arto Javanainen, Ali Mohammadzadeh, Luigi Dilillo32th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2019, Noordwijk, Netherlands. pp.1-6.
- Characterization of a RISC-V Microcontroller Through Fault InjectionDario Asciolla, Luigi Dilillo, Douglas Almeida dos Santos, Douglas Melo, Alessandra Menicucci, Marco OttaviInternational Conference on Applications in Electronics Pervading Industry, Environment and Society (APPLEPIES), Sep 2019, Pisa, Italy. pp.91-101.
- Which metrics to use for RF indirect test strategy?Hassan El Badawi, Mariane Comte, Florence Azaïs, Vincent Kerzérho, Serge Bernard, François LefevreSMACD: Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Jul 2019, Lausanne, Switzerland. pp.73-76.
- Towards Improvement of Mission Mode Failure Diagnosis for System-on-ChipSafa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Aymen Ladhar, Eric Faehn25th International Symposium on On-Line Testing And Robust System Design (IOLTS), Jul 2019, Rhodes, Greece. pp.21-26.
- A Comprehensive Approach to a Trusted Test InfrastructureMarc Merandat, Vincent Reynaud, Emanuele Valea, Jerome Quevremont, Nicolas Valette, Paolo Maistri, R. Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di NataleIVSW: International Verification and Security Workshop, Jul 2019, Rhodes, Greece. <http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw19>
- A Capacitor-Less CMOS Neuron Circuit for Neuromemristive NetworksHassen Aziza, Mathieu Moreau, Jean-Michel Portal, Arnaud Virazel, Patrick Girard17th International Conference on Electronics Circuits and Systems (NEWCAS), Jun 2019, Munich, Germany. <10.1109/NEWCAS44328.2019.8961278>
- Design and Implementation of a Flexible Interface for TID DetectorIacopo Fara, Lucas Matana Luza, Jérôme Boch, Gianluca Furano, Marco Ottavi, Luigi Dilillo8th International Workshop on Advances in Sensors and Interfaces (IWASI), Jun 2019, Otranto, Italy. pp.158-162.
- Stream Cipher Based Encryption in IEEE Test StandardsEmanuele Valea, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE), May 2019, Baden Baden, Germany.
- Power Measurement and Spectral Test of ZigBee Transmitters from 1-bit Under-sampled AcquisitionThibault Vayssade, Florence Azaïs, Laurent Latorre, François LefevreETS: European Test Symposium, May 2019, Baden-Baden, Germany. <10.1109/ETS.2019.8791540>
- Encryption-Based Secure JTAGEmanuele Valea, Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreDDECS: Design and Diagnostics of Electronic Circuits Systems, Apr 2019, Cluj-Napoca, Romania. <10.1109/DDECS.2019.8724654>
- Providing Confidentiality and Integrity in Ultra Low Power IoT DevicesEmanuele Valea, Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Sophie Dupuis, Bruno RouzeyreDTIS: Design & Technology of Integrated Systems In Nanoscale Era, Apr 2019, Mykonos, Greece. <10.1109/DTIS.2019.8735090>
- Analyzing the Error Propagation in a Parameterizable Network-on-Chip RouterDouglas Rossi de Melo, Cesar Zeferino, Luigi Dilillo, Eduardo Augusto BezerraLATS: Latin-American Test Symposium, Mar 2019, Santiago, Chile. <10.1109/LATW.2019.8704580>
- A Fault-Tolerant Reconfigurable Platform for Communication Modules of SatellitesCézar Rigo, Lucas Matana Luza, Elder Dominghini Tramontin, Victor Martins, Sara Vega Martinez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Fabian Luis Vargas, Eduardo Augusto BezerraLATS: Latin-American Test Symposium, Mar 2019, Santiago, Chile. <10.1109/LATW.2019.8704551>
- Use of ensemble methods for indirect test of RF circuits: can it bring benefits?Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, François LefevreLATS: Latin American Test Symposium, Mar 2019, Santiago, Chile. pp.1-6.
- The Use of Ensemble Learning in Indirect Testing of Analog and RF Integrated CircuitsHassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, François LefevreSouth European Test Seminar (SETS), 2019, Pitztal, Austria.
- Test of 2.4 GHz ZigBee Transmitter using Standard Digital ATEThibault Vayssade, Florence Azaïs, Laurent Latorre, François LefevreSouth European Test Seminar (SETS), 2019, Pitztal, Austria.
2018
- Enabling deep-space CubeSat missions through state-of-the-art radiation-hardened technologiesLucas Matana Luza, Cézar Rigo, Elder Dominghini Tramontin, Victor Martins, Sara Vega Martinez, Leonardo Kessler Slongo, Laio Oriel Seman, Luigi Dilillo, Eduardo Augusto Bezerra3rd IAA Latin American CubeSat Workshop (IAA-LACW), Dec 2018, Ubatuba, Brazil. <http://innalogics.com/iaalacw.org/iaalacw/>
- Implementation of fault tolerance techniques for integrated network interfacesDouglas Rossi de Melo, Cesar Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra3rd IAA Latin American CubeSat Workshop (IAA-LACW), Dec 2018, Ubatuba, Brazil.
- An Effective Intra-Cell Diagnosis Flow for Industrial SRAMsTien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick GirardITC: International Test Conference, Oct 2018, Phoenix, United States. pp.1-8.
- Investigation of Mean-Error Metrics for Testing Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbarcschi, Alberto Bosio31st IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2018), Oct 2018, Chicago, United States. pp.1-6.
- Study of the Impact of the LHC Radiation Environments on the Synergistic Displacement Damage and Ionizing Dose Effect on Electronic ComponentsRudy Ferraro, Salvatore Danzeca, Luigi Dilillo, Chiara Cangialosi, Rubén García Alía, F. Cerutti, A. Tsinganis, A. Masi, Markus BruggerRADECS: Radiation Effects on Components and Systems, Sep 2018, Göteborg, Sweden. <http://www.radecs2018.org>
- SEE Flux and Spectral Hardness Calibration of Neutron Spallation and Mixed Field FacilitiesMatteo Cecchetto, Rubén García Alía, Pablo Fernandez-Martinez, Rudy Ferraro, Salvatore Danzeca, Frédéric Wrobel, Carlo Cazzaniga, Christopher FrostRADECS: Radiation Effects on Components and Systems, Sep 2018, Goteborg, Sweden. <http://www.radecs2018.org>
- Approximate TMR Based on Successive Approximation to Protect Against Multiple Bit Upset in MicroprocessorsGennaro Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio18th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2018), Sep 2018, Goteborg, Sweden. <10.1109/RADECS45761.2018.9328687>
- Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault modelJean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan de Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hely, R. Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno RouzeyreFDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.1-6.
- Exploiting Phase Information in Thermal Scans for Stealthy Trojan DetectionMaxime Cozzi, Jean-Marc Galliere, Philippe MaurineDSD: Digital System Design, Aug 2018, Prague, Slovakia. pp.573-576.
- 2018 Compendium of Radiation-Induced Effects for Candidate Particle Accelerator ElectronicsSalvatore Danzeca, Gilles Foucard, Georgios Tsiligiannis, Rudy Ferraro, G. Piscopo, C.G. Mcallister, Thomas Borel, Paul Peronnard, Markus Brugger, Alessandro Masi, Simone GilardoniIEEE Nuclear & Space Radiation Effects Conference (NSREC 2018), Jul 2018, Waikoloa Village, HI, United States. pp.1-6.
- Bistatic MIMO System with Uniform Circular Arc Arrays for Single near Field Target LocalizationJinze Du, Bin Wu, Yi Yang, Chao Yuan, Parth Raj Singh, Amit Karel, Lian Li10th International Conference on Communication Software and Networks (ICCSN 2018), Jul 2018, Chengdu, China. pp.357-360.
- Predicting the Impact of Functional Approximation: from Component- to Application-LevelMarcello Traiola, Alessandro Savino, Mario Barbareschi, Stefano Di Carlo, Alberto Bosio24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Jul 2018, Platja d'Aro, Spain. pp.61-64.
- Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applicationsGennaro Rodrigues, Fernanda Kastensmidt, Vincent Pouget, Alberto BosioIOLTS: International On-Line Testing Symposium, Jul 2018, Platja d'Aro, Spain. pp.291-294.
- Combined analysis of supply voltage and body-bias voltage for energy managementRida Kheirallah, Jean-Marc Galliere, Nadine Azemard, Gilles R. DucharmePATMOS: Power And Timing Modeling, Optimization and Simulation, Jul 2018, Platja d’Aro, Spain. pp.88-91.
- The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacksJean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hely, R. Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno RouzeyreIOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219.
- A new secure stream cipher for scan chain encryptionMathieu da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno RouzeyreIVSW: International Verification and Security Workshop, Jul 2018, Platja d’Aro, Spain. <http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw18/>
- Encryption of test data: which cipher is better?Mathieu da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno RouzeyrePRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. pp.85-88.
- Low-cost functional test of a 2.4 GHz OQPSK transmitter using standard digital ATEThibault Vayssade, Florence Azaïs, Laurent Latorre, Francois LefèvreIOLTS: International On-Line Testing Symposium, Jul 2018, Platja d'Aro, Spain. pp.17-22.
- A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide ObfuscationHonorio Martin, Luis Entrena, Sophie Dupuis, Giorgio Di NataleIOLTS: International Symposium on On-Line Testing And Robust System Design, Jul 2018, Platja d'Aro, Spain. pp.41-42.
- Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy TradeoffsGennaro Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Alberto Bosio14th International Symposium on Applied Reconfigurable Computing (ARC 2018), May 2018, Santorini, Greece. pp.647-658.
- Distributed Optical Fiber Radiation Sensing at CERNGaetano Li Vecchi, Markus Brugger, Salvatore Danzeca, Diego Di Francesca, Rudy Ferraro, Sylvain Girard, Yacine Kadi, Oliver Stein9th International Particle Accelerator Conference, Apr 2018, Vancouver, Canada. pp.WEPAF083.
- Synthesis of Finite State Machines on Memristor CrossbarsUmberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fišer, Alberto Bosio21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2018, Budapest, Hungary. pp.107-112.
- On the Comparison of Different ATPG approaches for Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr 2018, Budapest, Hungary. pp.85-90.
- Thermal Scans for Detecting Hardware TrojansMaxime Cozzi, Philippe Maurine, Jean-Marc GalliereCOSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2018, Singapour, Singapore. pp.117-132.
- Special session: How approximate computing impacts verification, test and reliabilityLukas Sekanina, Zdeněk Vašíček, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes dos Santos, Stefano Di Carlo36th VLSI Test Symposium (VTS), Apr 2018, San Francisco, CA, United States. <10.1109/VTS.2018.8368628>
- Best practices in e-assessments with a special focus on cheating preventionDirk von Grunigen, Fernando Benites de Azevedo E Souza, Beatrice Pradarelli, Amani Magid, Mark CieliebakIEEE Global Engineering Education Conference (EDUCON 2018), Apr 2018, Tenerife, Spain. pp.893-899.
- Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cellsEmna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi DililloDTIS: Design & Technology of Integrated Systems In Nanoscale Era, LIRMM, Apr 2018, Taormina, Italy. <10.1109/DTIS.2018.8368578>
- Is aproximate computing suitable for selective hardening of arithmetic circuits?Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Apr 2018, Taormina, Italy. pp.1-6.
- SI ECCS: SECure context saving for IoT devicesEmanuele Valea, Mathieu da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno RouzeyreDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. <10.1109/DTIS.2018.8368561>
- Does stream cipher-based scan chains encryption really prevent scan attacks?Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreTRUDEVICE Workshop, Mar 2018, Dresden, Germany. <https://www.date-conference.com/date18/conference/workshop-w05>
- Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injectionGennaro Rodrigues, Fernanda Kastensmidt, Vincent Pouget, Alberto BosioLATS: Latin-American Test Symposium, Mar 2018, Sao Paulo, Brazil. <10.1109/LATW.2018.8349675>
- Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologiesAmit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel RenovellLATS: Latin-American Test Symposium, Mar 2018, Sao Paulo, Brazil. <10.1109/LATW.2018.8349696>
- Testing Approximate Digital Circuits: Challenges and OpportunitiesMarcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto BosioIEEE 19th Latin-American Test Symposium (LATS), Mar 2018, Sao Paulo, Brazil. pp.1-6.
2017
- An Advanced Diagnosis Flow for SRAMsArnaud Virazel, Tien-Phu Ho, Alberto BosioISTFA: International Symposium for Testing and Failure Analysis, Nov 2017, Pasadena, United States. <https://www.asminternational.org/web/istfa-2017>
- Improvement of the tolerated raw bit-error rate in NAND Flash-based SSDs with the help of embedded statisticsValentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi DililloITC: International Test Conference, Oct 2017, Fort Worth, United States. <10.1109/TEST.2017.8242066>
- Single-Event Effects in the Peripheral Circuitry of a Commercial Ferroelectric Random- Access MemoryAlexandre Louis Bosser, Viyas Gupta, Arto Javanainen, Georgios Tsiligiannis, Stephen Lalumondiere, Dale Brewe, Véronique Ferlet-Cavrois, Helmut Puchner, Heikki Kettunen, Thierry Gil, Frédéric Wrobel, Frédéric Saigné, Ari Virtanen, Luigi DililloRADECS: Radiation and Its Effects on Components and Systems, Oct 2017, Genève, Switzerland. <http://radecs2017.com/Radecs2017/>
- Towards digital circuit approximation by exploiting fault simulationMarcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto BosioEWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. <10.1109/EWDTS.2017.8110108>
- A calculation method to estimate single event upset cross sectionFrédéric Wrobel, Antoine Touboul, V. Pouget, Luigi Dilillo, J. Boch, F. SaignéESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Sep 2017, Bordeaux, France. <https://esref2017.sciencesconf.org>
- Experimentations on scan chain encryption with PRESENTMathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.45-50.
- Hacking the Control Flow error detection mechanismGiorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno RouzeyreIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.51-56.
- Analytical Study of On-chip Generations of Analog Sine-wave Based on Combined Digital SignalsStéphane David-Grignot, Achraf Lamlih, Vincent Kerzérho, Florence Azaïs, Fabien Soulier, Serge BernardIMSTW: International Mixed Signals Testing Workshop, Jul 2017, Thessaloniki, Greece. <10.1109/IMS3TW.2017.7995205>
- Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI TechnologyAmit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, Keshav SinghISVLSI: International Symposium on Very Large Scale Integration, Jul 2017, Bochum, Germany. pp.320-325.
- Reliability of computing systems: From flip flops to variablesGiorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, R. LeveugleIOLTS: International On-Line Testing Symposium, Jul 2017, Thessaloniki, Greece. pp.196-198.
- Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memoriesElena Ioana Vatajelu, Giorgio Di Natale, Paolo PrinettoIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.128-133.
- Test and reliability in approximate computingLorena Anghel, Mounir Benabdenbi, Alberto Bosio, Elena Ioana VatajeluIMSTW: International Mixed-Signal Testing Workshop, Jul 2017, Thessaloniki, Greece. <10.1109/IMS3TW.2017.7995210>
- IDEFI-FINMINA: a French educative project for the awareness, innovation and multidisciplinarity in microelectronicsOlivier Bonnaud, Ahmad Bsiesy, Laurent Fesquet, Béatrice Pradarelli27th European Association for Education in Electrical and Information Engineering Annual Conference (EAEEIE 2017), Jun 2017, Grenoble, France. <10.1109/EAEEIE.2017.8768621>
- Refresh frequency reduction of data stored in SSDs based on A-timer and timestampsMarcelino Seif, Emna Farjallah, Franck Badets, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Valentin Gherman, Luigi DililloETS: European Test Symposium, May 2017, Limassol, Cyprus. pp.1-6.
- Scan chain encryption for the test, diagnosis and debug of secure circuitsMathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco RestifoETS: European Test Symposium, May 2017, Limassol, Cyprus. <10.1109/ETS.2017.7968248>
- Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditionsAmit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, Keshav SinghETS: European Test Symposium, May 2017, Limassol, Cyprus. <10.1109/ETS.2017.7968208>
- Mitigating Read & Write Errors in STT-MRAM Memories under DVSElena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan FiguerasETS: European Test Symposium, May 2017, Limassol, Cyprus. <10.1109/ETS.2017.7968209>
- Do we need a holistic approach for the design of secure IoT systems?Mauro Contini, Giorgio Di Natale, Annelie Heuser, Thomas Poppelmann, Nele MentensCF: Computing Frontiers, May 2017, Siena, Italy. pp.425-430.
- Combo of innovative educational approaches to teach industrial test to undergraduate studentsBéatrice Pradarelli, Pascal Nouet, Laurent LatorreEDUCON: Global Engineering Education Conference, Apr 2017, Athens, Greece. pp.56-64.
- How to throw chocolate at students: A survey of extrinsic means for increased audience attentionMark Cieliebak, Amani Magid, Béatrice PradarelliEDUCON: Global Engineering Education Conference, Apr 2017, Athens, Greece. pp.199-203.
- Formal Design Space Exploration for memristor-based crossbar architectureMarcello Traiola, Mario Barbareschi, Alberto Bosio20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2017, Dresden, Germany. pp.145-150.
- Towards approximation during test of Integrated CircuitsImran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto BosioDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. <10.1109/DDECS.2017.7934574>
- An effective fault-injection framework for memory reliability enhancement perspectivesGhita Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo BernardiDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. <10.1109/DTIS.2017.7930172>
- Memristive devices: Technology, Design Automation and Computing FrontiersMario Barbareschi, Alberto Bosio, Hoang Anh Du Nguyen, Said Hamdioui, Marcello Traiola, Elena Ioana VatajeluDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. <10.1109/DTIS.2017.7930178>
- Approximate computing: Design & test for integrated circuitsArnaud Virazel, Alberto Bosio, Patrick Girard, Mario BarbareschiLATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. <10.1109/LATW.2017.7906737>
- Analysis of short defects in FinFET based logic cellsFreddy Forero, Jean-Marc Galliere, Michel Renovell, Víctor ChampacLATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. <10.1109/LATW.2017.7906755>
- Can we Approximate the Test of Integrated Circuits?Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto BosioWAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden. <https://wapco.e-ce.uth.gr/program.html>
2016
- Test of Low Power Circuits: Issues and Industrial PracticesAlberto Bosio, Patrick Girard, Arnaud VirazelICECS: International Conference on Electronics, Circuits and Systems, Dec 2016, Monte Carlo, Monaco. <http://icecs.isep.fr>
- SCHIFI: Scalable and flexible high performance FPGA-based fault injectorSuman Sau, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Amlan ChakrabartiDCIS: Design of Circuits and Integrated Systems, Nov 2016, Granada, Spain. <10.1109/DCIS.2016.7845375>
- Cross-layer system reliability assessment framework for hardware faultsAlessandro Vallero, Alessandro Savino, Gianfranco Michele Maria Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Sotiris Tselonis, Marc Riera Villanueva, Ramon Canal, Antonio Gonzalez, Maha Kooli, Alberto Bosio, Giorgio Di NataleITC: International Test Conference, Nov 2016, Fort Worth, TX, United States. <10.1109/TEST.2016.7805863>
- Duplication-based Concurrent Detection of Hardware Trojans in Integrated CircuitsManikandan Palanichamy, Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreTRUDEVICE, Nov 2016, Barcelona, Spain. <https://trudevice2016.eel.upc.edu/>
- True random number generator based on nanomagnetsLuca Gnoli, Matteo Bollo, Marco Vacca, Mariagrazia Graziano, Giorgio Di NataleNMDC: Nanotechnology Materials and Devices Conference, Oct 2016, Toulouse, France. <10.1109/NMDC.2016.7777089>
- A Case Study on the Approximate Test of Integrated CircuitsImran Wali, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto BosioAC: Approximate Computing, Oct 2016, Pittsburgh, PA, United States. <http://approximate.uni-paderborn.de/pages/general-info/welcome.php>
- Design of a Radiation Tolerant System for Total Ionizing Dose Monitoring Using Floating Gate and RadFET DosimetersRudy Ferraro, Salvatore Danzeca, Matteo Brucoli, Alessandro Masi, Markus Brugger, Luigi DililloTWEPP: Topical Workshop on Electronics for Particle Physics, Sep 2016, Karlsruhe, Germany. <http://indico.cern.ch/event/489996/>
- A Hybrid Power Estimation Technique to improve IP power models qualityAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril ChevalierVLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallin, Estonia. <10.1109/VLSI-SoC.2016.7753582>
- XbarGen: A memristor based boolean logic synthesis toolMarcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto BosioIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Sep 2016, Tallinn, Estonia. <10.1109/VLSI-SoC.2016.7753567>
- Faster-than-at-speed execution of functional programs: An experimental analysisPaolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico VeniniVLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallinn, Estonia. <10.1109/VLSI-SoC.2016.7753581>
- Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional ProgramsPaolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sanchez, Federico VeniniVLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, Sep 2016, Tallinn, Estonia. pp.130-151.
- Mixed-level simulation tool for design optimization of electrical impedance spectroscopy systemsAchraf Lamlih, Vincent Kerzérho, Serge Bernard, Fabien Soulier, Mariane Comte, Michel Renovell, Tristan Rouyer, Sylvain BonhommeauIWIS: International Workshop on Impedance Spectroscopy, Sep 2016, Chemnitz, Germany. <https://www.tu-chemnitz.de/etit/messtech/iwis/openconf/modules/request.php?module=oc_program&action=program.php>
- Problem-Based Learning Approach to Teach Printed Circuit Boards TestBéatrice Pradarelli, Pascal Nouet, Laurent LatorreICL: Interactive Collaborative Learning, Sep 2016, Belfast, United Kingdom. pp.45-57.
- Comparison of the Effects of Muon and Low-Energy Proton Irradiation on a 65 nm Low-Power SRAMAlexandre Louis Bosser, Viyas Gupta, Arto Javanainen, Georgios Tsiligiannis, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Ari Virtanen, Luigi DililloRADECS: Radiation and Its Effects on Components and Systems, Sep 2016, Bremen, Germany. <http://www.radecs2016.com/joomla/>
- Investigation on the Sensitivity of a 65nm Flash-Based FPGA for CERN ApplicationsGeorgios Tsiligiannis, Rudy Ferraro, Salvatore Danzeca, Alessandro Masi, Markus Brugger, Frédéric SaignéRADECS: Radiation and Its Effects on Components and Systems, Sep 2016, Brême, Germany. <10.1109/RADECS.2016.8093209>
- The Power Law Shape of Heavy Ions Experimental Cross SectionFrédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Eric Lorfèvre, Frédéric SaignéNSREC: Nuclear and Space Radiation Effects Conference, IEEE NPSS (Nuclear & Plasma Sciences Society ), Jul 2016, Portland, United States. <http://www.nsrec.com/>
- Improving the Functional Test Delay Fault Coverage: A Microprocessor Case StudyAymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza ReordaISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, PA, United States. pp.731-736.
- Hardware Trust through Layout Filling: a Hardware Trojan Prevention TechniquePapa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259.
- Impact of VT and Body-Biasing on Resistive short detection in 28nm UTBB FDSOI – LVT and RVT configurationsAmit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel RenovellISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, PA, United States. pp.164-169.
- Towards Model Driven Design of Crypto Primitives and ProcessesAlberto Carelli, Giorgio Di Natale, Pascal Trotta, Tiziana MargariaSAM: Sensor Array and Multichannel Signal Processing, Jul 2016, Rio de Janeiro, Brazil. pp.152-158.
- Cache-aware reliability evaluation through LLVM-based analysis and fault injectionMaha Kooli, Giorgio Di Natale, Alberto BosioIOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.19-22.
- Using Outliers to Detect Stealthy Hardware Trojan Triggering?Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreIVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France.
- STT-MTJ-based TRNG with on-the-fly temperature/current variation compensationElena Ioana Vatajelu, Giorgio Di Natale, Paolo PrinettoIOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.179-184.
- Revisiting software-based soft error mitigation techniques via accurate error generation and propagation modelsMojtaba Ebrahimi, Maryam Rashvand, Firas Kaddachi, Mehdi B. Tahoori, Giorgio Di NataleIOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.66-71.
- MTCube project: COTS memory SEE ground-test results and in-orbit error rate predictionViyas Gupta, Alexandre Louis Bosser, Frédéric Wrobel, Frédéric Saigné, Laurent Dusseau, Ali Mohammadzadeh, Luigi Dilillo4S: Small Satellites Systems and Services Symposium, Centre national d'études spatiales (CNES); European Space Agency (ESA), May 2016, La Valletta, Malta. <http://congrexprojects.com/4S2016/home>
- Behavior and test of open-gate defects in FinFET based cellsFrancisco Mesalles, Hector Villacorta, Michel Renovell, Víctor ChampacETS: European Test Symposium, May 2016, Amsterdam, Netherlands. <10.1109/ETS.2016.7519305>
- A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic CircuitsImran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza ReordaETS: European Test Symposium, May 2016, Amsterdam, Netherlands. <10.1109/ETS.2016.7519296>
- Per Peers Learning Education Approach to Teach Industrial Test to Undergraduate StudentsBéatrice Pradarelli, Pascal Nouet, Laurent LatorreEWME: European Workshop on Microelectronics Education, May 2016, Southampton, United Kingdom. <10.1109/EWME.2016.7496485>
- Thermal issues in test: An overview of the significant aspects and industrial practiceJuergen Alt, Paolo Bernardi, Alberto Bosio, Ricardo Cantoro, Hans Kerkhoff, Andreas Leininger, Wolfgang Molzer, Allessandro Motta, Christian Pacha, Alberto Pagani, Alireza Rohani, Rudolf StrasserVTS: VLSI Test Symposium, Apr 2016, Las Vegas, NV, United States. <10.1109/VTS.2016.7477278>
- Security primitives (PUF and TRNG) with STT-MRAMElena Ioana Vatajelu, Giorgio Di Natale, Paolo PrinettoVTS: VLSI Test Symposium, Apr 2016, Las Vegas, United States. <10.1109/VTS.2016.7477292>
- Cache- and register-aware system reliability evaluation based on data lifetime analysisMaha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto BosioVTS: VLSI Test Symposium, Apr 2016, Las Vegas, United States. <10.1109/VTS.2016.7477299>
- An effective approach for functional test programs compactionAymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza ReordaDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. <10.1109/DDECS.2016.7482466>
- A hybrid power modeling approach to enhance high-level power modelsAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril ChevalierDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. <10.1109/DDECS.2016.7482453>
- System-level reliability evaluation through cache-aware software-based fault injectionFiras Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, Mehdi B. TahooriDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. <10.1109/DDECS.2016.7482446>
- Auto-adaptive ultra-low power ICAlberto Bosio, Philippe Debaud, Patrick Girard, Stéphane Guilhot, Miroslav Valka, Arnaud VirazelDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. <10.1109/DTIS.2016.7483886>
- SEcube™: An open-source security platform in a single SoCAntonio Varriale, Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Pascal Trotta, Tiziana MargariaDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. <10.1109/DTIS.2016.7483810>
- Industrial Test Project Oriented EducationBéatrice Pradarelli, Pascal Nouet, Laurent LatorreEDUCON: Global Engineering Education Conference, Apr 2016, Abu Dhabi, United Arab Emirates. pp.119-124.
- An effective BIST architecture for power-gating mechanisms in low-power SRAMsAlberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo B. ZordanISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.185-191.
- Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology NodesDeepak Kumar Arora, Darayus Adil Patel, Nc Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto BosioISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.295-300.
- Towards a Highly Reliable SRAM-based PUFsElena Ioana Vatajelu, Giorgio Di Natale, Paolo PrinettoDATE: Design, Automation and Test in Europe, Mar 2016, Dresden, Germany. pp.273-276.
- Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defectAmit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel RenovellLATS: Latin-American Test Symposium, Mar 2016, Foz do Iguacu, Brazil. pp.129-134.
2015
- An efficient hybrid power modeling approach for accurate gate-level power estimationAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril ChevalierICM: International Conference on Microelectronics, Dec 2015, Casablanca, Morocco. pp.17-20.
- Validation Of Single BBICS Architecture In Detecting Multiple FaultsRaphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreATS: Asian Test Symposium, Nov 2015, Mumbai, India. <https://www.ee.iitb.ac.in/ats15/>
- An Experimental Comparative Study of Fault-Tolerant ArchitecturesImran Wali, Arnaud Virazel, Alberto Bosio, Patrick GirardVALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. pp.1-6.
- Exploiting the Variability of the Magnetic Tunnel Junction for Security PurposesElena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinettoe-NVM: Leading Edge Embedded NVM, Sep 2015, Gardanne, France.
- Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technologyStephan de Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreTRUDEVICE Workshop, Sep 2015, Saint-Malo, France.
- Hierarchical Secure DfTMafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreTRUDEVICE Workshop, Sep 2015, St Malo, France.
- Multi-segment Enhanced Scan-chains for Secure ICsMafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ilia PolianTRUDEVICE Workshop, Sep 2015, Saint-Malo, France.
- Zero Bit-Error-Rate Weak PUF based on Spin-Transfer-Torque MRAM MemoriesElena Ioana Vatajelu, Giorgio Di Natale, Paolo PrinettoTRUDEVICE Workshop, Sep 2015, Saint-Malo, France.
- SEcubeTM: The most advanced, Open Source Security Platform in a Single ChipAntonio Varriale, Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Tiziana MargariaTRUDEVICE Workshop, Sep 2015, Saint-Malo, France.
- Proton-Induced SDRAM Cell DegradationAxel Rodriguez, Frédéric Wrobel, Anne Samaras, Francoise Bezerra, Benjamin Vandevelde, Robert Ecoffet, Antoine Touboul, Nathalie Chatry, Luigi Dilillo, Frédéric SaignéRADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. <10.1109/RADECS.2015.7365650>
- A Methodology for the Analysis of Memory Response to Radiation through Bitmap Superposition and SlicingAlexandre Louis Bosser, Viyas Gupta, Georgios Tsiligiannis, Rudy Ferraro, Christopher Frost, Ali Mohammadzadeh, Arto Javanainen, Helmut Puchner, Mario Rossi, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi DililloRADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. <10.1109/RADECS.2015.7365578>
- Heavy-ion radiation impact on a 4Mb FRAM under Different Test ConditionsViyas Gupta, Alexandre Louis Bosser, Georgios Tsiligiannis, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi DililloRADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. <10.1109/RADECS.2015.7365617>
- Hardware Trojan Prevention using Layout-Level Design ApproachPapa-Sidy Ba, Manikandan Palanichamy, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno RouzeyreECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. <10.1109/ECCTD.2015.7300093>
- Investigation on MCU Clustering Methodologies for Cross-Section Estimation of RAMsAlexandre Louis Bosser, Viyas Gupta, Georgios Tsiligiannis, Arto Javanainen, Heikki Kettunen, Helmut Puchner, F. Saigné, Ari Virtanen, Frédéric Wrobel, Luigi DililloNSREC: Nuclear and Space Radiation Effects Conference, Jul 2015, Boston, MA, United States. <10.1109/TNS.2015.2496874>
- Impact of Stacked-Layer Structure on SEE Rate of SRAMsViyas Gupta, Alexandre Louis Bosser, Georgios Tsiligiannis, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi DililloNSREC: Nuclear and Space Radiation Effects Conference, IEEE / NPSS, Jul 2015, Boston, United States.
- Generic Analytic Expression of Heavy Ion SEU Cross Section Derived from Monte-Carlo Diffusion-Based Prediction CodeFrédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Robert Ecoffet, Eric Lorfèvre, Francoise Bezerra, Markus Brugger, Rubén García Alía, Frédéric SaignéNSREC: Nuclear and Space Radiation Effects Conference, IEEE / NPSS, Jul 2015, Boston, United States. <http://www.nsrec.com/2015Brochure.pdf>
- An ATPG Flow to Generate Crosstalk-Aware Path Delay PatternAnu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge PravossoudovitchISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.515-520.
- Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuitsStephan de Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.362-367.
- 3D DFT Challenges and SolutionsYassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen SchloeffelISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.603-608.
- Digital Right Management for IP ProtectionJerome Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, Mario BarbareschiISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.200-203.
- A framework for efficient implementation of analog/RF alternate test with model redundancySyhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel RenovellISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.621-626.
- Toward adaptation of ADCs to operating conditions through on-chip correctionVincent Kerzérho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge BernardISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.634-639.
- STT-MRAM-Based Strong PUF ArchitectureElena Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo PrinettoISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.467-472.
- Design space exploration and optimization of a Hybrid Fault-Tolerant ArchitectureImran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza ReordaIOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. pp.89-94.
- Digital on-chip measurement circuit for built-in phase noise testingStéphane David-Grignot, Florence Azaïs, Laurent Latorre, François LefevreIMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. <10.1109/IMS3TW.2015.7177880>
- A generic methodology for building efficient prediction models in the context of alternate testingSyhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel RenovellIMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. <10.1109/IMS3TW.2015.7177873>
- Real-Time SRAM Based Particle DetectorLuigi Dilillo, Alexandre Louis Bosser, Viyas Gupta, Frédéric Wrobel, Frédéric SaignéIWASI: International Workshop on Advances in Sensors and Interfaces, Politecnico di Bari, Jun 2015, Gallipoli, Italy. pp.58-62.
- Power-aware voltage tuning for STT-MRAM reliabilityElena Ioana Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan FiguerasETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. <10.1109/ETS.2015.7138748>
- Analog test: Why still “à la mode” after more than 25 years of research?Florence AzaïsETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. <10.1109/ETS.2015.7138772>
- An effective hybrid fault-tolerant architecture for pipelined coresImran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick GirardETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. <10.1109/ETS.2015.7138733>
- A New Technique for Low-Cost Phase Noise Production Testing from 1-bit Signal AcquisitionStéphane David-Grignot, Florence Azaïs, Laurent Latorre, François LefevreETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. pp.1-6.
- Session-less based thermal-aware 3D-SIC test schedulingMarie-Lise Flottes, João Azevedo, Giorgio Di Natale, Bruno RouzeyreETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. <10.1109/ETS.2015.7138732>
- Challenges in Designing Trustworthy Cryptographic Co-ProcessorsRicardo Chaves, Giorgio Di Natale, Lejla Batina, Shivam Bhasin, Baris Ege, Apostolos Fournaris, Nele Mentens, Stjepan Picek, Francesco Regazzoni, Vladimir Rozic, Nicolas Sklavos, Bohan YangISCAS: International Symposium on Circuits and Systems, May 2015, Lisbon, Portugal. pp.2009-2012.
- Special session: Hot topics: Statistical test methodsManuel J. Barragan, Gildas Leger, Florence Azaïs, R. D. Blanton, Adit D. Singh, Stephen SunterVTS: VLSI Test Symposium, Apr 2015, Napa, CA, United States. <10.1109/VTS.2015.7116265>
- Embedded test instrument for on-chip phase noise evaluation of analog/IF signalsFlorence Azaïs, Stéphane David-Grignot, Laurent Latorre, François LefevreDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.237-242.
- Design-for-Diagnosis Architecture for Power SwitchesMiroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane GuilhotDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48.
- Scan-chain intra-cell defects gradingAymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza ReordaDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. <10.1109/DTIS.2015.7127349>
- An effective ATPG flow for Gate Delay FaultsAlberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza ReordaDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. <10.1109/DTIS.2015.7127350>
- On the limitations of logic testing for detecting Hardware Trojans HorsesMarie-Lise Flottes, Sophie Dupuis, Papa-Sidy Ba, Bruno RouzeyreDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. <10.1109/DTIS.2015.7127362>
- Software testing and software fault injectionMaha Kooli, Alberto Bosio, Pascal Benoit, Lionel TorresDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. <10.1109/DTIS.2015.7127370>
- Statistical Energy Study for 28nm FDSOI DevicesRida Kheirallah, Jean-Marc Galliere, Aida Todri-Sanial, Gilles R. Ducharme, Nadine AzemardEuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2015, Budapest, Hungary. <10.1109/EuroSimE.2015.7103149>
- Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technologySylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick GirardISQED: International Symposium on Quality Electronic Design, Apr 2015, Santa Clara, United States. pp.366-370.
- A digital technique for the evaluation of SSB phase noise of analog/RF signalsFlorence Azaïs, Stéphane David-Grignot, François Lefevre, Laurent LatorreLATS: Latin-American Test Symposium, Mar 2015, Puerto Vallarta, Mexico. <10.1109/LATW.2015.7102407>
- Ring Oscillators Analysis for FPGA Security PurposesMario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel TorresTRUDEVICE, Mar 2015, Grenoble, France.
- Exploring the impact of functional test programs re-used for power-aware testingAymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza ReordaDATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.1277-1280.
- New Testing Procedure for Finding Insertion Sites of Stealthy Hardware TrojansSophie Dupuis, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Papa-Sidy BaDATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.776-781.
- STT MRAM-Based PUFsElena Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo PrinettoDATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.872-875.
2014
- On the Generation of Diagnostic Test Set for Intra-cell DefectsZhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne AuvrayATS: Asian Test Symposium, Nov 2014, Hangzhou, China. pp.312-317.
- Low-cost phase noise testing of complex RF ICs using standard digital ATEStéphane David-Grignot, Florence Azaïs, Laurent Latorre, François LefevreITC: International Test Conference, Oct 2014, Seattle, WA, United States. <10.1109/TEST.2014.7035301>
- TRUDEVICE Project: Trustworthy Manufacturing and Utilization of Secure DevicesNicolas Sklavos, Giorgio Di NataleHiPEAC Computing Systems Week (CSW), Oct 2014, Athens, Greece. <https://www.hipeac.net/csw/2014/athens/>
- Laser-Induced Fault Effects in Security-Dedicated CircuitsVincent Beroulle, Philippe Candelier, Stephan de Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hely, Guillaume Hubert, R. Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clement Tavernier, Pierre VanhauwaertVLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240.
- Secure Test Method for Fuzzy ExtractorMafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di NataleJoint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands.
- Multi-stage Cross-layer Hardware Trojan Prevention, Detection and ToleranceCristiana Bolchini, Luca Cassano, Giorgio Di NataleJoint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands.
- MRAM-based PUFGiorgio Di Natale, Paolo Prinetto, Elena Ioana VatajeluJoint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands.
- Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOSJean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Alexandre Sarafianos25th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2014), Sep 2014, Berlin, Germany.
- Stochastic model for phase noise measurement from 1-bit signal acquisitionStéphane David-Grignot, Florence Azaïs, François Lefevre, Laurent LatorreIMS3TW: International Mixed-Signals, Sensors, and Systems Test Workshop, Sep 2014, Porto Alegre, Brazil. <10.1109/IMS3TW.2014.6997400>
- Study of adaptive tuning strategies for Near Field Communication (NFC) transmitter moduleMouhamadou Dieng, Florence Azaïs, Mariane Comte, Serge Bernard, Vincent Kerzérho, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-ContiIMS3TW: International Mixed-Signals, Sensors, and Systems Test Workshop, Sep 2014, Porto ALegre, Brazil. <10.1109/IMS3TW.2014.6997401>
- Cross-Layer Early Reliability Evaluation for the Computing cOntinuumStefano Di Carlo, Alessandro Vallero, Dirnitris Gizopoulos, Giorgio Di NataleDSD: Digital System Design, Aug 2014, Verona, Italy. pp.199-205.
- Single Event Upset Prediction from Heavy Ions Cross Sections with No ParametersFrédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Frédéric SaignéNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
- SEU Cross Section Calculation Based on Experimental Data of Another kind of ParticleAnnelise Touboul, Antoine Touboul, Frédéric Wrobel, V. Pouget, Luigi Dilillo, Frédéric Saigné, Robert Ecoffet, Eric Lorfèvre, Françoise Bezerra, Markus BruggerNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
- Efficient Dynamic Test Methods for COTS SRAMs Under Heavy Ion IrradiationGeorgios Tsiligiannis, Luigi Dilillo, Viyas Gupta, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Helmut Puchner, Alexandre Louis Bosser, Arto Javanainen, Ari Virtanen, Frédéric Wrobel, Laurent Dusseau, Frédéric SaignéNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France.
- Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude Vs. Underground Experiments, Modeling and Numerical Monte Carlo SimulationTarek Saad Saoud, Soilihi Moindjie, Jean-Luc Autran, Daniela Munteanu, Frédéric Wrobel, Frédéric Saigné, Philippe Cocquerez, Luigi DililloNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
- Real-Time Testing of 90nm COTS SRAMs at Concordia Station in AntarcticaGeorgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Philippe Cocquerez, Jean-Luc Autran, Antonio Litterio, Frédéric Wrobel, Frédéric SaignéNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
- A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply NoiseAnu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud VirazelISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.226-231.
- 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT ArchitecturesYassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen SchloeffelISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.386-391.
- A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware TrojansSophie Dupuis, Papa-Sidy Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54.
- Customized Cell Detector for Laser-Induced-Fault DetectionFeng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. pp.37-42.
- Cross-Layer Early Reliability Evaluation: Challenges and PromisesStefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Antonio Gonzales, Ramon Canal, Riccardo Mariani, Mauro Pipponzi, Arnaud Grasset, Philippe Bonnot, Frank Reichenback, Gulzaib Rafiw, Trond LoekstadIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.228-233.
- Solutions for the self-adaptation of communicating systems in operationMartin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzérho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G StratigopoulosIOLTS: International On-line Test Symposium, Jul 2014, Platja d’Aro, Spain. pp.234-239.
- Self-Adaptive NFC SystemsVincent Kerzérho, Florence Azaïs, Mouhamadou Dieng, Mariane Comte, Serge Bernard, Michel Renovell, Paul-Henri Pugliesi-Conti, Thibault KervaonIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain.
- Phase noise measurement on IF analog signals using standard digital ATE resourcesStéphane David-Grignot, Laurent Latorre, Florence Azaïs, François LefevreNEWCAS: New Circuits and Systems, Jun 2014, Trois-Rivieres, Canada. pp.121-124.
- Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approachFeng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreTRUDEVICE Workshop, May 2014, Paderborn, Germany. <http://www.ets14.de/media/PDFs/workshops/TRUDEVICE-ETS14-PreliminaryProgam>
- Investigations on alternate analog/RF test with model redundancyHaithem Ayari, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Syhem Larguech, Mariane Comte, Michel RenovellSTEM Workshop, May 2014, Paderborn, Germany. <http://www.ets14.de/pages/workshops/stem-workshop.php>
- Presentation of the MTCube CubeSat ProjectViyas Gupta, Luigi Dilillo, Frédéric Wrobel, Ali Mohammadzadeh, Georgios Tsiligiannis, Muriel Bernard, Laurent Dusseau4S: Small Satellites Systems and Services Symposium, European Space Agency (ESA); Centre National d'Etudes Spatiales (CNES), May 2014, Majorca, Spain. <http://congrexprojects.com/2014-events/4S2014/home>
- iBoX — Jitter based Power Supply Noise sensorMiroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel, Patrick Girard, Philippe Debaud, Stephane GuilhotETS: European Test Symposium, May 2014, Paderborn, United States. <10.1109/ETS.2014.6847830>
- Fault injection tools based on Virtual MachinesMaha Kooli, Giorgio Di Natale, Pascal Benoit, Alberto Bosio, Lionel Torres, Volkmar SiehReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. <10.1109/ReCoSoC.2014.6861351>
- A novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMRLuca Cassano, Alberto Bosio, Giorgio Di NataleETS: European Test Symposium, May 2014, Paderborn, Germany. <10.1109/ETS.2014.6847831>
- Radiation Study of a 4Mbit Ferroelectric RAM for Space ApplicationsHelmut Puchner, Georgios Tsiligiannis, Luigi DililloSEE: Single Event Effects, Aeroflex Corporation, the Aerospace Corporation, Brigham Young University, Lockheed Martin, the NASA Electronic Parts and Packaging Program, the Naval Research Laboratory, Sandia National Laboratories, and Vanderbilt University, May 2014, San Diego, United States. <http://radhome.gsfc.nasa.gov/radhome/see_mapld/2014/index.cfm>
- A Comprehensive Evaluation of Functional Programs for Power-Aware TestAymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo BernardiNATW: North Atlantic Test Workshop, May 2014, Johnson City, NY, United States. pp.69-72.
- Laser attacks on integrated circuits: from CMOS to FD-SOIJean-Max Dutertre, Stephan de Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, Mathieu Lisart, Joel Damiens, Philippe Candelier, Marie-Lise Flottes, Giorgio Di NataleDTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. <10.1109/DTIS.2014.6850664>
- A survey on simulation-based fault injection tools for complex systemsMaha Kooli, Giorgio Di NataleDTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorini, Greece. <10.1109/DTIS.2014.6850649>
- Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate levelFeng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno RouzeyreDTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. <10.1109/DTIS.2014.6850665>
- Protecting combinational logic in pipelined microprocessor cores against transient and permanent faultsImran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-SanialDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.223-225.
- Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounceAnu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud VirazelDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.207-212.
- Test and diagnosis of power switchesMiroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel, Patrick Girard, Philippe Debaud, Stephane GuilhotDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.213-218.
- Timing-aware ATPG for critical paths with multiple TSVsCarolina Momo Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud VirazelDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.116-121.
- An intra-cell defect grading toolAlberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Stefano Bernabovi, Paolo BernardiDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.298-301.
- TSV aware timing analysis and diagnosis in paths with multiple TSVsCarolina Momo Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud VirazelVTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. <10.1109/VTS.2014.6818772>
- Built-In Self-Test for Manufacturing TSV Defects before bondingGiorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim ZimoucheVTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. <10.1109/VTS.2014.6818771>
- Hacking and Protecting IC HardwareSaid Hamdioui, Giorgio Di Natale, Battum Van, Jean-Luc Danger, Fethulah Smailbegovic, Mark TehranipoorDATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. <10.7873/DATE.2014.112>
- Testing PUF-Based Secure Key Storage CircuitsMafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di NataleDATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. <10.7873/DATE.2014.207>
- New implementions of predictive alternate analog/RF test with augmented model redundancyHaithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel RenovellDATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. <10.7873/DATE2014.144>
- Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testingSyhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Mariane Comte, Michel RenovellLATW: Latin American Test Workshop, Mar 2014, Fortaleza, Brazil. <10.1109/LATW.2014.6841930>
- Experimental Heavy-Ion SEU Cross-Sections Of Sram Memory ComponentsAlexandre Louis Bosser, Luigi Dilillo, Viyas Gupta, Arto Javanainen, Heikki Kettunen, Mario Rossi, Georgios Tsiligiannis, Ari VirtanenPhysics Days, Finnish Physical Society, Tampere University of Technology (TUT), and Tavicon Ltd., Mar 2014, Tampere, Finland. <http://webhotel2.tut.fi/fys/physicsdays/>
- Hacking and protecting IC hardwareSaïd Hamdiaoui, Jean-Luc Danger, Giorgio Di Natale, Fethulah Smailbegovic, Gerard van Battum, Mark TehranipoorDATE, Mar 2014, Dresden, Germany.
- Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal considerationYuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud VirazelASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. pp.544-549.
Last update on 04/01/2021
Department : Microélectronique
Head : Arnaud VIRAZEL