TEST: Test and dEpendability of microelectronic integrated SysTems

Les travaux conduits dans l’équipe TEST ont pour objectif principal le développement de modèles, de méthodes et d’outils permettant d’assurer la qualité d’un dispositif microélectronique intégré après fabrication.

Nos contributions principales concernent l’impact des technologies récentes et émergentes sur la qualité des dispositifs et les coûts de mise en oeuvre avec en particulier les problématiques liées à la complexité d’intégration, à la variabilité des paramètres de fabrication et à la consommation croissante des circuits intégrés. Elles concernent également la prise en compte des contraintes spécifiques liées aux circuits sécurisés et à l’environnement d’utilisation (spatial et radiatif). Les technologies étudiées, et leur prise en compte dans un flot de conception pour la création de systèmes fiables et testables, englobent les technologies CMOS avancées, par exemple FDSOI/FinFET, ainsi que les technologies de rupture comme l’intégration 3D où les technologies émergentes de mémoires.

Les recherches menées aboutissent à la proposition de nouveaux modèles de fautes, au développement d’instruments de monitoring ou de nouvelles méthodes de conception en vue du test et à la proposition de nouvelles architectures matérielles intégrées au système afin de surveiller son fonctionnement tout au long de sa vie.

L’équipe TEST est la plus grande équipe académique au niveau international dont les thématiques de recherche sont intégralement dédiées aux problématiques de test et fiabilité des composants constituant un système intégré microélectronique. Ceci lui permet d’adresser les multiples facettes de cette thématique : digital, analogique, RF, mémoires, ...

Activités scientifiques

Les activités scientifiques de l’équipe TEST sont structurées autour de 4 axes de recherche adressant les problématiques de Fiabilité et de Test dans les domaines suivants :

• Axe 1 : Circuits digitaux, analogiques et RFs

• Axe 2 : Circuits sécurisés

• Axe 3 : Technologies et Paradigmes Emergents

• Axe 4 : Environnements Spatial et Radiatif

L’axe 1 regroupe les activités « coeurs de métier » de l’équipe et les axes 2, 3, et 4 sont liés aux travaux menés dans les thèmes transversaux du département Microélectronique avec la prise en compte de contraintes spécifiques liées aux circuits sécurisés, aux technologies et paradigmes émergents ainsi qu’aux environnements hostiles.

Axe 1 : Fiabilité et Test des Circuits Digitaux, Analogiques et RFs

Les systèmes sur puce ont vu leur surface augmenter d’un facteur 10 et leur consommation multiplier par 5 lors des dix dernières années. Chaque saut technologique ayant permis cette intégration a aussi ajouté de nouvelles contraintes faisant obstacle à la fiabilité du système. Par exemple, l’augmentation des variations PVT ou de la densité et de la nature des défauts, l’ajout de structures spécifiques pour le contrôle de la puissance consommée…

Il est donc nécessaire de développer des solutions de test et d’amélioration de la fiabilité afin de garantir le rendement de production (le plus élevé possible) et la durée de vie du système (la plus longue possible). De plus, l’intégration de blocs analogiques et RF pose de nombreux problèmes, principalement liés au fait que les méthodes de l’état de l’art utilisées pour tester ces blocs nécessitent l’utilisation de ressources de test spécifiques extrêmement coûteuses par rapport aux ressources numériques disponibles sur un équipement de test standard.

Axe 2 : Fiabilité, Test, Confiance et Sécurité des Circuits Intégrés

L’accroissement massif de l’utilisation de systèmes communicants a introduit la sécurité comme pivot de leur développement. De plus, comme la conception et la fabrication de ces systèmes sont devenues des opérations extrêmement complexes et géographiquement distribuées sur toute la planète, de nouvelles vulnérabilités de sécurité et de confiance sont apparues. Par conséquence, la totalité du flot de production du matériel est devenue elle-même sujette à des problèmes de sécurité et de confiance, qui incluent les attaques par canaux cachés, la rétro-ingénierie, le piratage des propriétés intellectuelles (IP), jusqu’à la modification mal intentionnée des circuits.

Axe 3 : Fiabilité et Test des technologies émergentes

La fin prévue de la course à la miniaturisation entraine aujourd’hui la communauté vers une démarche en rupture, usuellement intitulée « More than Moore ». La stratégie dans ce cadre consiste à explorer des solutions relevant du changement de matériaux, d’architectures, de méthodes ou de paradigmes de conception.

Axe 4 : Fiabilité et Test en environnements spatial et radiatif

Les composants électroniques peuvent être soumis à différentes sources de radiations en fonction du contexte applicatif que ce soient des environnements naturels comme l’espace et l’atmosphère ou des environnements artificiels tels que les accélérateurs de particules ou les réacteurs nucléaires.

Ces radiations peuvent entrainer des perturbations dans le fonctionnement des systèmes intégrés microélectroniques. De nombreuses applications sensibles ne peuvent tolérer un taux de défaillance important du fait de leur criticité. De part la complexité des effets induits par les radiations ionisantes, nos travaux dans ce domaine portent sur le développement de méthodes d'analyse et d'expérimentation. En plus des effets radiatifs, les effets de la température sont également pris en compte dans le cadre de cet axe de recherche.

Contrats de Recherche

TRUDEVICE :

Trustworthy Manufacturing and Utilization of Secure Devices

CLERECO :

Cross-Layer Early Reliability Evaluation for the Computing cOntinuum

MTCUBE :

Memory Test CUBEsat

TEEVA :

TEEVA - Trusted Execution Environment

Rayonnement

Les membres de l’équipe sont fortement impliqués dans les conférences ETS «European Test Symposium» (organisation en 2013, président de comité des programmes de 2015 à 2016, Publication Chair de 2015 à 2016 et membres du Steering Commitee), VTS « VLSI Test Symposium » (Publication Chair depuis 2012, General chair en 2013 et membre du comité des programmes) et DATE «Design Automation and Test in Europe» (Program Vice-Chair en 2016 et Program Chair en 2017, membre du comité exécutif depuis 2013).

Nous participons aussi très activement aux conférences et workshop internationaux relatifs à nos axes de recherche : IEEE Computer Society Annual Symposium on VLSI (Program Co-Chair en 2016 General co-chair en 2015 et Track Chair de 2015 à 2017 et Publication Chair en 2015), Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (General chair de 2013 à 2016 et Program Chair de 2013 à 2014), IEEE International Mixed-Signals Test Workshop (Chair du Steering Committe de 2013 à 2016, Program Chair en 2014). Des membres de l’équipe sont aussi impliqués dans les comités de lecture des revues majeures de notre domaine : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Computers, JETTA – Journal of Electronic Testing – Theory and Applications, IEEE Transactions on Very Large Scale Integration Systems, IEEE Transactions on Emerging Topics in Computing, JOLPE - Journal of Low Power Electronics, ACM Journal of Emerging Technologies in Computing Systems.

Nous participons aussi très activement à l’IEEE Computer Society European TTTC (Test Technology Technical Council) (Chair depuis 2014, Electronic Media chair depuis 2012).

Au niveau national, nous sommes fortement impliqués dans le GdR SoC-SiP/SoC2 (directeur adjoint, création et responsabilité du groupe de travail Sécurité des Systèmes Matériels, membres du comité de pilotage), dans le pré-GdR Sécurité Informatique (membre du bureau) et dans le GdR ERRATA (membre du bureau et organisation des journées thématiques RADSOL).

Membres

Permanents

Non permanents

Publications depuis 2013 - Evaluation 2019

Articles de revues internationales

2018

  1. Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption
    Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2018. <10.1109/TCAD.2018.2818722>
  2. On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints
    Stéphane David-Grignot, Achraf Lamlih, Mohamed Moez Belhaj, Vincent Kerzérho, Florence Azaïs, Fabien Soulier, Philippe Freitas, Tristan Rouyer, Sylvain Bonhommeau, Serge Bernard
    Journal of Electronic Testing, Springer Verlag, 2018. <10.1007/s10836-018-5710-4>
  3. Towards a Dependable True Random Number Generator With Self-Repair Capabilities
    Honorio Martin, Giorgio Di Natale, Luis Entrena
    IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2018, 65 (1), pp.247-256.
  4. Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges Ahead
    Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IEEE Design & Test, IEEE, 2018, 35 (2), pp.73-90.
  5. Assessing Body Built-In Current Sensors for Detection of Multiple Transient Faults
    Raphael Andreoni Camponogara-Viera, Jean-Max Dutertre, O. Potin, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Rodrigo Possamai Bastos
    Microelectronics Reliability, Elsevier, 2018.

2017

  1. A calculation method to estimate single event upset cross section
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Jérôme Boch, Frédéric Saigné
    Microelectronics Reliability, Elsevier, 2017, 76-77, pp.644-649.
  2. Report on DATE 2017 in Lausanne
    David Atienza, Giorgio Di Natale
    IEEE Design & Test, IEEE, 2017, 34 (4), pp.76-77.
  3. Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies
    Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell
    Journal of Electronic Testing, Springer Verlag, 2017, 33 (4), pp.515-527.
  4. HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization
    Arnaud Virazel, Alejandro Nocua, Alberto Bosio, Patrick Girard, Cyril Chevalier
    Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2017, 26 (08). <10.1142/S0218126617400047>
  5. Microprocessor Testing: Functional Meets Structural Test
    Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
    Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2017, 26 (08). <10.1142/S0218126617400072>
  6. Computing reliability: On the differences between software testing and software fault injection techniques
    Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, Lionel Torres
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2017, 50, pp.102-112.
  7. Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI Technology
    Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell
    IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2017, 16 (3), pp.417-430.
  8. Design of a radiation tolerant system for total ionizing dose monitoring using floating gate and RadFET dosimeters
    Rudy Ferraro, Salvatore Danzeca, Matteo Brucoli, Alessandro Masi, Markus Brugger, Luigi Dilillo
    Journal of Instrumentation, IOP Publishing, 2017, 12, pp.1-13.
  9. Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era
    Aida Todri-Sanial, Saraju Mohanty, Mariane Comte, Marc Belleville
    ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2017, 13 (2), pp.1-2.
  10. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits
    Arnaud Virazel, Imran Wali, Bastien Deveautour, Alberto Bosio, Patrick Girard, M. Sonza Reorda
    Journal of Electronic Testing, Springer Verlag, 2017, 33 (1), pp.25-36.
  11. A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions
    Mario Barbareschi, Giorgio Di Natale, Lionel Torres, Antonino Mazzeo
    IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, In press, pp.1-23.
  12. A Cross-Level Power Estimation Technique to Improve IP Power Models Quality
    Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
    Journal of Low Power Electronics, American Scientific Publishers, 2017, 13 (1), pp.10-28.

2016

  1. An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization
    Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick Girard
    Journal of Electronic Testing, Springer Verlag, 2016, 32 (6), pp.721-733.
  2. Soft errors in commercial off-the-shelf static random access memories
    Luigi Dilillo, Georgios Tsiligiannis, Viyas Gupta, Alexandre Bosser, Frédéric Saigné, Frédéric Wrobel
    Semiconductor Science and Technology, IOP Publishing, 2016, Special Issue on Radiation Effects in Semiconductor Devices, 32 (1). <10.1088/1361-6641/32/1/013006>
  3. Frontside Versus Backside Laser Injection: A Comparative Study
    Stephan De Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes
    ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, Special Issue on Secure and Trustworthy Computing, 13 (1), pp.Art 7.
  4. Ring oscillators analysis for security purposes in Spartan-6 FPGAs
    Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (Part A), pp.3-10.
  5. The Power Law Shape of Heavy Ions Experimental Cross Section
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Eric Lorfèvre, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 64 (1), pp.427-433.
  6. Methodologies for the Statistical Analysis of Memory Response to Radiation
    Alexandre Bosser, Viyas Gupta, Georgios Tsiligiannis, Christopher Frost, Ali Mohammad Zadeh, Jukka Jaatinen, Arto Javanainen, Helmut Puchner, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2122-2128.
  7. Proton-Induced Single-Event Degradation in SDRAMs
    Axel Rodriguez, Frédéric Wrobel, Anne Samaras, Francoise Bezerra, Benjamin Vandevelde, Robert Ecoffet, Antoine Touboul, Christian Chatry, Luigi Dilillo, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2115-2121.
  8. Heavy-Ion Radiation Impact on a 4 Mb FRAM Under Different Test Modes and Conditions
    Viyas Gupta, Alexandre Bosser, Georgios Tsiligiannis, Ali Mohammad Zadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2016, 63 (4), pp.2010-2015.
  9. A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores
    Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
    Journal of Electronic Testing, Springer Verlag, 2016, 32 (2), pp.147-161.
  10. SSB Phase Noise Evaluation of Analog/IF Signals on Standard Digital ATE
    Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre
    Journal of Electronic Testing, Springer Verlag, 2016, 32 (1), pp.69-82.
  11. Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE)
    Lilian Bossuet, Giorgio Di Natale, Paris Kitsos
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 47 (A), pp.1-2.
  12. Scan-Chain Intra-Cell Aware Testing
    Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Matteo Sonza Reorda, Paolo Bernardi, Etienne Auvray
    IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2016, PP (99), In press. <10.1109/TETC.2016.2624311>
  13. Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits
    Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre
    Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016. <10.1142/S0218126616400144>
  14. Design for Test and Diagnosis of Power Switches
    Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
    Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.1640013.
  15. STT-MRAM-Based PUF Architecture exploiting Magnetic Tunnel Junction Fabrication-Induced Variability
    Ioana Vatajelu, Giorgio Di Natale, Mario Barbareschi, Lionel Torres, Marco Indaco, Paolo Prinetto
    ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2016, 13 (1). <10.1145/2790302>

2015

  1. Investigation on MCU Clustering Methodologies for Cross-Section Estimation of RAMs
    Alexandre Bosser, Viyas Gupta, Georgios Tsiligiannis, Arto Javanainen, Heikki Kettunen, Helmut Puchner, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2015, 62 (6), pp.2620-2626.
  2. SEE on Different Layers of Stacked-SRAMs
    Viyas Gupta, Alexandre Bosser, Georgios Tsiligiannis, Mathias Rousselet, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi Dilillo
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2015, 62 (6 ), pp.2673-2678.
  3. Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies
    Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    Microelectronics Journal, Elsevier, 2015, 46 (11), pp.1091-1102.
  4. Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview
    Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Kooli Maha, Savino Alessandro, Politano Gianfranco, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di Carlo
    Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2015, 39 (8), pp.1204-1214.
  5. Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range
    Stéphane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre
    Journal of Electronic Testing, Springer Verlag, 2015, pp.1-17.

2014

  1. Heavy Ion SEU Cross Section Calculation Based on Proton Experimental Data, and Vice Versa
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Robert Ecoffet, Eric Lorfèvre, Francoise Bezerra, Markus Brugger, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3564-3571.
  2. Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude vs. Underground Experiments, Modeling and Numerical Monte Carlo Simulation
    Tarek Saad Saoud, Soilihi Moindjie, Jean-Luc Autran, Daniela Munteanu, Frédéric Wrobel, Frédéric Saigné, Philippe Cocquerez, Luigi Dilillo, Maximilien Glorieux
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3380-3388.
  3. Dynamic Compact Model of Self-Referenced Magnetic Tunnel Junction
    João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Jérémy Alvarez-Hérault, Ken Mackay
    IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2014, 61 (11), pp.3877-3882.
  4. 90 nm SRAM Static and Dynamic Mode Real-Time Testing at Concordia Station in Antarctica
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Philippe Cocquerez, Jean-Luc Autran, Antonio Litterio, Frédéric Wrobel, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3389-3394.
  5. Dynamic Test Methods for COTS SRAMs
    Georgios Tsiligiannis, Luigi Dilillo, Viyas Gupta, Alberto Bosio, Patrick Girard, Arnaud Virazel, Helmut Puchner, Alexandre Bosser, Arto Javanainen, Ari Virtanen, Christopher Frost, Frédéric Wrobel, Laurent Dusseau, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (6), pp.3095-3102.
  6. Testing Methods for PUF-Based Secure Key Storage Circuits
    Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.581-594.
  7. Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS
    Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Alexandre Sarafianos
    Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2289-2294.
  8. On the Test and Mitigation of Malfunctions in Low-Power SRAMs
    Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.611-627.
  9. Testing for Gate Oxide Short Defects using the Detectability Interval Paradigm
    Jean-Marc Galliere, Florence Azaïs, Mariane Comte, Michel Renovell
    Information Technology, Oldenbourg Verlag, 2014, 56 (4), pp.173-181.
  10. Gate Voltage Contribution to Neutron-Induced SEB of Trench Gate Fieldstop IGBT
    Lionel Foro, Antoine Touboul, Alain Michez, Frédéric Wrobel, Paolo Rech, Luigi Dilillo, Christopher Frost, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1739-1746.
  11. Evaluating a Radiation Monitor for Mixed-Field Environments based on SRAM Technology
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Frédéric Wrobel, Frédéric Saigné
    Journal of Instrumentation, IOP Publishing, 2014, 9. <10.1088/1748-0221/9/05/C05052>
  12. Multiple Cell Upset Classification in Commercial SRAMs
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Helmut Puchner, Christopher Frost, Frédéric Wrobel, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1747-1754.
  13. On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis
    Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    Information Security Journal: A Global Perspective, Taylor & Francis, 2014, Trustworthy Manufacturing and Utilization of Secure Devices, 22 (5-6), pp.226-236.
  14. TRUDEVICE: A COST Action on "Trustworthy Manufacturing and Utilization of Secure Devices" (Editorial)
    Giorgio Di Natale
    Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.205-207.
  15. Multi-Level Ionizing-Induced Transient Fault Simulator
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.251-264.
  16. Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison
    Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (4), pp.947-951.
  17. Determining Realistic Parameters for the Double Exponential Law that Models Transient Current Pulses
    Frédéric Wrobel, Luigi Dilillo, Antoine Touboul, Vincent Pouget, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1813-1818.
  18. Enhancing Confidence in Indirect Analog/RF Testing against the Lack of Correlation between Regular Parameters and Indirect Measurements
    Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    Microelectronics Journal, Elsevier, 2014, 45 (3), pp.336-344.
  19. An SRAM Based Monitor for Mixed-Field Radiation Environments
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Frédéric Wrobel, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2014, 61 (4), pp.1663-1670.
  20. Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers
    Ahmed Rekik, Florence Azaïs, Frédérick Mailly, Pascal Nouet
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (1), pp.87-100.
  21. A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs
    João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Hérault, Ken Mackay
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (11), pp.2326-2335.
  22. Globally Constrained Locally Optimized 3-D Power Delivery Networks
    Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (10), pp.2131-2144.
  23. Test versus Security: Past and Present
    Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
    IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2014, pp.13.
  24. Intra-Cell Defects Diagnosis
    Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.541-555.
  25. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems
    Ahn Duc Tran, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Hans-Joachim Wunderlich
    Journal of Electronic Testing, Springer Verlag, 2014, 30 (4), pp.401-413.

2013

  1. A regular fabric design methodology for applications requiring specific layout-level design rules
    Sophie Dupuis, Noury Ludovic, Fel Nicolas
    Microelectronics Journal, Elsevier, 2013, 45 (2), pp.217-225.
  2. A Novel Differential Scan Attack on Advanced DFT Structures
    Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    ACM Transactions on Design Automation of Electronic Systems, Association for Computing Machinery, 2013, 18 (4), pp.58.
  3. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection
    Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale
    Microelectronics Reliability, Elsevier, 2013, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 53 (9), pp.1320-1324.
  4. A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC
    Vincent Kerzérho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, Guilherme Bontorin, Michel Renovell
    Microelectronics Journal, Elsevier, 2013, 44 (9), pp.840-843.
  5. Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption
    Paolo Bernardi, Mauricio De Carvalho, Ernesto Sanchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard
    Journal of Low Power Electronics, American Scientific Publishers, 2013, 9 (2), pp.253-263.
  6. A Silicon Diode-Based Detector for Investigations of Atmospheric Radiation
    Frédéric Wrobel, Jean-Roch Vaillé, Denis Pantel, Luigi Dilillo, Jean-Marc Galliere, Jean-Luc Autran, Philippe Cocquerez, Pierre Chadoutaud, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2013, 60 (5), pp.3603-3608.
  7. Proton Flux Anisotropy in the Atmosphere: Experiment and Modeling
    Frédéric Wrobel, Jean-Roch Vaillé, Denis Pantel, Luigi Dilillo, Jean-Marc Galliere, Antoine Touboul, Pierre Chadoutaud, Philippe Cocquerez, Michel Lacourty, Marie-Anne Claire, Jean-Luc Autran, Christian Chatry, Florent Laplanche, Bruno Azais, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2013, 60 (4), pp.2386-2391.
  8. Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation
    Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2013, 21 (5), pp.958-970.
  9. A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic
    Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre
    Journal of Electronic Testing, Springer Verlag, 2013, pp.001-010.
  10. Testing a Commercial MRAM under Neutron and Alpha Radiation in Dynamic Mode
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Steven Mcclure, Antoine Touboul, Frédéric Wrobel, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2013, 60 (4), pp.2617-2622.
  11. A Study of Tapered 3-D TSVs for Power and Thermal Integrity
    Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2013, 21 (2), pp.306-319.
  12. Soft Error Triggering Criterion Based on Simplified Electrical Model of the SRAM cell
    Frédéric Wrobel, Antoine Touboul, Luigi Dilillo, Frédéric Saigné
    IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2013, 60 (4), pp.2537-2541.
  13. Secure JTAG Implementation Using Schnorr Protocol
    Amitabh Das, Jean Da Rolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
    Journal of Electronic Testing, Springer Verlag, 2013, 29 (2), pp.193-209.

Communications internationales

2018

  1. Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model
    Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Faber Louis-Barthelemy, Marie-Lise Flottes, Gendrier Philippe, David Hely, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
    FDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. 14th Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018.
  2. Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection
    Maxime Cozzi, Jean-Marc Galliere, Philippe Maurine
    DSD: Digital System Design, Aug 2018, Prague, Slovakia. Euromicro Conference on Digital System Design, 2018. <http://dsd-seaa2018.fit.cvut.cz/dsd/>
  3. The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks
    Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hely, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
    IOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. 24th IEEE International Symposium on On-Line Testing and Robust System Design, 2018. <10.1109/IOLTS.2018.8474230>
  4. Encryption of test data: which cipher is better?
    Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
    PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. IEEE, 14th Conference on PhD Research in Microelectronics and Electronics, 2018. <10.1109/PRIME.2018.8430366>
  5. A new secure stream cipher for scan chain encryption
    Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
    IVSW: International Verification and Security Workshop, Jul 2018, Platja d’Aro, Spain. 3nd International Verification and Security Workshop, 2018. <http://tima.univ-grenoble-alpes.fr/conferences/ivsw/ivsw18/>
  6. Combined analysis of supply voltage and body-bias voltage for energy management
    Rida Kheirallah, Jean-Marc Galliere, Nadine Azemard, Gilles Ducharme
    PATMOS: Power and Timing Modeling, Optimization and Simulation, Jul 2018, Platja d’Aro, Spain. 28th IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation, 2018. <10.1109/PATMOS.2018.8464159>
  7. Distributed Optical Fiber Radiation Sensing at CERN
    Gaetano Li Vecchi, Markus Brugger, Salvatore Danzeca, Diego Di Francesca, Rudy Ferraro, Sylvain Girard, Yacine Kadi, Oliver Stein
    9th International Particle Accelerator Conference, Apr 2018, Vancouver, Canada. pp.WEPAF083, 2018.
  8. Thermal Scans for Detecting Hardware Trojans
    Maxime Cozzi, Philippe Maurine, Jean-Marc Galliere
    COSADE: Constructive Side-Channel Analysis and Secure Design, Apr 2018, Singapour, Singapore. 9th International Workshop on Constructive Side-Channel Analysis and Secure Design, LNCS (10815), pp.117-132, 2018, COSADE 2018.
  9. SECCS: SECure Context Saving for IoT Devices
    Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. 13th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2018. <www.lirmm.fr/DTIS18/>
  10. Does stream cipher-based scan chains encryption really prevent scan attacks?
    Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    TRUDEVICE Workshop, Mar 2018, Dresden, Germany. Trustworthy Manufacturing and Utilization of Secure Devices, W05, 2018. <https://www.date-conference.com/date18/conference/workshop-w05>

2017

  1. An Advanced Diagnosis Flow for SRAMs
    Arnaud Virazel, Tien Phu Ho, Alberto Bosio
    ISTFA: International Symposium for Testing and Failure Analysis, Nov 2017, Pasadena, United States. 43rd International Symposium for Testing and Failure Analysis, 2017. <https://www.asminternational.org/web/istfa-2017>
  2. Improvement of the tolerated raw bit-error rate in NAND Flash-based SSDs with the help of embedded statistics
    Valentin Gherman, Emna Farjallah, Jean-Marc Armani, Marcelino Seif, Luigi Dilillo
    ITC: International Test Conference, Oct 2017, Fort Worth, United States. 48th International Test Conference, 2017, ITC Proceedings. <10.1109/TEST.2017.8242066>
  3. Towards digital circuit approximation by exploiting fault simulation
    Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
    EWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. IEEE, 15th IEEE East-West Design & Test Symposium, 2017. <10.1109/EWDTS.2017.8110108>
  4. Reliability of computing systems: from flip flops to variables
    Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Regis Leveugle
    IOLTS: International On-Line Testing and Robust System Design Symposium, Jul 2017, Thessaloniki, Greece. 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017, Proceedings. <10.1109/IOLTS.2017.8046242>
  5. Reliability of computing systems: From flip flops to variables
    Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Regis Leveugle
    IOLTS: International On-Line Testing and Robust System Design, Jul 2017, Thessaloniki, Greece. IEEE, 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017. <10.1109/IOLTS.2017.8046242>
  6. Test and reliability in approximate computing
    Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Elena Ioana Vatajelu
    IMSTW: International Mixed-Signal Testing Workshop, Jul 2017, Thessaloniki, Greece. 22nd International Mixed-Signal Testing Workshop, 2017. <10.1109/IMS3TW.2017.7995210>
  7. Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology
    Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, Keshav Singh
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2017, Bochum, Germany. IEEE, IEEE International Symposium on Very Large Scale Integration, 2017. <10.1109/ISVLSI.2017.63>
  8. Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories
    Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    IEEE. IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. IEEE, IEEE 2nd International Verification and Security Workshop, pp.128-133, 2017, Proceedings.
  9. Hacking the Control Flow error detection mechanism
    Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
    IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. IEEE, 2nd IEEE International Verification and Security Workshop, 2017. <10.1109/IVSW.2017.8031544>
  10. Experimentations on scan chain encryption with PRESENT
    Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. IEEE, 2nd IEEE International Verification and Security Workshop, 2017. <10.1109/IVSW.2017.8031543>
  11. Analytical Study of On-chip Generations of Analog Sine-wave Based on Combined Digital Signals
    Stéphane David-Grignot, Achraf Lamlih, Vincent Kerzérho, Florence Azaïs, Fabien Soulier, Serge Bernard
    IMSTW: International Mixed Signals Testing Workshop, Jul 2017, Thessaloniki, Greece. IEEE, 22nd IEEE International Mixed Signals Testing Workshop, 2017. <10.1109/IMS3TW.2017.7995205>
  12. IDEFI-FINMINA: a French educative project for the awareness, innovation and multidisciplinarity in microelectronics
    Olivier Bonnaud, Ahmad Bsiesy, Laurent Fesquet, Beatrice Pradarelli
    27th European Association for Education in Electrical and Information Engineering Annual Conference (EAEEIE 2017), Jun 2017, Grenoble, France.
  13. Detection of resistive open and short defects in FDSOI under delay-based test: Optimal V<inf>DD</inf> and body biasing conditions
    Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Galliere, Michel Renovell, Keshav Singh
    cts in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS: European Test Symposium, May 2017, Limassol, Cyprus. IEEE, 22nd IEEE European Test Symposium, 2017. <10.1109/ETS.2017.7968208>
  14. Mitigating Read & Write Errors in STT-MRAM Memories under DVS
    Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras
    ETS: European Test Symposium, May 2017, Limassol, Cyprus. IEEE, 22nd IEEE European Test Symposium, 2017. <10.1109/ETS.2017.7968209>
  15. Scan chain encryption for the test, diagnosis and debug of secure circuits
    Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo
    ETS: European Test Symposium, May 2017, Limassol, Cyprus. IEEE, 22nd IEEE European Test Symposium, 2017. <10.1109/ETS.2017.7968248>
  16. Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps
    Marcelino Seif, Emna Farjallah, Franck Badets, Christophe Layer, Jean-Marc Armani, Francis Joffre, Costin Anghel, Valentin Gherman, Luigi Dilillo
    ETS: European Test Symposium, May 2017, Limassol, Cyprus. IEEE, 22nd IEEE European Test Symposium, pp.1-6, 2017.
  17. Do we need a holistic approach for the design of secure IoT systems?
    Mauro Contini, Giorgio Di Natale, Annelie Heuser, Thomas Poppelmann, Nele Mentens
    Computing Frontiers Conference, May 2017, Siena, Italy. ACM International Conference on Computing Frontiers, 2017. <http://www.computingfrontiers.org/2017/>
  18. Combo of innovative educational approaches to teach industrial test to undergraduate students
    Beatrice Pradarelli, Pascal Nouet, Laurent Latorre
    EDUCON: Global Engineering Education Conference, Apr 2017, Athens, Greece. IEEE, 8th IEEE Global Engineering Education Conference, 2017. <10.1109/EDUCON.2017.7942824>
  19. Towards approximation during test of Integrated Circuits
    Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. IEEE, 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2017. <10.1109/DDECS.2017.7934574>
  20. Memristive devices: Technology, Design Automation and Computing Frontiers
    Mario Barbareschi, Alberto Bosio, Hoang Anh Du Nguyen, Said Hamdioui, Marcello Traiola, Elena Ioana Vatajelu
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. Academic Press, London, UK, 12th International Conference on Design Technology of Integrated Systems In Nanoscale Era, pp.1-8, 2017.
  21. An effective fault-injection framework for memory reliability enhancement perspectives
    Ghita Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. IEEE, 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017. <10.1109/DTIS.2017.7930172>
  22. Approximate computing: Design & test for integrated circuits
    Arnaud Virazel, Alberto Bosio, Patrick Girard, Mario Barbareschi
    LATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. IEEE, 18th IEEE Latin American Test Symposium, 2017. <10.1109/LATW.2017.7906737>
  23. Analysis of short defects in FinFET based logic cells
    Freddy Forero, Jean-Marc Galliere, Michel Renovell, Víctor Champac
    LATS: Latin American Test Symposium, Mar 2017, Bogota, Colombia. IEEE, 18th IEEE Latin American Test Symposium, 2017. <10.1109/LATW.2017.7906755>

2016

  1. Test of Low Power Circuits: Issues and Industrial Practices
    Alberto Bosio, Patrick Girard, Arnaud Virazel
    ICECS: International Conference on Electronics, Circuits and Systems, Dec 2016, Monte Carlo, Monaco. 23rd IEEE International Conference on Electronics, Circuits and Systems, 2016. <http://icecs.isep.fr>
  2. SCHIFI: Scalable and flexible high performance FPGA-based fault injector
    Suman Sau, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Amlan Chakrabarti
    DCIS: Design of Circuits and Integrated Systems, Nov 2016, Granada, Spain. IEEE, 31st International Conference on Design of Circuits and Integrated Systems, 2016. <10.1109/DCIS.2016.7845375>
  3. Cross-layer system reliability assessment framework for hardware faults
    Alessandro Vallero, Alessandro Savino, Gianfranco Michele Maria Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Sotiris Tselonis, Marc Riera Villanueva, Ramon Canal, Antonio Gonzalez, Maha Kooli, Alberto Bosio, Giorgio Di Natale
    ITC: International Test Conference, Nov 2016, Fort Worth, TX, United States. IEEE, IEEE International Test Conference, 2017. <10.1109/TEST.2016.7805863>
  4. Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits
    Manikandan Palanichamy, Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    TRUDEVICE, Nov 2016, Barcelona, Spain. 5th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, 2016. <https://trudevice2016.eel.upc.edu/>
  5. True random number generator based on nanomagnets
    Luca Gnoli, Matteo Bollo, Marco Vacca, Mariagrazia Graziano, Giorgio Di Natale
    NMDC: Nanotechnology Materials and Devices Conference, Oct 2016, Toulouse, France. 11th IEEE Nanotechnology Materials and Devices Conference, 2016. <10.1109/NMDC.2016.7777089>
  6. Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs
    Paolo Bernardi, Alberto Bosio, Giorgio Natale, Andrea Guerriero, Ernesto Sanchez, Federico Venini
    Thomas Hollstein; Jaan Raik; Sergei Kostin; Anton Tšertov; Ian O'Connor; Ricardo Reis. VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, Sep 2016, Tallinn, Estonia. Springer International Publishing, 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip, AICT-508, pp.130-151, 2017, IFIP Advances in Information and Communication Technology.
  7. A Hybrid Power Estimation Technique to improve IP power models quality
    Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
    VLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallin, Estonia. 24th IFIP/IEEE International Conference on Very Large Scale Integration, 2016. <10.1109/VLSI-SoC.2016.7753582>
  8. Faster-than-at-speed execution of functional programs: An experimental analysis
    Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico Venini
    VLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallinn, Estonia. 24th IFIP/IEEE International Conference on Very Large Scale Integration, 2016. <10.1109/VLSI-SoC.2016.7753581>
  9. Mixed-level simulation tool for design optimization of electrical impedance spectroscopy systems
    Achraf Lamlih, Vincent Kerzérho, Serge Bernard, Fabien Soulier, Mariane Comte, Michel Renovell, Tristan Rouyer, Sylvain Bonhommeau
    IWIS: International Workshop on Impedance Spectroscopy, Sep 2016, Chemnitz, Germany. Session: Bioimpedance Spectroscopy II (N012). <https://www.tu-chemnitz.de/etit/messtech/iwis/openconf/modules/request.php?module=oc_program&action=program.php>
  10. Problem-Based Learning Approach to Teach Printed Circuit Boards Test
    Beatrice Pradarelli, Pascal Nouet, Laurent Latorre
    ICL: Interactive Collaborative Learning, Sep 2016, Belfast, United Kingdom. 19th International Conference on Interactive Collaborative Learning, 2016. <http://www.icl-conference.org/icl2016/>
  11. Investigation on the Sensitivity of a 65nm Flash-Based FPGA for CERN Applications
    Georgios Tsiligiannis, Rudy Ferraro, Salvatore Danzeca, Alessandro Masi, Markus Brugger, Frédéric Saigné
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2016, Brême, Germany. 16th European Conference on Radiation and Its Effects on Components and Systems, 2016. <10.1109/RADECS.2016.8093209>
  12. Comparison of the Effects of Muon and Low-Energy Proton Irradiation on a 65 nm Low-Power SRAM
    Alexandre Bosser, Viyas Gupta, Arto Javanainen, Georgios Tsiligiannis, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Ari Virtanen, Luigi Dilillo
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2016, Bremen, Germany. 16th European Conference on Radiation and Its Effects on Components and Systems, 2016. <http://www.radecs2016.com/joomla/>
  13. Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study
    Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, PA, United States. IEEE, VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, pp.731-736, 2016.
  14. The Power Law Shape of Heavy Ions Experimental Cross Section
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Eric Lorfèvre, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2016, Portland, United States. IEEE, 2016. <http://www.nsrec.com/>
  15. Impact of VT and Body-Biasing on Resistive short detection in 28nm UTBB FDSOI – LVT and RVT configurations
    Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, United States. Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’16), 2016. <10.1109/ISVLSI.2016.102>
  16. Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique
    Papa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, United States. 2016. <10.1109/ISVLSI.2016.22>
  17. Towards Model Driven Design of Crypto Primitives and Processes
    Alberto Carelli, Giorgio Di Natale, Pascal Trotta, Tiziana Margaria
    SAM: Sensor Array and Multichannel Signal Processing, Jul 2016, Rio de Janeiro, Brazil. CSREA Press, 9th IEEE Sensor Array and Multichannel Signal Processing Workshop (SAM), pp.152-158, 2016.
  18. Cache-aware reliability evaluation through LLVM-based analysis and fault injection
    Maha Kooli, Giorgio Di Natale, Alberto Bosio
    IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), pp.19-22, 2016.
  19. Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models
    Mojtaba Ebrahimi, Maryam Rashvand, Firas Kaddachi, Mehdi B. Tahoori, Giorgio Di Natale
    IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), pp.66-71, 2016.
  20. STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation
    Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    IOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2016. <10.1109/IOLTS.2016.7604694>
  21. Using Outliers to Detect Stealthy Hardware Trojan Triggering?
    Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France. IEEE International Verification and Security Workshop, 2016.
  22. MTCube project: COTS memory SEE ground-test results and in-orbit error rate prediction
    Viyas Gupta, Alexandre Bosser, Frédéric Wrobel, Frédéric Saigné, Laurent Dusseau, Ali Mohammadzadeh, Luigi Dilillo
    4S: Small Satellites Systems and Services Symposium, May 2016, La Valletta, Malta. 2016. <http://congrexprojects.com/4S2016/home>
  23. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits
    Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
    ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. 21th IEEE European Test Symposium, 2016. <10.1109/ETS.2016.7519296>
  24. Behavior and test of open-gate defects in FinFET based cells
    Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor Champac
    ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. IEEE, 21th IEEE European Test Symposium, 2016. <10.1109/ETS.2016.7519305>
  25. Per Peers Learning Education Approach to Teach Industrial Test to Undergraduate Students
    Beatrice Pradarelli, Pascal Nouet, Laurent Latorre
    EWME: European Workshop on Microelectronics Education, May 2016, Southampton, United Kingdom. 11th European Workshop on Microelectronics Education, 2016. <http://ewme2016.ecs.soton.ac.uk>
  26. Thermal issues in test: An overview of the significant aspects and industrial practice
    Juergen Alt, Paolo Bernardi, Alberto Bosio, Ricardo Cantoro, Hans Kerkhoff, Andreas Leininger, Wolfgang Molzer, Allessandro Motta, Christian Pacha, Alberto Pagani, Alireza Rohani, Rudolf Strasser
    VTS: VLSI Test Symposium, Apr 2016, Las Vegas, NV, United States. IEEE, IEEE 34th VLSI Test Symposium, 2016. <10.1109/VTS.2016.7477278>
  27. Security primitives (PUF and TRNG) with STT-MRAM
    Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    IEEE. VTS: VLSI Test Symposium, Apr 2016, Las Vegas, United States. 34th IEEE VLSI Test Symposium, 2016. <10.1109/VTS.2016.7477292>
  28. Cache- and register-aware system reliability evaluation based on data lifetime analysis
    Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio
    VTS: VLSI Test Symposium , Apr 2016, Las Vegas, United States. 34th IEEE VLSI Test Symposium, 2016. <10.1109/VTS.2016.7477299>
  29. System-level reliability evaluation through cache-aware software-based fault injection
    Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, Mehdi B. Tahoori
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016. <10.1109/DDECS.2016.7482446>
  30. An effective approach for functional test programs compaction
    Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2016. <10.1109/DDECS.2016.7482466>
  31. A hybrid power modeling approach to enhance high-level power models
    Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, 19th International Symposium on Design and Diagnostics of Electronic Circuits Systems, 2016. <10.1109/DDECS.2016.7482453>
  32. Auto-adaptive ultra-low power IC
    Alberto Bosio, Philippe Debaud, Patrick Girard, Stéphane Guilhot, Miroslav Valka, Arnaud Virazel
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. IEEE, 11th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016. <10.1109/DTIS.2016.7483886>
  33. SEcube™: An open-source security platform in a single SoC
    Antonio Varriale, Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Pascal Trotta, Tiziana Margaria
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. IEEE, 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2016. <10.1109/DTIS.2016.7483810>
  34. Industrial Test Project Oriented Education
    Beatrice Pradarelli, Pascal Nouet, Laurent Latorre
    EDUCON: Global Engineering Education Conference, Apr 2016, Abu Dhabi, United Arab Emirates. IEEE, 2016. <http://www.educon-conference.org/educon2016/index.php>
  35. Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes
    Deepak Kumar Arora, Darayus Adil Patel, Nc Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio
    ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. 17th International Symposium & Exhibits on Quality Electronic Desgn, pp.295-300, 2016.
  36. An effective BIST architecture for power-gating mechanisms in low-power SRAMs
    Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo B. Zordan
    ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. IEEE, 17th International Symposium on Quality Electronic Design, pp.185-191, 2016.
  37. Towards a Highly Reliable SRAM-based PUFs
    Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    EDA Consortium. DATE: Design, Automation and Test in Europe, Mar 2016, Dresden, Germany. 19th DATE conference and exhibition, 2016. <https://www.date-conference.com/proceedings-archive/2016/>
  38. Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect
    Amit Karel, Mariane Comte, Jean-Marc Galliere, Florence Azaïs, Michel Renovell
    LATS: Latin-American Test Symposium, Mar 2016, Foz do Iguacu, Brazil. 17th IEEE Latin-American Test Symposium, pp.129-134, 2016.

2015

  1. An efficient hybrid power modeling approach for accurate gate-level power estimation
    Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
    ICM: International Conference on Microelectronics, Dec 2015, Casablanca, Morocco. 27th International Conference on Microelectronics, pp.17-20, 2015.
  2. Validation Of Single BBICS Architecture In Detecting Multiple Faults
    Raphael Andreoni Camponogara-Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    ATS: Asian Test Symposium, Nov 2015, Mumbai, India. 24th IEEE Asian Test Symposium, 2015. <https://www.ee.iitb.ac.in/ats15/>
  3. An Experimental Comparative Study of Fault-Tolerant Architectures
    Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard
    VALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. IARIA XPS Press, 7th International Conference on Advances in System Testing and Validation Lifecycle, pp.1-6, 2015.
  4. Exploiting the Variability of the Magnetic Tunnel Junction for Security Purposes
    Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    e-NVM: Leading Edge Embedded NVM, Sep 2015, Gardanne, France. 2015.
  5. Ring Oscillators Analysis for FPGA Security Purposes
    Mario Barbareschi, Lionel Torres, Giorgio Di Natale
    TRUDEVICE Workshop, Sep 2015, St Malo, France. Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, 2015.
  6. Hierarchical Secure DfT
    Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    TRUDEVICE Workshop, Sep 2015, St Malo, France. 4th Workshop on Secure Hardware and Security Evaluation, 2015.
  7. Multi-segment Enhanced Scan-chains for Secure ICs
    Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ilia Polian
    TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. 4th Workshop on Secure Hardware and Security Evaluation, 2015.
  8. Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology
    Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. 2015.
  9. SEcubeTM: The most advanced, Open Source Security Platform in a Single Chip
    Antonio Varriale, Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto, Tiziana Margaria
    TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. 4th Workshop on Secure Hardware and Security Evaluation, 2015.
  10. Zero Bit-Error-Rate Weak PUF based on Spin-Transfer-Torque MRAM Memories
    Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
    TRUDEVICE Workshop, Sep 2015, Saint-Malo, France. 4th Workshop on Secure Hardware and Security Evaluation, 2015.
  11. Proton-Induced SDRAM Cell Degradation
    Axel Rodriguez, Frédéric Wrobel, Anne Samaras, Francoise Bezerra, Benjamin Vandevelde, Robert Ecoffet, Antoine Touboul, Nathalie Chatry, Luigi Dilillo, Frédéric Saigné
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. 15th European Conference on Radiation and Its Effects on Components and Systems, 2015. <10.1109/RADECS.2015.7365650>
  12. Heavy-ion radiation impact on a 4Mb FRAM under Different Test Conditions
    Viyas Gupta, Alexandre Bosser, Georgios Tsiligiannis, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi Dilillo
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. 15th European Conference on Radiation and Its Effects on Components and Systems, 2015. <10.1109/RADECS.2015.7365617>
  13. A Methodology for the Analysis of Memory Response to Radiation through Bitmap Superposition and Slicing
    Alexandre Bosser, Viyas Gupta, Georgios Tsiligiannis, Rudy Ferraro, Christopher Frost, Ali Mohammadzadeh, Arto Javanainen, Helmut Puchner, Mario Rossi, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi Dilillo
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2015, Moscou, Russia. 15th European Conference on Radiation and Its Effects on Components and Systems, 2015. <10.1109/RADECS.2015.7365578>
  14. Hardware Trojan Prevention using Layout-Level Design Approach
    Papa-Sidy Ba, Palanichamy Manikandan, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    IEEE. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. Proceedings of the 2015 European Conference on Circuit Theory and Design (ECCTD). <10.1109/ECCTD.2015.7300093>
  15. Generic Analytic Expression of Heavy Ion SEU Cross Section Derived from Monte-Carlo Diffusion-Based Prediction Code
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Robert Ecoffet, Eric Lorfèvre, Francoise Bezerra, Markus Brugger, Ruben Garcia Alia, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2015, Boston, United States. 2015, 2015 IEEE Nuclear & Space Radiation Effects Conference (NSREC 2015). <http://www.nsrec.com/2015Brochure.pdf>
  16. Investigation on MCU Clustering Methodologies for Cross-Section Estimation of SRAMs
    Alexandre Bosser, Viyas Gupta, Arto Javanainen, Heikki Kettunen, Helmut Puchner, Frédéric Saigné, Ari Virtanen, Frédéric Wrobel, Luigi Dilillo
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2015, Boston, United States. IEEE, 2015, IEEE Nuclear and Space Radiation Effects Conferencee, Boston, USA, 2015. <http://www.nsrec.com/2015Brochure.pdf>
  17. Impact of Stacked-Layer Structure on SEE Rate of SRAMs
    Viyas Gupta, Alexandre Bosser, Georgios Tsiligiannis, Ali Mohammadzadeh, Arto Javanainen, Ari Virtanen, Helmut Puchner, Frédéric Saigné, Frédéric Wrobel, Luigi Dilillo
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2015, Boston, United States. 2015.
  18. Toward adaptation of ADCs to operating conditions through on-chip correction
    Vincent Kerzérho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’15), pp.634-639, 2015.
  19. A framework for efficient implementation of analog/RF alternate test with model redundancy
    Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. IEEE, Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’15), pp.621-626, 2015.
  20. STT-MRAM-Based Strong PUF Architecture
    Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo Prinetto
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.467-472, 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
  21. Digital Right Management for IP Protection
    Jerome Rampon, Renaud Perillat, Lionel Torres, Pascal Benoit, Giorgio Di Natale, Mario Barbareschi
    ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.200-203, 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
  22. An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern
    Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.515-520, 2015.
  23. 3D DFT Challenges and Solutions
    Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.603-608, Proceedings of 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
  24. Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits
    Stephan De Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). <10.1109/ISVLSI.2015.76>
  25. Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture
    Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
    IOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International, pp.89-94, 2015.
  26. A generic methodology for building efficient prediction models in the context of alternate testing
    Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    IMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. IEEE, 2015, Mixed-Signal Testing Workshop (IMSTW), 2015 20th International. <10.1109/IMS3TW.2015.7177873>
  27. Digital on-chip measurement circuit for built-in phase noise testing
    Stéphane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre
    IMSTW: International Mixed-Signals Test Workshop, Jun 2015, Paris, France. IEEE, 2015, Mixed-Signal Testing Workshop (IMSTW), 2015 20th International. <10.1109/IMS3TW.2015.7177880>
  28. Real-Time SRAM Based Particle Detector
    Luigi Dilillo, Alexandre Bosser, Viyas Gupta, Frédéric Wrobel, Frédéric Saigné
    IWASI: International Workshop on Advances in Sensors and Interfaces, Jun 2015, Gallipoli, Italy. Proceeding IWASI 2015: 6th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), pp.58-62, 2015.
  29. Une pedagogie par projet pour des etudiants acteurs et auteurs de leur apprentissage
    Beatrice Pradarelli, Pascal Nouet, Laurent Latorre
    QPES: Questions de Pédagogie dans l’Enseignement Supérieur, Jun 2015, Brest, France. 2015. <http://www.colloque-pedagogie.org/?q=node/5>
  30. A New Technique for Low-Cost Phase Noise Production Testing from 1-bit Signal Acquisition
    Stéphane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. IEEE, Proc. IEEE European Test Symposium 2015 (ETS'15), pp.1-6, 2015.
  31. An effective hybrid fault-tolerant architecture for pipelined cores
    Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. 20th IEEE European Test Symposium, pp.1-6, 2015.
  32. Session-less based thermal-aware 3D-SIC test scheduling
    Marie-Lise Flottes, João Azevedo, Giorgio Di Natale, Bruno Rouzeyre
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. IEEE, 20th IEEE European Test Symposium, 2015. <10.1109/ETS.2015.7138732>
  33. Analog test: Why still “à la mode” after more than 25 years of research?
    Florence Azaïs
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. IEEE, 20th IEEE European Test Symposium, 2015. <10.1109/ETS.2015.7138772>
  34. Power-aware voltage tuning for STT-MRAM reliability
    Elena Ioana Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
    ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. IEEE, 20th IEEE European Test Symposium, 2015. <10.1109/ETS.2015.7138748>
  35. Challenges in Designing Trustworthy Cryptographic Co-Processors
    Ricardo Chaves, Giorgio Di Natale, Lejla Batina, Shivam Bhasin, Baris Ege, Apostolos Fournaris, Nele Mentens, Stjepan Picek, Francesco Regazzoni, Vladimir Rozic, Nicolas Sklavos, Bohan Yang
    ISCAS: International Symposium on Circuits and Systems, May 2015, Lisbon, Portugal. Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2009-2010, 2015.
  36. Special session: Hot topics: Statistical test methods
    Manuel J. Barragan, Gildas Leger, Florence Azaïs, R. D. Blanton, Adit D. Singh, Stephen Sunter
    VTS: VLSI Test Symposium, Apr 2015, Napa, CA, United States. IEEE Computer Society, 33rd IEEE VLSI Test Symposium, 2015. <10.1109/VTS.2015.7116265>
  37. Embedded test instrument for on-chip phase noise evaluation of analog/IF signals
    Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. IEEE, Proc. of the 18th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15), pp.237-242, 2015.
  38. Design-for-Diagnosis Architecture for Power Switches
    Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48, 2015.
  39. Software testing and software fault injection
    Maha Kooli, Alberto Bosio, Pascal Benoit, Lionel Torres
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015. <10.1109/DTIS.2015.7127370>
  40. Scan-chain intra-cell defects grading
    Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. Design Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, pp.1-6, 2015.
  41. An effective ATPG flow for Gate Delay Faults
    Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. Design Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, pp.1-6, 2015.
  42. On the limitations of logic testing for detecting Hardware Trojans Horses
    Marie-Lise Flottes, Sophie Dupuis, Papa-Sidy Ba, Bruno Rouzeyre
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. IEEE, Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, 2015. <10.1109/DTIS.2015.7127362>
  43. Statistical Energy Study for 28nm FDSOI Devices
    Kheirallah Rida, Jean-Marc Galliere, Aida Todri-Sanial, Gilles Ducharme, Nadine Azemard
    EuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2015, Budapest, Hungary. Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2015 16th International Conference on, 2015. <10.1109/EuroSimE.2015.7103149>
  44. Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology
    Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
    ISQED: International Symposium on Quality Electronic Design, Apr 2015, Santa Clara, United States. Quality Electronic Design (ISQED), 2015 16th International Symposium on, pp.366-370, 2015.
  45. A digital technique for the evaluation of SSB phase noise of analog/RF signals
    Florence Azaïs, Stéphane David-Grignot, François Lefevre, Laurent Latorre
    LATS: Latin-American Test Symposium, Mar 2015, Puerto Vallarta, Mexico. IEEE, 2015, Test Symposium (LATS), 2015 16th Latin-American. <10.1109/LATW.2015.7102407>
  46. Ring Oscillators Analysis for FPGA Security Purposes
    Mario Barbareschi, Giorgio Di Natale, Florent Bruguier, Pascal Benoit, Lionel Torres
    TRUDEVICE Workshop, Mar 2015, Grenoble, France. Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, W10, 2015.
  47. STT MRAM-Based PUFs
    Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo Prinetto
    DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 978-3-9815-3704-8, pp.872-875, 2015.
  48. Exploring the impact of functional test programs re-used for power-aware testing
    Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
    DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.1277-1280, 2015.
  49. New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans
    Sophie Dupuis, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Papa-Sidy Ba
    DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. IEEE, 2015.

2014

  1. On the Generation of Diagnostic Test Set for Intra-cell Defects
    Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray
    ATS: Asian Test Symposium, Nov 2014, Hangzhou, China. Test Symposium (ATS), 2014 IEEE 23rd Asian, pp.312-317, 2014.
  2. Low-cost phase noise testing of complex RF ICs using standard digital ATE
    Stephane David-Grignot, Florence Azaïs, Laurent Latorre, François Lefevre
    ITC: International Test Conference, Oct 2014, Seattle, WA, United States. IEEE, 2014. <10.1109/TEST.2014.7035301>
  3. TRUDEVICE Project: Trustworthy Manufacturing and Utilization of Secure Devices
    Nicolas Sklavos, Giorgio Di Natale
    HiPEAC Computing Systems Week (CSW), Oct 2014, Athens, Greece. 2014. <https://www.hipeac.net/csw/2014/athens/>
  4. Laser-Induced Fault Effects in Security-Dedicated Circuits
    Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hely, Guillaume Hubert, Régis Leveugle, Lu Feng, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clement Tavernier, Pierre Vanhauwaert
    Luc Claesen; Maria-Teresa Sanz-Pascual; Ricardo Reis; Arturo Sarmiento-Reyes. VLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, AICT-464, pp.220-240, 2015, IFIP Advances in Information and Communication Technology.
  5. MRAM-based PUF
    Giorgio Di Natale, Paolo Prinetto, Ioana Vatajelu
    Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands.
  6. Secure Test Method for Fuzzy Extractor
    Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale
    Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. 2014.
  7. Multi-stage Cross-layer Hardware Trojan Prevention, Detection and Tolerance
    Cristiana Bolchini, Luca Cassano, Giorgio Di Natale
    Joint MEDIAN-TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. 2014.
  8. Stochastic model for phase noise measurement from 1-bit signal acquisition
    Stephane David-Grignot, Florence Azaïs, François Lefevre, Laurent Latorre
    IMS3TW'14: International Mixed-Signals, Sensors, and Systems Test Workshop, Sep 2014, Porto Alegre, Brazil. IEEE, pp.1-6.
  9. Study of adaptive tuning strategies for Near Field Communication (NFC) transmitter module
    Mouhamadou Dieng, Florence Azaïs, Mariane Comte, Serge Bernard, Vincent Kerzérho, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-Conti
    IMS3TW'14: International Mixed-Signals, Sensors, and Systems Test Workshop, Sep 2014, Porto ALegre, Brazil. IEEE, pp.1-6.
  10. Cross-Layer Early Reliability Evaluation for the Computing Continuum
    Stefano Di Carlo, Alessandro Vallero, Dirnitris Gizopoulos, Giorgio Di Natale
    IEEE. DSD: Digital System Design, Aug 2014, Verona, Italy. 978-1-4799-5793-4/14, pp.199-205, 2014, Digital System Design (DSD), 2014 17th Euromicro Conference on.
  11. Real-Time Testing of 90nm COTS SRAMs at Concordia Station in Antarctica
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Philippe Cocquerez, Jean-Luc Autran, Antonio Litterio, Frédéric Wrobel, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. IEEE Nuclear & Space Radiation Effects Conference (NSREC 2014), 2014. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
  12. Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude Vs. Underground Experiments, Modeling and Numerical Monte Carlo Simulation
    Tarek Saad Saoud, Soilihi Moindjie, Jean-Luc Autran, Daniela Munteanu, Frédéric Wrobel, Frédéric Saigné, Philippe Cocquerez, Luigi Dilillo
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. IEEE Nuclear & Space Radiation Effects Conference (NSREC 2014), 2014. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
  13. Single Event Upset Prediction from Heavy Ions Cross Sections with No Parameters
    Frédéric Wrobel, Antoine Touboul, Vincent Pouget, Luigi Dilillo, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. IEEE Nuclear & Space Radiation Effects Conference (NSREC 2014), 2014. <http://ieee-npss.org/wp-content/uploads/2014/03/2014-NSREC.pdf>
  14. Efficient Dynamic Test Methods for COTS SRAMs Under Heavy Ion Irradiation
    Georgios Tsiligiannis, Luigi Dilillo, Viyas Gupta, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Helmut Puchner, Alexandre Bosser, Arto Javanainen, Ari Virtanen, Frédéric Wrobel, Laurent Dusseau, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France. IEEE Nuclear & Space Radiation Effects Conference (NSREC 2014), 2014.
  15. A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise
    Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2014, Tampa, FL, United States. VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on, pp.226-231, 2014.
  16. 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures
    Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2014, Tampa, Florida, United States. pp.386-391, 2014, Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
  17. Cross-Layer Early Reliability Evaluation: Challenges and Promises
    Stefano Di Carlo, Alessandro Vallero, Dimitris Gizopoulos, Giorgio Di Natale, Antonio Gonzales, Ramon Canal, Riccardo Mariani, Mauro Pipponzi, Arnaud Grasset, Philippe Bonnot, Frank Reichenback, Gulzaib Rafiw, Trond Loekstad
    IEEE. IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. 20th IEEE International On-Line Testing Symposium, pp.228-233, 2014.
  18. Solutions for the self-adaptation of communicating systems in operation
    Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzérho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G Stratigopoulos
    IOLTS: International International On-line Test Symposium, Jul 2014, Platja d’Aro, Spain. IEEE Computer Society, 20th International International On-line Test Symposium, pp.234-239, 2014.
  19. Self-Adaptive NFC Systems
    Vincent Kerzérho, Florence Azaïs, Mouhamadou Dieng, Mariane Comte, Serge Bernard, Michel Renovell, Paul-Henri Pugliesi-Conti, Thibault Kervaon
    IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. IEEE, 20th IEEE International On-Line Testing Symposium, 2014, Special Session 4 – Solutions for the self-adaptation of communicating systems in operation.
  20. Customized Cell Detector for Laser-Induced-Fault Detection
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    IOLTS: International On-Line Testing Symposium, Jul 2014, Girona, Spain. IEEE 20th International On-Line Testing Symposium, pp.37-42, 2014.
  21. A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans
    Sophie Dupuis, Papa-Sidy Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    IOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. IEEE, 20th International On-Line Testing Symposium, pp.49-54, 2014.
  22. Phase noise measurement on IF analog signals using standard digital ATE resources
    Stephane David-Grignot, Laurent Latorre, Florence Azaïs, François Lefevre
    NEWCAS: New Circuits and Systems, Jun 2014, Trois-Rivieres, Canada. IEEE, IEEE 12th International New Circuits and Systems Conference, pp.121-124, 2014.
  23. Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approach
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    TRUDEVICE Workshop, May 2014, Paderborn, Germany. TRUDEVICE Workshop on Test and Fault Tolerance for Secure Devices, 2014. <http://www.ets14.de/media/PDFs/workshops/TRUDEVICE-ETS14-PreliminaryProgam>
  24. Investigations on alternate analog/RF test with model redundancy
    Haithem Ayari, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Syhem Larguech, Mariane Comte, Michel Renovell
    STEM Workshop, May 2014, Paderborn, Germany. 1st Workshop on Statistical Test Methods, 2014. <http://www.ets14.de/pages/workshops/stem-workshop.php>
  25. A novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMR
    Luca Cassano, Alberto Bosio, Giorgio Di Natale
    ETS: European Test Symposium, May 2014, Paderborn, Germany. IEEE, 978-1-4799-3415-7/14, 2014, 19th IEEE European Test Symposium (ETS 2014). <10.1109/ETS.2014.6847831>
  26. iBoX — Jitter based Power Supply Noise sensor
    Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel, Patrick Girard, Philippe Debaud, Stephane Guilhot
    ETS: European Test Symposium, May 2014, Paderborn, United States. Test Symposium (ETS), 2014 19th IEEE European, pp.1-2, 2014.
  27. Fault injection tools based on Virtual Machines
    Kooli Maha, Giorgio Di Natale, Pascal Benoit, Alberto Bosio, Lionel Torres, Volkmar Sieh
    ReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. 2014, Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on. <10.1109/ReCoSoC.2014.6861351>
  28. Presentation of the MTCube CubeSat Project
    Viyas Gupta, Luigi Dilillo, Frédéric Wrobel, Ali Mohammadzadeh, Georgios Tsiligiannis, Muriel Bernard, Laurent Dusseau
    4S: Small Satellites Systems and Services Symposium, May 2014, Majorca, Spain. 2014. <http://congrexprojects.com/2014-events/4S2014/home>
  29. Radiation Study of a 4Mbit Ferroelectric RAM for Space Applications
    Helmut Puchner, Georgios Tsiligiannis, Luigi Dilillo
    SEE: Single Event Effects, May 2014, San Diego, United States. 2014. <http://radhome.gsfc.nasa.gov/radhome/see_mapld/2014/index.cfm>
  30. A Comprehensive Evaluation of Functional Programs for Power-Aware Test
    Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi
    NATW: North Atlantic Test Workshop, May 2014, Johnson City, NY, United States. IEEE, Test Workshop (NATW), 2014 IEEE 23rd North Atlantic, pp.69-72, 2014.
  31. Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate level
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. IEEE, 9th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2014. <10.1109/DTIS.2014.6850665>
  32. A survey on simulation-based fault injection tools for complex systems
    Kooli Maha, Giorgio Di Natale
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorini, Greece. 2014, Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2014 9th IEEE International Conference On. <10.1109/DTIS.2014.6850649>
  33. Laser attacks on integrated circuits: from CMOS to FD-SOI
    Jean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, Mathieu Lisart, Joel Damiens, Philippe Candelier, Marie-Lise Flottes, Giorgio Di Natale
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014. <10.1109/DTIS.2014.6850664>
  34. Timing-aware ATPG for critical paths with multiple TSVs
    Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.116-121, 2014.
  35. Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults
    Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pp.223-225, 2014.
  36. Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce
    Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.207-212, 2014.
  37. Test and diagnosis of power switches
    Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel, Patrick Girard, Philippe Debaud, Stephane Guilhot
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pp.213-218, 2014.
  38. An intra-cell defect grading tool
    Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Stefano Bernabovi, Paolo Bernardi
    DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.298-301, 2014.
  39. TSV aware timing analysis and diagnosis in paths with multiple TSVs
    Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Apr 2014, Napa, CA, United States. VLSI Test Symposium (VTS), 2014 IEEE 32nd, pp.1-6, 2014.
  40. Built-In Self-Test for Manufacturing TSV Defects before bonding
    Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche
    IEEE. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. 32nd IEEE VLSI Test Symposium (VTS) pp.1-6, 2014.
  41. Hacking and Protecting IC Hardware
    Said Hamdioui, Giorgio Di Natale, Battum Van, Jean-Luc Danger, Fethulah Smailbegovic, Mark Tehranipoor
    DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. 978-3-9815370-2-4/DATE14, pp.1-7, 2014, Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014.
  42. Testing PUF-Based Secure Key Storage Circuits
    Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale
    DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. pp.1-6, 2014, Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014.
  43. New implementions of predictive alternate analog/RF test with augmented model redundancy
    Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, Michel Renovell
    DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. 2014. <10.7873/DATE2014.144>
  44. Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing
    Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Mariane Comte, Michel Renovell
    LATW: Latin American Test Workshop, Mar 2014, Fortaleza, Brazil. 15th IEEE Latin American Test Workshop, pp.1-6, 2014.
  45. Experimental Heavy-Ion SEU Cross-Sections Of Sram Memory Components
    Alexandre Bosser, Luigi Dilillo, Viyas Gupta, Arto Javanainen, Heikki Kettunen, Mario Rossi, Georgios Tsiligiannis, Ari Virtanen
    Physics Days: Annual Meeting of the Finnish Physical Society, Mar 2014, Tampere, Finland. Physics Days 2014, the 48th Annual Meeting of the Finnish Physical Society, is organized in Tampere Hall - the largest congress center in Nordic countries - on March 11-13, 2014, 2014. <http://webhotel2.tut.fi/fys/physicsdays/>
  46. Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration
    Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    ASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. 19th Asia and South Pacific Design Automation Conference, 2014. <10.1109/ASPDAC.2014.6742948>
  47. Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration
    Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    ASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. pp.544-549, 2014, Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific.

2013

  1. A BIST Method for TSVs Pre-Bond Test
    Hakim Zimouche, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale
    IDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, 2013.
  2. MIRID: Mixed-Mode IR-Drop Induced Delay Simulator
    Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian
    ATS: Asian Test Symposium, Nov 2013, Jiaosi Township, Taiwan. 22nd Asian Test Symposium, pp.177-182, 2013.
  3. Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing
    Ioana Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Nabil Badereddine
    ATS: Asian Test Symposium, Nov 2013, Jiaosi Township, Taiwan. pp.109-114, 2013.
  4. Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive Defects
    João Azevedo, Arnaud Virazel, Yuanqing Cheng, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Hérault
    VALID: Advances in System Testing and Validation Lifecycle, Oct 2013, Venice, Italy. 5th International Conference on Advances in System Testing and Validation Lifecycle, pp.39-44, 2013.
  5. On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell
    Ioana Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Frédéric Wrobel, Frédéric Saigné
    DFT: Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2013, New York, United States. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, pp.143-148, 2013.
  6. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection
    Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale
    ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Sep 2013, Arcachon, France. IEEE Computer Society, 24th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, pp.B3c-2 #68, 2013.
  7. SEU Monitoring in Mixed-Field Radiation Environments of Particle Accelerators
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Frédéric Wrobel, Frédéric Saigné
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. 14th European Conference on Radiation and Its Effects on Components and Systems, pp.1-4, 2013.
  8. Comparison of the transient current shapes obtained with the diffusion model and the double exponential law — Impact on the SER
    Frédéric Wrobel, Luigi Dilillo, Antoine Touboul, Frédéric Saigné
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. 14th European Conference on Radiation and Its Effects on Components and Systems, 2013. <10.1109/RADECS.2013.6937441>
  9. Gate voltage contribution to neutron-induced SEB of Trench Gate Fieldstop IGBT
    Lionel Foro, Antoine Touboul, Frédéric Wrobel, Paolo Rech, Luigi Dilillo, Christopher Frost, Frédéric Saigné
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. 14th European Conference on Radiation and Its Effects on Components and Systems, 2013. <10.1109/RADECS.2013.6937428>
  10. Multiple-Cell-Upsets on a commercial 90nm SRAM in Dynamic Mode
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Christopher Frost, Frédéric Wrobel, Frédéric Saigné
    RADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. 14th European Conference on Radiation and Its Effects on Components and Systems, pp.1-4, 2013.
  11. Improving Defect Localization Accuracy by means of Effect-Cause Intra-Cell Diagnosis at Transistor Level
    Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Etienne Auvray
    SDD: Silicon Debug and Diagnosis, Sep 2013, Anaheim, CA, United States. 8th IEEE International Workshop on Silicon Debug and Diagnosis, 2013. <http://sdd.tttc-events.org/13/>
  12. TSVs Pre-Bond Testing: a test scheme for capturing BIST responses
    Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche
    3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. IEEE, 4th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits in conjunction with ITC / Test Week 2013 September 12-13, 2013 - Disneyland Hotel – Anaheim, California, USA, 2013. <http://www.pld.ttu.ee/3dtest/past_events/2013/>
  13. 3D Design For Test Architectures Based on IEEE P1687
    Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel
    3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. 4th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2013.
  14. A Comparative Analysis of Indirect Measurement Selection Strategies for Analog/RF Alternate Testing
    Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzérho, Mariane Comte, Michel Renovell
    3rd IEEE International Workshop on Test and Validation of High Speed Analog Circuits, Sep 2013, Anaheim, CA, United States. 2013.
  15. On the Reuse of Read and Write Assist Circuits to Improve Test Efficiency in Low-Power SRAMs
    Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Nabil Badereddine
    ITC: International Test conference, Sep 2013, Anaheim, CA, United States. pp.1-10, 2013.
  16. A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults
    Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.157-163, 2013.
  17. Laser-Induced Fault Simulation
    Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    EUROMICRO DSD/SEAA, Sep 2013, Santander, Spain. 16th Euromicro Conference on Digital System Design (DSD) & 39th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), pp.609-614, 2013.
  18. A novel method to mitigate TSV electromigration for 3D ICs
    Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
    ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. pp.121-126, 2013.
  19. SRAM Soft Error Rate Evaluation Under Atmospheric Neutron Radiation and PVT variations
    Georgios Tsiligiannis, Ioana Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Frédéric Wrobel, Frédéric Saigné
    IOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Crete, Greece. On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International, pp.145-150, 2013.
  20. Temperature Impact on the Neutron SER of a Commercial 90nm SRAM
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Christopher Frost, Frédéric Wrobel, Frédéric Saigné
    NSREC: Nuclear and Space Radiation Effects Conference, Jul 2013, San Francisco, Ca, United States. IEEE, pp.1-4, 2013.
  21. A smart test controller for scan chains in secure circuits
    Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    IOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Greece. 19th IEEE International On-Line Testing Symposium, pp.228-229, 2013.
  22. Mitigate TSV Electromigration for 3D ICs - From the Architecture Perspective
    Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
    International Symposium on VLSI, Natale, Brazil. pp.6, 2013.
  23. An Integrated Solid Detector For Onboard Detection Of Natural Radiations In Atmosphere
    Frédéric Wrobel, Jean-Roch Vaillé, Antoine Touboul, Luigi Dilillo, Frédéric Saigné
    iWoRID: International Workshop on Radiation Imaging Detectors, Jun 2013, Paris, France. 15th International Workshops on Radiation Imaging Detectors, 2013. <http://www.synchrotron-soleil.fr/Workshops/2013/IWORID2013>
  24. Evaluating An SEU Monitor For Mixed-Field Radiation Environments
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Frédéric Wrobel, Frédéric Saigné
    iWoRID: International Workshop on Radiation Imaging Detectors, Jun 2013, Paris, France. 15th International Workshops on Radiation Imaging Detectors, 2013. <http://www.synchrotron-soleil.fr/Workshops/2013/IWORID2013>
  25. Worst-Case Power Supply Noise and Temperature Distribution Analysis for 3D PDNs with Multiple Clock Domains
    Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
    NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. 11th International IEEE Conference on New Circuits and Systems, 2013. <10.1109/NEWCAS.2013.6573628>
  26. Accurate and Efficient Analytical Electrical Model of Antenna for NFC Applications
    Mouhamadou Dieng, Mariane Comte, Serge Bernard, Vincent Kerzérho, Florence Azaïs, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-Conti
    NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. IEEE, IEEE 11th International New Circuits and Systems Conference, pp.137-141, 2013.
  27. A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators
    Yassine Fkih, Pascal Vivet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. IEEE, 11th International International New Circuits and Systems Conference, pp.001-004, 2013.
  28. Characterization of an SRAM Based Particle Detector For Mixed-Field Radiation Environments
    Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, Jean-Roch Vaillé, Frédéric Wrobel, Frédéric Saigné
    IWASI: International Workshop on Advances in Sensors and Interfaces, Jun 2013, Bari, Italy. 5th IEEE International Workshop on Advances in Sensors and Interfaces, pp.75-80, 2013.
  29. A toolkit to demystify CMOS Active Pixel Sensors
    Jean-Marc Galliere, Jérôme Boch
    MSE: Microelectronic Systems Education, Jun 2013, Austin, TX, United States. IEEE, IEEE International Conference on Microelectronic Systems Education, 2013. <10.1109/MSE.2013.6566696>
  30. A Bulk Built-in Sensor for Detection of Fault Attacks
    Rodrigo Possamai Bastos, Franck Sill Torres, Jean Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
    HOST: Hardware-Oriented Security and Trust, Jun 2013, Austin, TX, United States. 6th Annual IEEE International Symposium on Hardware-Oriented Security and Trust, pp.51-54, 2013.
  31. Identification of Hardware Trojans triggering signals
    Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
    First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France. 2013. <http://trudevice.com/Workshop/>
  32. Analyzing Resistive-Open Defects in SRAM Core-Cell under the Effect of Process Variability
    Ioana Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Nabil Badereddine
    ETS: European Test Symposium, May 2013, Avignon, France. Test Symposium (ETS), 2013 18th IEEE European, pp.1-6, 2013.
  33. Computing Detection Probability of Delay Defects in Signal Line TSVs
    Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
    ETS: European Test Symposium, May 2013, Avignon, France. Test Symposium (ETS), 2013 18th IEEE, 2013. <10.1109/ETS.2013.6569349>
  34. Analyzing resistive-open defects in SRAM core-cell under the effect of process variability
    Ioana Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Nabil Badereddine
    ETS: European Test Symposium, May 2013, Avignon, France. 18th IEEE European Test Symposium, 2013. <10.1109/ETS.2013.6569373>
  35. A Built-in Scheme for Testing and Repairing Voltage Regulators of Low-Power SRAMs
    Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Nabil Badereddine
    VTS: VLSI Test Symposium, Apr 2013, Berkeley, CA, United States. IEEE 31st VLSI Test Symposium, pp.1-6, 2013.
  36. Self-test and self-calibration of a MEMS convective accelerometer
    Ahmed Rekik, Florence Azaïs, Frédérick Mailly, Pascal Nouet, Mohamed Masmoudi
    DTIP: Design, Test, Integration & Packaging of MEMS/MOEMS, Apr 2013, Barcelona, Spain. Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2013 on, Barcelona, 2013, pp. 1-4. keywords: ,, pp.239-242, 2013.
  37. Fast and Accurate Electro-Thermal Analysis of Three-Dimensional Power Delivery Networks
    Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
    EuroSimE: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, Apr 2013, Wroclaw, Poland. Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2013 14th International Conference on, pp.1-4, 2013.
  38. Pre-characterization Procedure for a Mixed Mode Simulation of IR-Drop Induced Delays
    Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker
    LATW: Latin American Test Workshop, Apr 2013, Cordoba, Argentina. 14th Latin American Test Workshop, 2013. <10.1109/LATW.2013.6562657>
  39. Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures
    Ioana Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Nabil Badereddine
    DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2013, Abu Dhabi, United Arab Emirates. 8th International Conference on Design Technology of Integrated Systems in Nanoscale Era, pp.39-44, 2013.
  40. Test Solution for Data Retention Faults in Low-Power SRAMs
    Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Nabil Badereddine
    EDA Association. DATE: Design, Automation and Test in Europe, Mar 2013, Grenoble, France. Design, Automation & Test in Europe Conference & Exhibition, pp.442-447, 2013.
  41. Effect-Cause Intra-Cell Diagnosis at Transistor Level
    Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Etienne Auvray
    ISQED: International Symposium on Quality Electronic Design, Mar 2013, Santa Clara, CA, United States. 14th International Symposium on Quality Electronic Design, pp.460-467, 2013.

Mots-clés

Fiabilité, Circuits et Systèmes Intégrés, Numérique, Analogique, RF, Circuits Sécurisés, Confiance matérielle, Sécurité matérielle, Technologies émergentes, Environnement spatial et radiatif, Méthodologies et Outils de Conception, Génération de tests, Simulation de fautes, Diagnostic de pannes, Attaques du matériel, Contre-mesures, Test, Modélisation

Dernière mise à jour le 27/06/2018