European scalable and power efficient HPC platform based on low-power embedded technology
Energy efficiency is already a primary concern for the design of any computer system and it is unanimously recognized that future Exascale systems will be strongly constrained by their power consumption. This is why the Mont-Blanc project, which was launched since October 2011, has set itself to design a new type of computer architecture capable of setting future global High-Performance Computing (HPC) standards that will deliver Exascale performance while using 15 to 30 times less energy.
The third phase of the Mont-Blanc project (i.e.Mont-Blanc 3) started in October 2015: it is coordinated by Bull, the Atos brand for technology products and software, and has a budget of 7.9 million Euros, funded by the European Commission under the Horizon 2020 programme. The third phase adopts a co-design approach to ensure that hardware and system innovations are readily translated into benefits for HPC applications. It aims at designing a new high-end HPC platform that is able to deliver a new level of performance/energy ratio when executing real applications.
At CNRS, we are involved in 3 main work-packages. A brief description of the work packages is given below.
- WP3. Balanced architecture: The aim of this work package is to investigate non-volatile memory technologies such as magnetic memories (MRAMs). The investigations will be made on the basis of state-of-the-art technology information such as read/ write energy and latency that will be modeled and embedded into higher-level simulator such as Gem5. Furthermore, techniques to reduce the area and power consumption in Network-on-Chip will be explored. Areas such us optimization of input buffered routers, centralized buffered solutions and bufferless routers will be investigated.
- WP4. Compute Efficiency: The aim is to explore the use of different computing nodes (i.e. ARM bigLITTLE) in the system for energy efficiency.
- WP5. Simulation tools: Performance estimation of large scale systems using trace-driving simulation approach will be carried out in this work package. The trace-driven approach is fast, scalable and sensitive for exploring different architectural parameters of multicore systems.